NEC UPA1790G

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA1790
SWITCHING
N-AND P-CHANNEL POWER MOS FET
INDUSTRIAL USE
PACKAGE DRAWING (Unit : mm)
DESCRIPTION
This product is N-and P-Channel MOS Field Effect Transistor
8
designed for motor driver applications.
5
FEATURES
N-Channel
1 ; Source 1
2 ; Gate 1
7,8 ; Drain 1
P-Channel
3 ; Source 2
4 ; Gate 2
5,6 ; Drain 2
• Dual chip type
• Low on-resistance
N-Channel RDS(on)1 = 0.12 Ω TYP. (VGS = 10 V, ID = 0.5 A)
4.4
5.37 MAX.
0.8
+0.10
–0.05
1.44
0.05 MIN.
RDS(on)2 = 0.74 Ω TYP. (VGS = –4 V, ID = –0.35 A)
6.0 ±0.3
4
0.15
P-Channel RDS(on)1 = 0.45 Ω TYP. (VGS = –10 V, ID = –0.35 A)
1.8 MAX.
RDS(on)2 = 0.19 Ω TYP. (VGS = 4 V, ID = 0.5 A)
1
• Low input capacitance
N-Channel Ciss = 180 pF TYP.
0.5 ±0.2
0.10
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
P-Channel Ciss = 230 pF TYP.
• Built-in G-S protection diode
• Small and surface mount package (Power SOP8)
EQUIVARENT CIRCUIT
ORDERING INFORMATION
Drain
PART NUMBER
PACKAGE
µPA1790G
Power SOP8
Drain
Body
Diode
Gate
Gate
Protection
Diode
Source
Gate
Protection
Diode
N-Channel
Remark
Body
Diode
Gate
Source
P-Channel
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
G14320EJ1V0DS00 (1st edition)
Date Published May 1999 NS CP(K)
Printed in Japan
©
1999
µ PA1790
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
PARAMETER
SYMBOL
N-CHANNEL
P-CHANNEL
UNIT
Drain to Source Voltage (VGS = 0 V)
VDSS
60
–60
V
Gate to Source Voltage (VDS = 0 V)
VGSS
±20
# 20
V
Drain Current (DC)
ID(DC)
±1.0
# 0.7
A
ID(pulse)
±4.0
# 2.8
A
Drain Current (pulse)
Note1
Total Power Dissipation (1 unit)
Note2
PT
1.7
W
Total Power Dissipation (2 unit)
Note2
PT
2.0
W
Channel Temperature
Tch
150
°C
Storage Temperature
Tstg
–55 to +150
°C
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1 %
2
2. Mounted on ceramic substrate of 2000 mm x 2.25 mm
2
Data Sheet G14320EJ1V0DS00
µ PA1790
ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.)
N-CHANNEL
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
RDS(on)1
VGS = 10 V, ID = 0.5 A
0.12
0.26
Ω
RDS(on)2
VGS = 4 V, ID = 0.5 A
0.19
0.34
Ω
VGS(off)
VDS = 10 V, ID = 1 mA
1.0
1.7
2.5
V
Forward Transfer Admittance
| yfs |
VDS = 10 V, ID = 0.5 A
1.0
1.7
Drain Leakage Current
IDSS
VDS = 60 V, VGS = 0 V
10
µA
Gate to Source Leakage Current
IGSS
VGS = ±16 V, VDS = 0 V
±10
µA
Input Capacitance
Ciss
VDS = 10 V
180
pF
Output Capacitance
Coss
VGS = 0 V
100
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
35
pF
Turn-on Delay Time
td(on)
ID = 0.5 A
1
ns
VGS(on) = 10 V
1.4
ns
td(off)
VDD = 30 V
23
ns
tf
RG = 10 Ω
17
ns
Total Gate Charge
QG
ID = 1.0 A
8
nC
Gate to Source Charge
QGS
VDD = 48 V
1
nC
Gate to Drain Charge
QGD
VGS = 10 V
3.5
nC
VF(S-D)
IF = 1.0 A, VGS = 0 V
0.75
V
Reverse Recovery Time
trr
IF = 1.0 A, VGS = 0 V
30
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A / µs
33
nC
Drain to Source On-state Resistance
Gate to Source Cut-off Voltage
Rise Time
tr
Turn-off Delay Time
Fall Time
Body Diode Forward Voltage
TEST CIRCUIT 1 SWITCHING TIME
TEST CIRCUIT 2 GATE CHARGE
D.U.T.
D.U.T.
RL
RG
RG = 10 Ω
PG.
S
VGS
VGS
Wave Form
0
VGS(on)
10 %
IG = 2 mA
RL
50 Ω
VDD
90 %
PG.
VDD
90 %
ID
90 %
ID
VGS
0
ID
10 %
0 10 %
Wave Form
τ
τ = 1µ s
Duty Cycle ≤ 1 %
tr
td(on)
ton
td(off)
tf
toff
Data Sheet G14320EJ1V0DS00
3
µ PA1790
P-CHANNEL
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
RDS(on)1
VGS = –10 V, ID = –0.35 A
0.45
0.6
Ω
RDS(on)2
VGS = –4 V, ID = –0.35 A
0.74
1.1
Ω
VGS(off)
VDS = –10 V, ID = –1 mA
–1.0
–1.7
–2.5
V
Forward Transfer Admittance
| yfs |
VDS = –10 V, ID = –0.35 A
5.0
Drain Leakage Current
IDSS
VDS = –60 V, VGS = 0 V
–10
µA
Gate to Source Leakage Current
IGSS
VGS = # 16 V, VDS = 0 V
# 10
µA
Input Capacitance
Ciss
VDS = –10 V
230
pF
Output Capacitance
Coss
VGS = 0 V
100
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
25
pF
Turn-on Delay Time
td(on)
ID = –0.35 A
1.9
ns
VGS(on) = –10 V
1.7
ns
VDD = –30 V
30
ns
tf
RG = 10 Ω
15
ns
Total Gate Charge
QG
ID = –0.7 A
7.6
nC
Gate to Source Charge
QGS
VDD = –48 V
1
nC
Gate to Drain Charge
QGD
VGS = –10 V
2
nC
Drain to Source On-state Resistance
Gate to Source Cut-off Voltage
Rise Time
tr
Turn-off Delay Time
td(off)
Fall Time
Body Diode Forward Voltage
S
VF(S-D)
IF = 0.7 A, VGS = 0 V
0.85
V
Reverse Recovery Time
trr
IF = 0.7 A, VGS = 0 V
58
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A / µs
130
nC
TEST CIRCUIT 1 SWITCHING TIME
TEST CIRCUIT 2 GATE CHARGE
D.U.T.
D.U.T.
RL
RG
RG = 10 Ω
PG.
VGS
VGS
Wave Form
0
PG.
90 %
90 %
ID
VGS
0
ID
10 %
0 10 %
Wave Form
τ
τ = 1µ s
Duty Cycle ≤ 1 %
tr
td(on)
ton
RL
50 Ω
VDD
90 %
VDD
ID
4
VGS(on)
10 %
IG = 2 mA
td(off)
tf
toff
Data Sheet G14320EJ1V0DS00
µ PA1790
[MEMO]
Data Sheet G14320EJ1V0DS00
5
µ PA1790
[MEMO]
6
Data Sheet G14320EJ1V0DS00
µ PA1790
[MEMO]
Data Sheet G14320EJ1V0DS00
7
µ PA1790
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
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M7 98. 8