NEC UPA1770

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA1770
SWITCHING
DUAL P-CHANNEL POWER MOS FET
INDUSTRIAL USE
ORDERING INFORMATION
DESCRIPTION
The µPA1770 is a P-channel MOS Field Effect
Transistor designed for power management
applications of portable machines.
PART NUMBER
PACKAGE
µPA1770G
Power SOP8
FEATURES
• Dual chip type
• Low on-resistance
RDS(on)1 = 37 mΩ MAX. (VGS = –4.5 V, ID = –3.0 A)
RDS(on)2 = 39 mΩ MAX. (VGS = –4.0 V, ID = –3.0 A)
RDS(on)3 = 59 mΩ MAX. (VGS = –2.5 V, ID = –3.0 A)
• Low input capacitance
Ciss = 1300 pF TYP.
• Built-in G-S protection diode
• Small and surface mount package (Power SOP8)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
Drain to Source Voltage
VDSS
–20
V
Gate to Source Voltage
VGSS
! 12
V
Drain Current (DC)
ID(DC)
! 6.0
A
ID(pulse)
! 24
A
Total Power Dissipation (1 unit)
Note2
PT
0.40
W
Total Power Dissipation (2 unit)
Note2
PT
0.75
W
Total Power Dissipation (1 unit)
Note3
PT
1.7
W
Total Power Dissipation (2 unit)
Note3
PT
2.0
W
Channel Temperature
Tch
150
°C
Storage Temperature
Tstg
–55 to +150
°C
Drain Current (pulse)
★
★
Note1
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1 %
2. Mounted on FR4 Board of 1600 mm x 1.6 mm, Drain Pad size : 4.5 mm x 35 µm, TA = 25°C
2
★
2
2
3. Mounted on ceramic substrate of 1200 mm x 2.2 mm, TA = 25°C
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
G14055EJ1V0DS00 (1st edition)
Date Published November 1999 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
©
1999
µ PA1770
★
ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
Drain to Source On-state Resistance
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
RDS(on)1
VGS = –4.5 V, ID = –3.0 A
28
37
mΩ
RDS(on)2
VGS = –4.0 V, ID = –3.0 A
29.5
39
mΩ
RDS(on)3
VGS = –2.5 V, ID = –3.0 A
44
59
mΩ
VGS(off)
VDS = –10 V, ID = 1 mA
–0.5
–1.0
–1.5
V
Forward Transfer Admittance
| yfs |
VDS = –10 V, ID = –3.0 A
5.0
11
Drain Leakage Current
IDSS
VDS = –20 V, VGS = 0 V
–1
µA
Gate to Source Leakage Current
IGSS
VGS = ! 12 V, VDS = 0 V
! 10
µA
Input Capacitance
Ciss
VDS = –10 V
1300
pF
Output Capacitance
Coss
VGS = 0 V
325
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
155
pF
Turn-on Delay Time
td(on)
ID = –3.0 A
25
ns
VGS(on) = –4.5 V
110
ns
VDD = –10 V
130
ns
tf
RG = 10 Ω
140
ns
Total Gate Charge
QG
ID = –6.0 A
11
nC
Gate to Source Charge
QGS
VDD = –16 V
2.0
nC
Gate to Drain Charge
QGD
VGS = –4.5 V
4.0
nC
VF(S-D)
IF = 6.0 A, VGS = 0 V
0.8
V
Reverse Recovery Time
trr
IF = 6.0 A, VGS = 0 V
60
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A / µs
40
nC
Gate to Source Cut-off Voltage
Rise Time
tr
Turn-off Delay Time
td(off)
Fall Time
Body Diode Forward Voltage
TEST CIRCUIT 1 SWITCHING TIME
TEST CIRCUIT 2 GATE CHARGE
D.U.T.
D.U.T.
RL
RG
RG = 10 Ω
PG.
VGS
VGS
Wave Form
0
PG.
VDD
ID
Wave Form
90 %
90 %
τ = 1µ s
Duty Cycle ≤ 1 %
10 %
0 10 %
tr
td(on)
ton
IG = 2 mA
RL
50 Ω
VDD
90 %
ID
τ
2
VGS(on)
10 %
ID
VGS
0
S
td(off)
tf
toff
Data Sheet G14055EJ1V0DS00
µ PA1770
TYPICAL CHARACTERISTICS(TA = 25 °C, All terminals are connected.)
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
rth(t) - Transient Thermal Resistance - ˚C/W
1000
Rth(ch-A) = 73.5 ˚C/W
100
10
1
0.1
0.01
0.001
0.00001
Mounted on ceramic
Single Pulse
substrate of 1200 mm 2 × 2.2 mm
Single Pulse , 1 unit
0.0001
0.001
0.01
0.1
1
10
100
1000
100
10
VDS = −10 V
Pulsed
TA = −50˚C
TA = −25˚C
TA = 25˚C
TA = 75˚C
TA = 125˚C
TA = 150˚C
1
0
−0.1
−1
−10
−100
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
80
Pulsed
VGS = −2.5 V
60
VGS = −4.0 V
40
VGS = −4.5 V
20
0
−0.1
−1
−10
−100
VGS(off) - Gate to Source Cut-off Voltage - V
|yfs| - Forward Transfer Admittance - S
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
RDS(on) - Drain to Source On-state Resistance - mΩ
PW - Pulse Width - s
RDS(on) - Drain to Source On-state Resistance - mΩ
★
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
80
Pulsed
70
ID = −6.0 A
60
50
40 ID = −3.0 A
30
20
10
0
0
−2
−4
−6
−8
−10
VGS - Gate to Source Voltage - V
GATE TO SOURCE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
−1.5
VDS = −10 V
ID = 1 mA
−1.0
−0.5
−0
−75 −50 −25
ID - Drain Current - A
0
25
50
75
100 125 150
Tch - Channel Temperature - ˚C
Data Sheet G14055EJ1V0DS00
3
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
100.0
100
VF(S−D) - Diode Forward Current - A
80.0
60.0
VGS = −2.5 V
VGS = −4.0 V
40.0
VGS = −4.5 V
20.0
0.0
−50
ID = −3.0 A
−25
0
25
50
75
100
VGS = −2.5 V
10
VGS = 0 V
1
0.1
0.01
0.00
125 150
0.50
Tch - Channel Temperature - ˚C
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
SWITCHING CHARACTERISTICS
Coss
100
Crss
10
1
−0.1
VGS = 0 V
f = 1 MHz
−1
−10
td(on), tr, td(off), tf - Switching Time - ns
1000
Ciss
1000
td(off)
100
tf
tr
td(on)
10
VDD = −16 V
VGS = −4.5V
RG = 10 Ω
1
−0.1
−100
−1
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
trr - Reverse Recovery Time - ns
di/dt = 100 A/ns
VGS = 0 V
1000
100
10
1
10
100
VDS - Drain to Source Voltage - V
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
1
0.1
−30
−6
−25
−5
VGS
−20
VDD = −16 V
VDD = −10 V
VDD = −4 V
−15
−2
−5
0
0
−1
VDS
2
4
6
8
10
12
QG - Gate Charge - nC
Data Sheet G14055EJ1V0DS00
−4
−3
−10
ID - Drain Current - A
4
−10
ID - Drain Current - A
VDS - Drain to Source Voltage - V
10000
1.50
1.00
VSD - Source to Drain Voltage - V
10000
Ciss, Coss, Crss - Capacitance - pF
Pulsed
14
0
16
VGS - Gate to Source Voltage - V
RDS(on) - Drain to Source On-state Resistance - mΩ
µ PA1770
µ PA1770
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
PT - Total Power Dissipation - W
dT - Percentage of Rated Power - %
2.8
100
80
60
40
20
Mounted on ceramic
substrate of
1200 mm 2 × 2.2 mm
2.4
2 unit
2.0
1 unit
1.6
1.2
0.8
0.4
0
0
0
20
40
60
80
100 120 140 160
0
TA - Ambient Temperature - ˚C
−30
PW
TA = 25 ˚C
Single Pulse
ID - Drain Current - A
1
s
m
10
PW
m
0
10
s
=
(a RDS
t V (o
n)
G
L
S
= im
−4 ite
.5 d
V)
µs
=
=
ID(DC)
m
s
Po
we
−1
100 120 140 160
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
Pulsed
VGS = −4.5 V
−20
VGS = −4.0 V
−15
VGS = −2.5 V
−10
d
ite
Lim
−0.1
0
80
−5
n
Mounted on ceramic
substrate of
2
1200 mm × 2.2 mm
−0.1 1unit
tio
ipa
iss
rD
ID - Drain Current - A
0
10
PW
PW
−10
60
−25
=
ID(pulse)
40
TA - Ambient Temperature - ˚C
FORWARD BIAS SAFE OPERATING AREA
−100
20
−1
−10
−100
−0
−0
−0.2
−0.4
−0.6
−0.8
−1.0
−1.2
VDS - Drain to Source Voltage - V
VDS - Drain to Source Voltage - V
FORWARD TRANSFER CHARACTERISTICS
ID - Drain Current - A
−100
VDS = −10 V
Pulsed
−10
−1
−0.1
TA = 150˚C
TA = 125˚C
TA = 75˚C
−0.01
−0.001
0
TA = 25˚C
TA = −25˚C
TA = −50˚C
−1
−2
−3
VGS - Gate to Source Voltage - V
Data Sheet G14055EJ1V0DS00
5
µ PA1770
PACKAGE DRAWING (Unit : mm)
Power SOP8
8
5
EQUIVALENT CIRCUIT
1 : Source 1
2 : Gate 1
7, 8 : Drain 1
(1/2 circuit)
3 : Source 2
4 : Gate 2
5, 6 : Drain 2
4.4
0.15
Remark
6
4
5.37 MAX.
1.27 0.78 MAX.
0.40
+0.10
–0.05
Body
Diode
Gate
6.0 ±0.3
0.8
Gate
Protection
Diode
+0.10
–0.05
1.44
0.05 MIN.
1.8 MAX.
1
Drain
Source
0.5 ±0.2
0.10
0.12 M
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
Data Sheet G14055EJ1V0DS00
µ PA1770
[MEMO]
Data Sheet G14055EJ1V0DS00
7
µ PA1770
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
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rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
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parties arising from the use of these circuits, software, and information.
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the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
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"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
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systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
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support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
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M7 98. 8