ETC UPD16718

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16718
480/420-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64-GRAY SCALES)
DESCRIPTION
The µ PD16718 is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input
is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000
colors by output of 64 values γ -corrected by an internal D/A converter and 7-by-2 external power modules. Because
the output dynamic range is as large as VSS2 + 0.1 V to VDD2 – 0.1 V, level inversion operation of the LCD’s common
electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line
inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit
whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a
maximum clock frequency of 57 MHz when driving at 2.5 V, this driver is applicable to SXGA+/UXGA-standard TFTLCD panels.
FEATURES
• CMOS level input (2.5 to 3.6 V)
• 480/420 Outputs
• Input of 6 bits (gray scale data) by 6 dots
• Capable of outputting 64 values by means of 7-by-2 external power modules (14 units) and a D/A converter (RDAC)
• Logic power supply voltage (VDD1): 2.5 to 3.6 V
• Driver power supply voltage (VDD2): 10.0 to 12.5 V
• Output dynamic range VSS2 + 0.1 V to VDD2 – 0.1 V
• High-speed data transfer: fCLK = 57 MHz (internal data transfer speed when operating at VDD1 = 2.5 V
• Apply for dot-line inversion, n-line inversion and column line inversion
• Output Voltage polarity inversion function (POL)
• Display data inversion function (capable of controlling by each input port) (POL21, POL22)
• Current consumption control function (LPC)
• TCP/COF package
★ ORDERING INFORMATION
Part Number
Package
µ PD16718N-xxx
µ PD16718NL-xxx
TCP (TAB package)
COF (Chip on Film) package
Remark Consult an our sales representative regarding the TCP/COF.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15423EJ1V0DS00 (1st edition)
Date Published December 2001 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
©
2001
µ PD16718
★ 1. BLOCK DIAGRAM
STHR
R,/L
CLK
Osel
STB
STHL
VDD1
VSS1
80-bit bidirectional shift register
C1
C2
C79
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
POL21
POL22
C80
Data register
Latch
POL
VDD2
Level shifter
VSS2
V0 to V13
D/A converter
Voltage follower output
LPC
S1
S2
S3
S480
Remark /xxx indicates active low signal.
★ 2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S1
V7
S479
7
V0
V6
S2
Multiplexer
6-bit D/A converter
7
V13
POL
2
Data Sheet S15423EJ1V0DS
S480
µ PD16718
3. PIN CONFIGURATION (µ PD16718) (Copper Foil Surface, Face-up)
STHL
D55
D54
D53
D52
D51
D50
D45
D44
D43
D42
D41
D40
D35
D34
D33
D32
D31
D30
Osel
VDD1
R,/L
V13
V12
V11
V10
V9
V8
V7
VDD2
VSS2
V6
V5
V4
V3
V2
V1
V0
VSS1
LPC
CLK
STB
POL
POL21
POL22
D25
D24
D23
D22
D21
D20
D15
D14
D13
D12
D11
D10
D05
D04
D03
D02
D01
D00
STHR
S480
S479
S478
S477
Copper Foil
Surface
S4
S3
S2
S1
Remark This figure does not specify the TCP/COF package.
Data Sheet S15423EJ1V0DS
3
µ PD16718
4. PIN FUNCTIONS
(1/2)
Pin Symbol
Pin Name
S1 to S480
Driver
D00 to D05
Display data
I/O
Output
Input
Description
The D/A converted 64-gray-scale analog voltage is output.
The display data is input with a width of 36 bits, viz., the gray scale data (6 bits)
D10 to D15
by 6 dots (2 pixels).
D20 to D25
DX0: LSB, DX5: MSB
D30 to D35
D40 to D45
D50 to D55
R,/L
Shift direction control
Input
Refers to the shift direction control. The shift directions of the shift registers are
as follows.
R,/L = H: STHR input, S1 → S480, STHL output
R,/L = L: STHL input, S480 → S1, STHR output
This pin is pulled up to power supply VDD1 inside IC.
STHR
Right shift start pulse
I/O
These refer to the start pulse I/O pins when driver ICs are connected in cascade.
Loading of display data starts when H is read at the rising edge of CLK.
R,/L = H (right shift): STHR input, STHL output
STHL
Left shift start pulse
I/O
R,/L = L (left shift): STHL input, STHR output
A high level should be input as the pulse of one cycle of the clock signal.
If the start pulse input is more than 2 CLK, the first 1 CLK of the high-level input
is valid.
CLK
Shift clock
Input
Refers to the shift register’s shift clock input. The display data is loaded into the
data register at the rising edge.
At the rising edge of the 80(70) clock after the start pulse input, the start pulse
output reaches the high level, thus becoming the start pulse of the next-level
driver. If 82(72)-clock pulses are input after input of the start pulse, input of
display data is halted automatically. The contents of the shift register are
cleared at the STB’s rising edge.
( ) indicates 420 output.
STB
Latch
Input
The contents of the data register are transferred to the latch circuit at the rising
edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It
is necessary to ensure input of one pulse per horizontal period.
POL
Polarity
Input
POL = L : The S2n–1 output uses V0 to V6 as the reference supply. The S2n output
uses V7 to V13 as the reference supply.
POL = H : The S2n–1 output uses V7 to V13 as the reference supply. The S2n
output uses V0 to V6 as the reference supply.
S2n-1 indicates the odd output: and S2n indicates the even output. Input of the
POL signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge.
!
POL21,
Data inversion
Input
POL22
Data inversion can invert when display data is loaded.
POL21: Invert/not invert of display data D00 to D05, D10 to D15, D20 to D25.
POL22: Invert/not invert of display data D30 to D35, D40 to D45, D50 to D55.
POL21, POL22 = H: Display data is inverted inside the µ PD16718.
POL21, POL22 = L: Display data is not inverted.
Osel
Number of output pins
select
4
input
Osel = H: driver output = 480 ch
Osel = L or open: driver output = 420 ch (Output pins S211 to S270 are invalid)
This pin is pulled down to power supply VDD1 inside IC.
Data Sheet S15423EJ1V0DS
µ PD16718
(2/2)
Pin Symbol
LPC
Pin Name
Low power control
I/O
Input
Description
The current consumption is lowered by controlling the constant current source of
the output amplifier and reduced VDD2 of normal current.
LPC = H or open: Normal power mode
LPC = L: Low power mode (about 3/4 of the normal current consumption)
This pin is pulled up to the VDD1 power supply inside IC.
V0 to V13
γ -corrected power
−
supplies
Input the γ -corrected power supplies from outside by using operational amplifier.
Make sure to maintain the following relationships. During the gray scale voltage
output, be sure to keep the gray scale level power supply at a constant level.
VDD2 − 0.1 V ≥ V0 > V1 > V2 > V3 > V4 > V5 > V6 ≥ V7 > V8 > V9 > V10 > V11 > V12 >
V13 ≥ VSS2 + 0.1 V and 0.45 x VDD2 ≤ V6 = V7 ≤ 0.55 x VDD2 or
VDD2 − 0.1 V ≥ V6 > V5 > V4 > V3 > V2 > V1 > V0 ≥ V13 > V12 > V11 > V10 > V9 > V8 >
V7 ≥ VSS2 + 0.1 V and 0.45 x VDD2 ≤ V0 = V13 ≤ 0.55 x VDD2
VDD1
Logic power supply
−
2.5 to 3.6 V
VDD2
Driver power supply
−
10.0 to 12.5 V
VSS1
Logic ground
−
Grounding
VSS2
Driver ground
−
Grounding
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V13 in that order.
Reverse this sequence to shut down. (Simultaneous power application to VDD2 and V0 to V9 is
possible.)
2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between
VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of a
bypass capacitor of about 0.01 µF is also advised between the γ -corrected power supply
terminals (V0, V1, V2, ···, V13) and VSS2.
Data Sheet S15423EJ1V0DS
5
µ PD16718
5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
This product incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively
gray scale voltages of differing polarity with respect to the LCD’s counter electrode (common electrode) voltage. The
D/A converter consists of ladder resistors and switches.
The ladder resistors (r0 to r62) are designed so that the ratio of LCD panel γ -compensated voltages to V0’ to V63’
and V0’’ to V63’’ is almost equivalent. For the 2 sets of seven γ -compensated power supplies, V0 to V6 and V7 to V13,
respectively, input gray scale voltages of the same polarity with respect to the common voltage. When fine-gray scale
voltage precision is not necessary, there is no need to connect a voltage follower circuit to the γ -compensated power
supplies V0 to V6 and V7 to V13.
Figure 5−1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and
VSS2, common electrode potential VCOM, and γ -corrected voltages V0 to V13 and the input data. Be sure to maintain
the voltage relationships as follows:
VDD2 − 0.1 V ≥ V0 > V1 > V2 > V3 > V4 > V5 > V6 ≥ V7 > V8 > V9 > V10 > V11 > V12 > V13 ≥ VSS2 + 0.1 V and
0.45 x VDD2 ≤ V6 = V7 ≤ 0.55 x VDD2 or
VDD2 − 0.1 V ≥ V6 > V5 > V4 > V3 > V2 > V1 > V0 ≥ V13 > V12 > V11 > V10 > V9 > V8 > V7 ≥ VSS2 + 0.1 V and
0.45 x VDD2 ≤ V0 = V13 ≤ 0.55 x VDD2
positive side > 0.5 VDD2 − 0.5V, negative side > 0.5 VDD2 + 0.5 V.
Figures 5−2 and 5−3 show the relationship between input data and output voltage. This driver IC is designed for
only single-sided mounting
Figure 5−
−1. Relationship between Input Data and γ - corrected Power Supply
VDD2
0.1 V
V0
V1
14
V2
17
V3
16
V4
14
V5
V6
0.5 VDD2
Split interval
V7
V8
14
V9
16
V10
17
V11
14
V12
V13
0.1 V
VSS2
00 01
0F
1F
Input data (HEX)
6
Data Sheet S15423EJ1V0DS
30
3E 3F
µ PD16718
Figure 5–2. γ -corrected Voltages and Ladder Resistors Ratio
V0
r0
V1
r1
V63'
V62'
V7
r62
V8
V61'
V2''
r60
V60'
r59
r3
r14
V48'
r16
V14''
r48
V9
V16''
r46
r17
r17
r46
V16'
V15'
r16
V11
r15
V47''
V48''
V49''
V14'
r14
r49
r60
r61
V15''
r47
V47'
V4
r48
V3''
r49
V49'
r47
V1''
r61
r2
r15
V2
V0''
r2
V2'
V61''
r1
V5
r62
V1'
V12
r0
V62''
V6
V0'
V13
V63''
rn
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
r32
r33
r34
r35
r36
r37
r38
r39
r40
r41
r42
r43
r44
r45
r46
r47
r48
r49
r50
r51
r52
r53
r54
r55
r56
r57
r58
r59
r60
r61
r62
Ratio
7.0
5.0
5.0
4.0
3.0
2.5
2.5
2.5
2.0
2.0
1.8
1.8
1.7
1.7
1.7
1.6
1.6
1.6
1.6
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.6
1.6
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
5.0
Caution There is no connection between V6 and V7 terminal in the chip.
Data Sheet S15423EJ1V0DS
7
µ PD16718
Figure 5–3. Relationship between Input Data and Output Voltage (POL21, POL22 = L)
(Output Voltage 1) VDD2 – 0.1 V ≥ V0 > V1 > V2 > V3 > V4 > V5 > V6 ≥ 0.5 VDD2 – 0.5 V
(Output Voltage 2) 0.5 VDD2 + 0.5 V ≥ V7 > V8 > V9 > V10 > V11 > V12 > V13 ≥ VSS2 + 0.1 V
Input Data
Output Voltage1
Output Voltage2
V0''
V7
V8
V9+(V8-V9)×
V9+(V8-V9)×
V9+(V8-V9)×
V9+(V8-V9)×
V9+(V8-V9)×
V9+(V8-V9)×
V9+(V8-V9)×
V9+(V8-V9)×
V9+(V8-V9)×
V9+(V8-V9)×
V9+(V8-V9)×
V9+(V8-V9)×
V9+(V8-V9)×
V9
V10+(V9-V10)×
V10+(V9-V10)×
V10+(V9-V10)×
V10+(V9-V10)×
V10+(V9-V10)×
V10+(V9-V10)×
V10+(V9-V10)×
V10+(V9-V10)×
V10+(V9-V10)×
V10+(V9-V10)×
V10+(V9-V10)×
V10+(V9-V10)×
V10+(V9-V10)×
V10+(V9-V10)×
V10+(V9-V10)×
V10
V11+(V10-V11)×
V11+(V10-V11)×
V11+(V10-V11)×
V11+(V10-V11)×
V11+(V10-V11)×
V11+(V10-V11)×
V11+(V10-V11)×
V11+(V10-V11)×
V11+(V10-V11)×
V11+(V10-V11)×
V11+(V10-V11)×
V11+(V10-V11)×
V11+(V10-V11)×
V11+(V10-V11)×
V11+(V10-V11)×
V11+(V10-V11)×
V11
V12+(V11-V12)×
V12+(V11-V12)×
V12+(V11-V12)×
V12+(V11-V12)×
V12+(V11-V12)×
V12+(V11-V12)×
V12+(V11-V12)×
V12+(V11-V12)×
V12+(V11-V12)×
V12+(V11-V12)×
V12+(V11-V12)×
V12+(V11-V12)×
V12+(V11-V12)×
V1
V1''
V2''
V3''
V4''
V5''
V6''
V7''
V8''
V9''
V10''
V11''
V12''
V13''
V14''
V15''
V16''
V17''
V18''
V19''
V20''
V21''
V22''
V23''
V24''
V25''
V26''
V27''
V28''
V29''
V30''
V31''
V32''
V33''
V34''
V35''
V36''
V37''
V38''
V39''
V40''
V41''
V42''
V43''
V44''
V45''
V46''
V47''
V48''
V49''
V50''
V51''
V52''
V53''
V54''
V55''
V56''
V57''
V58''
V59''
V60''
V61''
V62''
V0
V63''
V13
00H
V0'
V6
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
V5
V5+(V4-V5)×
V5+(V4-V5)×
V5+(V4-V5)×
V5+(V4-V5)×
V5+(V4-V5)×
V5+(V4-V5)×
V5+(V4-V5)×
V5+(V4-V5)×
V5+(V4-V5)×
V5+(V4-V5)×
V5+(V4-V5)×
V5+(V4-V5)×
V5+(V4-V5)×
V4
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V4+(V3-V4)×
V3
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V3+(V2-V3)×
V2
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
V2+(V1-V2)×
3EH
V1'
V2'
V3'
V4'
V5'
V6'
V7'
V8'
V9'
V10'
V11'
V12'
V13'
V14'
V15'
V16'
V17'
V18'
V19'
V20'
V21'
V22'
V23'
V24'
V25'
V26'
V27'
V28'
V29'
V30'
V31'
V32'
V33'
V34'
V35'
V36'
V37'
V38'
V39'
V40'
V41'
V42'
V43'
V44'
V45'
V46'
V47'
V48'
V49'
V50'
V51'
V52'
V53'
V54'
V55'
V56'
V57'
V58'
V59'
V60'
V61'
V62'
3FH
V63'
3.0
5.9
8.7
11.4
14.0
16.5
18.9
21.2
23.4
25.5
27.5
29.4
31.2
/
/
/
/
/
/
/
/
/
/
/
/
/
32.9
32.9
32.9
32.9
32.9
32.9
32.9
32.9
32.9
32.9
32.9
32.9
32.9
1.6
3.2
4.8
6.3
7.8
9.3
10.8
12.3
13.8
15.3
16.8
18.3
19.8
21.3
22.8
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
24.3
24.3
24.3
24.3
24.3
24.3
24.3
24.3
24.3
24.3
24.3
24.3
24.3
24.3
24.3
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.0
13.5
15.0
16.5
18.0
19.5
21.0
22.6
24.2
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
25.9
25.9
25.9
25.9
25.9
25.9
25.9
25.9
25.9
25.9
25.9
25.9
25.9
25.9
25.9
25.9
1.7
3.4
5.1
6.9
8.7
10.7
12.7
15.2
17.7
20.2
23.2
27.2
32.2
/
/
/
/
/
/
/
/
/
/
/
/
/
37.2
37.2
37.2
37.2
37.2
37.2
37.2
37.2
37.2
37.2
37.2
37.2
37.2
29.9
27.0
24.2
21.5
18.9
16.4
14.0
11.7
9.5
7.4
5.4
3.5
1.7
/
/
/
/
/
/
/
/
/
/
/
/
/
32.9
32.9
32.9
32.9
32.9
32.9
32.9
32.9
32.9
32.9
32.9
32.9
32.9
22.7
21.1
19.5
18.0
16.5
15.0
13.5
12.0
10.5
9.0
7.5
6.0
4.5
3.0
1.5
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
24.3
24.3
24.3
24.3
24.3
24.3
24.3
24.3
24.3
24.3
24.3
24.3
24.3
24.3
24.3
24.4
22.9
21.4
19.9
18.4
16.9
15.4
13.9
12.4
10.9
9.4
7.9
6.4
4.8
3.2
1.6
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
25.9
25.9
25.9
25.9
25.9
25.9
25.9
25.9
25.9
25.9
25.9
25.9
25.9
25.9
25.9
25.9
35.5
33.8
32.1
30.3
28.5
26.5
24.5
22.0
19.5
17.0
14.0
10.0
5.0
/
/
/
/
/
/
/
/
/
/
/
/
/
37.2
37.2
37.2
37.2
37.2
37.2
37.2
37.2
37.2
37.2
37.2
37.2
37.2
V12
Caution There is no connection between V6 and V7 terminal in the chip.
8
Data Sheet S15423EJ1V0DS
µ PD16718
6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN
Data format: 6 bits × 2 RGBs (6 dots)
Input width: 36 bits (2-pixel data)
R,/L = H (Right shift)
Output
S1
S2
S3
S4
"""
S479
S480
Data
D00 to D05
D10 to D15
D20 to D25
D30 to D35
"""
D40 to D45
D50 to D55
R,/L = L (Left shift)
Output
S1
S2
S3
S4
"""
S479
S480
Data
D00 to D05
D10 to D15
D20 to D25
D30 to D35
"""
D40 to D45
D50 to D55
POL
Note
S2n–1
Note
S2n
L
V0 to V6
V7 to V13
H
V7 to V13
V0 to V6
Note S2n•1 (Odd output), S2n (Even output)
★
7. RELATIONSHIP BETWEEN STB, POL, AND OUTPUT WAVEFORM
The output voltage is written to the LCD panel synchronized with the STB falling edge.
STB
POL
S2n-1
Selected voltage
positive side
Selected voltage
negative side
Selected voltage
positive side
S2n
Hi-Z
Selected voltage
negative side
Hi-Z
Selected voltage
positive side
Data Sheet S15423EJ1V0DS
Hi-Z
Selected voltage
negative side
9
µ PD16718
8. CURRENT CONSUMPTION REDUCTION FUNCTION
The µ PD16718 has a low power control function (LPC) which can switch the bias current of the output amplifier
between two levels.
<Low power control function (LPC)>
The bias current of the output amplifier can be switched between two levels using this pin.
LPC = H or open: low power mode
LPC = L: normal power mode
The VDD2 of static current consumption can be reduced to two thirds of that in normal mode, input a stable DC
current (VDD1/VSS1) to this pin.
10
Data Sheet S15423EJ1V0DS
µ PD16718
9. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Rating
Unit
–0.5 to +4.0
V
–0.5 to +17.0
V
–0.5 to VDD1 + 0.5
V
Logic Part Supply Voltage
VDD1
Driver Part Supply Voltage
VDD2
Logic Part Input Voltage
VI1
Driver Part Input Voltage
VI2
–0.5 to VDD2 + 0.5
V
Logic Part Output Voltage
VO1
–0.5 to VDD1 + 0.5
V
Driver Part Output Voltage
VO2
–0.5 to VDD2 + 0.5
V
Operating Ambient Temperature
TA
–10 to +75
°C
Storage Temperature
Tstg
–55 to +125
°C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = –10 to +75°C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Logic Part Supply Voltage
VDD1
2.5
3.3
3.6
V
Driver Part Supply Voltage
VDD2
10.0
11.5
12.5
V
High-Level Input Voltage
VIH
0.7 VDD1
VDD1
V
Low-Level Input Voltage
VIL
0
0.3 VDD1
V
γ -Corrected Voltage
V0 to V13
0.1
VDD2 − 0.1
V
0.1
VDD2 − 0.1
V
57
MHz
Driver Part Output Voltage
VO
Clock Frequency
fCLK
VDD1 = 2.5 V
Data Sheet S15423EJ1V0DS
11
µ PD16718
Electrical Characteristics (TA = –10 to +75°C, VDD1 = 2.5 to 3.6 V, VDD2 = 10.0 to 12.5 V, VSS1 = VSS2 = 0 V, LPC = L)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input Leak Current
IIL
Except Osel, LPC, R,/L
±1.0
µA
Pull-up Resistance Value
RPU
LPC, R,/L
100
190
500
kΩ
Pull-downResistance Value
RPD
Osel
25
50
150
kΩ
High-Level Output Voltage
VOH
STHR (STHL), IOH = 0 mA
Low-Level Output Voltage
VOL
STHR (STHL), IOL = 0 mA
γ -Corrected Resistance
Iγ
VDD2 = 12.5 V, V0 to V6 = V7 to V13 = 5.0 V
Driver Output Current
IVOH
Vx = 11.0 V, VOUT = 10.5 V
Output Voltage Deviation
VDD1 − 0.1
8.7
Note
Note
20
V
0.1
V
14.5
20.3
kΩ
–50
–20
µA
µA
IVOL
Vx = 0.5 V, VOUT = 1.0 V
∆VO
VO = 1.2 V to VDD2 − 1.2 V
±10
55
±20
mV
VO = 1.0 to 1.2 V
±13
±25
mV
VO = VDD2 − 1.2 V to VDD2 − 1.0 V
Output swing difference
∆VP–P1
VO = 5.4 V to VDD2 − 5.4 V
±5
±10
mV
deviation
∆VP–P2
VO = 1.9 to 5.4 V
±8
±15
mV
±15
±20
mV
VO = VDD2 − 5.4 V to VDD2 − 1.9 V
∆VP–P3
VO = 1.0 to 1.9 V
VO = VDD2 − 1.0 V to VDD2 − 1.9 V
Logic Part Dynamic Current
IDD1
VDD1 = 3.3 V
0.6
11
mA
IDD2
VDD2 = 11.5 V, with no load, LPC = L
5.4
10
mA
Consumption
Driver Part Dynamic Current
Consumption
Note VX refers to the output voltage of analog output pins S1 to S480.
VOUT refers to the voltage applied to analog output pins S1 to S480.
Cautions 1. fSTB = 50 kHz, fCLK = 40 MHz.
2. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the
measured values in the dot checkerboard input pattern.
3. Refers to the current consumption per driver when cascades are connected under the assumption
of UXGA single-sided mounting (10 units).
12
Data Sheet S15423EJ1V0DS
µ PD16718
Electrical Characteristics (TA = –10 to +75°C, VDD1 = 2.5 to 3.6 V, VDD2 = 10.0 to 12.5 V, VSS1 = VSS2 = 0 V, LPC = L)
Parameter
Start Pulse Delay Time
Symbol
tPLH1
Conditions
MIN.
TYP.
CL = 15 pF
tPKL1
Driver Output Delay Time
Unit
15
ns
15
ns
3.8
6
µs
tPLH3 Note2
6.7
10
µs
tPHL2 Note1
3.8
6
µs
6.1
tPLH2 Note1
CL = 75 pF, RL = 5 kΩ
10
µs
CI1
STHR (STHL) excluded, TA = 25°C
10
pF
CI2
STHR (STHL),TA = 25°C
15
pF
tPHL3
Input Capacitance
MAX.
Note2
Notes 1. tPLH2/tPHL2 are specified as the time it takes to reach the target voltage ±10% (condition: VO = 0.1 to 12.4 V).
2. tPLH3/tPHL3 are specified as the time it takes to reach the target voltage ±2% (condition: VO = 0.1 to 12.4 V).
★ <Measurement Condition>
RL1
RL2
RL3
RL4
Measure point
RL5
RLn = 1 kΩ
Output
CLn = 15 pF
CL1
CL2
Data Sheet S15423EJ1V0DS
CL3
CL4
CL5
13
µ PD16718
Timing Requirement (TA = –10 to +75°C, VDD1 = 2.5 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Clock Pulse Width
PW CLK
17
ns
Clock Pulse High Period
PW CLK(H)
4
ns
Clock Pulse Low Period
PW CLK(L)
4
ns
Data Setup Time
tSETUP1
3
ns
Data Hold Time
tHOLD1
0
ns
Start Pulse Setup Time
tSETUP2
3
ns
Start Pulse Hold Time
tHOLD2
0
ns
POL21, POL22 Setup Time
tSETUP3
3
ns
POL21, POL22 Hold Time
tHOLD3
0
ns
STB Pulse Width
PW STB
2
CLK
Last Data Timing
tLDT
2
CLK
STB-CLK Time
tSTB-CLK
STB ↑ → CLK ↑
7
ns
Time between STB and Start Pulse
tSTB-STH
STB ↑ → STHR (STHL) ↑
2
CLK
POL-STB Time
tPOL-STB
POL ↑ or ↓ → STB ↑
–5
ns
STB-POL Time
tSTB-POL
STB ↓ → POL ↓ or ↑
6
ns
Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
14
Data Sheet S15423EJ1V0DS
1
2
3
1
80
81
82
801
tr
2
VDD1
90%
802
10%
tSETUP2
tHOLD2
tf
VSS1
tSTB-CLK
VDD1
STHR
(1st Dr.)
VSS1
tSETUP1
Dn0 to Dn5
INVALID
D1 to D6 D7 to D12
tSETUP3
POL21,
POL22
tHOLD1
tSTB-STH
D469 to
D474
D475 to
D480
D481 to
D486
VDD1
D4795 to
D4800
INVALID
D1t o D6 D7 to D12
VSS1
tHOLD3
VDD1
INVALID
INVALID
Data Sheet S15423EJ1V0DS
VSS1
tPLH1
tPHL1
VDD1
STHL
(1st Dr.)
VSS1
tLDT
PWSTB
VDD1
STB
VSS1
tPOL-STB
tSTB-POL
VDD1
POL
VSS1
tPLH3
Hi-z
tPLH2
Switching Characteristics Waveform
CLK
PWCLK(H)
Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
PWCLK(L) PWCLK
Target Voltage ± 0%
6-bit accuracy
Sn
(VX)
tPHL3
15
µ PD16718
tPHL2
µ PD16718
10. RECOMMENDED SOLDERING CONDITIONS
The following conditions must be met for soldering conditions of the µ PD16718.
For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E).
Please consult with our sales offices in case other soldering process is used, or in case the soldering is done
under different conditions.
µ PD16718N-xxx: TCP (TAB package)
Mounting Condition
Thermocompression
Mounting Method
Soldering
Condition
Heating tool 300 to 350°C: heating for 2 to 3 seconds: pressure 100g (per
solder)
ACF
Temporary bonding 70 to 100°C: pressure 3 to 8 kg/cm2 : time 3 to 5
(Adhesive
seconds.
Conductive Film)
Real bonding 165 to 180°C: pressure 25 to 45 kg/cm2 : time 30 to 40
seconds. (When using the anisotropy conductive film SUMIZAC1003 of
Sumitomo Bakelite, Ltd.)
Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF manufacturing
company. Be sure to avoid using two or more packaging methods at a time.
16
Data Sheet S15423EJ1V0DS
µ PD16718
[MEMO]
Data Sheet S15423EJ1V0DS
17
µ PD16718
[MEMO]
18
Data Sheet S15423EJ1V0DS
µ PD16718
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S15423EJ1V0DS
19
µ PD16718
Reference Documents
NEC Semiconductor Device Reliability / Quality Control System (C10983E)
Quality Grades On NEC Semiconductor Devices (C11531E)
• The information in this document is current as of December, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4