DATA SHEET MOS INTEGRATED CIRCUIT µPD16835A MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT DESCRIPTION The µPD16835A is a monolithic quad H bridge driver IC that employs a CMOS control circuit and a MOS FET output circuit. Because it uses MOS FETs in its output stage, this driver IC consumes less power than conventional driver ICs that use bipolar transistors. Because the µPD16835A controls a motor by inputting serial data, its package has been shrunk and the number of pins reduced. As a result, the performance of the application set can be improved and the size of the set has been reduced. The µPD16835A employs a current-controlled 64-step micro step driving method that drives stepper motor with low vibration. The µPD16835A is housed in a 38-pin plastic shrink SOP to contribute to the miniaturization of the application set. The µPD16835A can simultaneously drive two stepper motors and is ideal for the mechanisms of camcorders. FEATURES • Four H bridge circuits employing power MOS FETs • Current-controlled 64-step micro step driving • Motor control by serial data (8 bytes x 8 bits) (original oscillation: 4-MHz input) Data is input with the LSB first. EVR reference setting voltage: 100 to 250 mV (@VREF = 250 mV) ... 4-bit data input (10-mV step) Chopping frequency: 32 to 124 kHz ... 5-bit data input (4-kHz step) Original oscillation division or internal oscillation selectable Number of pulses in 1 VD: 0 to 252 pulses ... 6 bits + 2-bit data input (4 pulses/step) Step cycle: 0.25 to 8191.75 µs ... 15-bit data input (0.25- µs step) • 3-V power supply. Minimum operating voltage: 2.7 V (MIN.) • Low current consumption IDD: 3.0 mA (MAX.), IDD (RESET): 100 µA (MAX.), IMO(RESET): 1.0 µA (MAX.) • 38-pin plastic shrink SOP (7.62 mm (300)) ORDERING INFORMATION Part number Package µPD16835AGS-BGG 38-pin plastic shrink SOP (7.62 mm (300)) The information in this document is subject to change without notice. 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Document No. S15973EJ1V0DS00 (1st edition) Date Published February 2002 N CP(K) Printed in Japan © 2002 37 RESET VD 36 VREF 32 SCLK 7 SDATA 35 LATCH 34 BLOCK DIAGRAM 2 OSCOUT OSCIN EXP0 EXP1 EXP2 EXP3 33 17 18 19 21 38 VDD 8 VM1 23 VM2 27 VM3 9 x2 SERIAL-PARARELLE DECODER PULSE GENERATER EXTOUT SELECTOR 1/N Data Sheet S15973EJ1V0DS VM4 13 EVR1 COSC 2 SELECTOR EVR2 CURRENT SET α OSC EVR1 EVR2 22 CURRENT SET β 31 + + – FILTER VM LGND 1 PGND 20 H BRIDGE α 1ch + – FILTER A1 A2 3 FILA 28 29 FBB – FILTER VM H BRIDGE α 2ch 26 24 + B1 B2 4 FILB 16 15 FBC FILTER VM H BRIDGE β 1ch 30 + C1 H BRIDGE β 2ch 14 C2 5 FILC 12 11 FBD D1 10 D2 6 FILD µPD16835A FBA + VM 25 EXTβ + + – EXTα µPD16835A PIN CONFIGURATION 38-pin plastic shrink SOP (7.62 mm (300)) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 LGND COSC FILA FILB FILC FILD VREF VDD VM3 D2 FBD D1 VM4 C2 FBC C1 EXP0 EXP1 EXP2 RESET OSCOUT OSCIN SCLK SDATA LATCH VD EXTβ B2 FBB B1 VM2 A2 FBA A1 VM1 EXTα EXP3 PGND Data Sheet S15973EJ1V0DS 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 3 µPD16835A 1. PIN FUNCTIONS Pin No. 4 Symbol Function 1 LGND Control circuit GND pin 2 COSC Chopping capacitor connection pin 3 FILA α 1-ch filter capacitor connection pin (1000 pF TYP.) 4 FILB α 2-ch filter capacitor connection pin (1000 pF TYP.) 5 FILC β 1-ch filter capacitor connection pin (1000 pF TYP.) 6 FILD β 2-ch filter capacitor connection pin (1000 pF TYP.) 7 VREF Reference voltage input pin (250 mV TYP.) 8 VDD Control circuit supply voltage input pin 9 VM3 Output circuit supply voltage input pin 10 D2 β 2-ch output pin 11 FBD β 2-ch sense resistor connection pin 12 D1 β 2-ch output pin 13 VM4 Output circuit supply voltage connection pin 14 C2 β 1-ch output pin 15 FBC β 1-ch sense resistor connection pin 16 C1 β 1-ch output pin 17 EXP0 Output monitor pin (open drain) 18 EXP1 Output monitor pin (open drain) 19 EXP2 Output monitor pin (open drain) 20 PGND Power circuit GND pin 21 EXP3 Output monitor pin (open drain) 22 EXTα Logic circuit monitor pin 23 VM1 Output circuit supply voltage input pin 24 A1 α 1-ch output pin 25 FBA α 1-ch sense resistor connection pin 26 A2 α 1-ch output pin 27 VM2 Output circuit supply voltage input pin 28 B1 α 2-ch output pin 29 FBB α 2-ch sense resistor connection pin 30 B2 α 2-ch output pin 31 EXTβ Logic circuit monitor pin 32 VD Video sync signal input pin 33 LATCH Latch signal input pin 34 SDATA Serial data input pin 35 SCLK Serial clock input pin 36 OSCIN Original oscillation input pin (4 MHz TYP.) 37 OSCOUT Original oscillation output pin 38 RESET Reset signal output pin Data Sheet S15973EJ1V0DS µPD16835A 2. I/O PIN EQUIVALENT CIRCUIT Pin Name Equivalent Circuit Pin Name Equivalent Circuit VDD VDD LATCH SDATA SCLK VDD Pad OSCIN RESET Pad Pull-down resistor (125 Ω) VDD OSCOUT EXTα EXTβ VDD EXP0 EXP1 EXP2 EXP3 Pad Pad VDD VREF Pad VDD FILA FILB FILC FILD Pad Buffer VM A1, A2 B1, B2 C1, C2 D1, D2 Parasitic diodes Pad FB Data Sheet S15973EJ1V0DS 5 4 MHz OSCIN 100 kΩ x 4 OSCOUT VD VREF EXP0 EXP1 EXP2 EXP3 SCLK SDATA LATCH RESET REGULATOR 3.3 V x2 VDD VM1 SERIAL-PARARELLE DECODER VM2 VM3 EXTOUT SELECTOR PULSE GENERATER 1/N Data Sheet S15973EJ1V0DS VM4 COSC BATTERY 4.8 to 11 V SELECTOR OSC EVR1 EVR2 EVR1 EVR2 CURRENT SET α CURRENT SET β EXTα EXTβ 3. EXAMPLE OF STANDARD CONNECTION 6 250 mV EVR : 1010 fOSC : 64 kHz CPU 33 pF + + + + – + – FILTER VM + – FILTER VM + – FILTER VM + FILTER VM LGND PGND H BRIDGE α 1ch FBA A1 H BRIDGE α 2ch A2 FILA FBB B1 B2 FILB H BRIDGE β 1ch FBC C1 H BRIDGE β 2ch C2 FILC FBD D1 D2 FILD 6.8 Ω x 2 6.8 Ω 1000 pF 6.8 Ω 1000 pF 1000 pF x 2 MOTOR 2 µPD16835A MOTOR 1 µPD16835A 4. STANDARD CHARACTERISTICS CURVES PT vs. TA Characteristics I MO (RESET) vs. VM Characteristics 1.4 1 OFF VM pin Current I MO (RESET) (µ A) Total Power Dissipation P T (W) 1.2 1.0 125°C/W 0.8 0.6 0.4 0.2 0 –10 0 80 100 20 40 60 Ambient Temperature TA (°C) 0.8 0.6 0.4 0.2 0 120 TA = 25°C, no load, after reset 4 IDD vs. VDD Characteristics 200 output open 4 VDD pin Current IDD (mA) VDD pin Current at Reset State I DD (RESET) (µA) TA = 25°C, operating, 3 2 1 2 3 4 5 Control Circuit Supply Volage VDD (V) TA = 25°C, after reset 150 100 50 0 6 2 VIH/VDD, VIL/VDD vs. VDD Characteristics 6 High-level/Low-level Input Current IIH/IIL (µ A) 60 TA = 25°C Input Voltage VIH/VDD, VIL/VDD (V) 3 4 5 Control Circuit Supply Volage VDD (V) IIH/IIL vs. VIN Characteristics 1 0.8 0.6 VIH VIL 0.4 0.2 0 12 IDD (RESET) vs. VDD Characteristics 5 0 6 8 10 Output Circuit Supply Voltage VM (V) 2 3 4 5 Control Circuit Supply Volage VDD (V) 6 TA = 25°C, IIH: VIN = VDD, IIL: VIN = 0 V 40 IIH 20 IIL 0 2 Data Sheet S15973EJ1V0DS 3 5 4 Input Voltage VIN (V) 6 7 µPD16835A fOSC vs. VDD Characteristics fSTEP vs. VDD Characteristics 6 TA = 25°C, COSC = 100 pF, DATA: all high 140 TA = 25°C, COSC = 100 pF Step Frequency fSTEP (kHz) Chopping Frequency fOSC (kHz) 150 130 120 110 5 4 3 100 90 2 3 4 5 Control Circuit Supply Voltage VDD (V) 2 6 2 VREFVER vs. VDD Characteristics IM (MAX) vs. EVR Characteristics Sine Wave Peak Output Current IM (MAX) (mA) EVR Variable Voltage V REFVER (mV) TA = 25°C, VREF = 250 mV 30 20 10 2 5 3 4 Control Circuit Supply Voltage VDD (V) 6 70 50 40 30 20 50 tON, tOFF vs. VM Characteristics Turn-on Time, Turn-off Time tON/tOFF (ns) 8 TA = 25°C, IM = 100 mA, CFIL : none 400 300 tON tOFF 200 100 4 10 6 8 Output Circuit Supply Voltage VM (V) TA = 25°C, VM = 6 V Rs = 6.8 Ω, fOSC = 64 kHz, L = 25 mH/R = 100 Ω at 1 kHz 60 500 0 6 80 40 0 3 4 5 Control Circuit Supply Voltage VDD (V) 12 Data Sheet S15973EJ1V0DS 100 150 200 250 Reference Setting Voltage EVR (mV) 300 µPD16835A 5. INTERFACE (I/F) CIRCUIT DATA CONFIGURATION (fCLK = 4-MHz EXTERNAL CLOCK INPUT) Input data consists of serial data (8 bytes x 8 bits). Input serial data with the LSB first, from the 1st byte to 8th byte. (1) Initial data (2) Standard data <1st byte> Bit <1st byte> Data Function Setting Bit DATA selection D7 Data Function Setting 0 HEADER DATA2 DATA selection D7 1 HEADER DATA2 D6 1 HEADER DATA1 D6 0 HEADER DATA1 D5 1 HEADER DATA0 D5 0 HEADER DATA0 D4 0 − − D4 0 − D3 1 or 0 EXP3 Hi-Z or L D3 1 or 0 EXP3 Hi-Z or L D2 1 or 0 EXP2 Hi-Z or L D2 1 or 0 EXP2 Hi-Z or L D1 1 or 0 EXP1 Hi-Z or L D1 1 or 0 EXP1 Hi-Z or L D0 1 or 0 EXP0 Hi-Z or L D0 1 or 0 EXP0 Hi-Z or L Remark Hi-Z : High impedance, Remark Hi-Z : High impedance, L : Low level (current sink) L : Low level (current sink) <2nd byte> Bit − <2nd byte> Data Function Setting Bit Data Function Setting D7 D7 1 or 0 α ROTATION α ch CCW/CW D6 D6 1 or 0 α ENABLE α ch ON/OFF Start point wait D5 D4 8-bit data D3 input Note 256 µs to 65.28 ms First Point Wait Setting (1 to 255) D2 ∆t = 256 µs D5 D3 6-bit data D2 input D1 D1 D0 D0 Note Input other than “0”. α ch D4 Number of α Pulse Number pulses in 1 VD Setting (0 to 63) ∆n = 4 pulses Note Note The number of pulses can be varied in 4-pulse steps. <3rd byte> Bit <3rd byte> Data Function Setting Bit Data Function Setting D7 D7 15-bit data D6 Start point drive D6 α ch pulse D5 wait D5 cycle 0.25 to 8191.75 µs D4 8-bit data First Point 256 µs to 65.28 ms D4 D3 input Note Magnetize Wait Setting D3 Low-order D2 8-bit data (1 to 32767) input ∆t = 0.25 µs D2 (1 to 255) D1 ∆t = 256 µs D0 D1 α Pulse Width Setting D0 Note Input other than “0”. Data Sheet S15973EJ1V0DS 9 µPD16835A <4th byte> Bit <4th byte> Data Function OSCSEL Setting Bit Data Internal/external D7 1 or 0 15-bit data Function Current Set α Setting D7 1 or 0 D6 0 - - D6 D5 0 - - D5 α ch pulse cycle : D4 Chopping D4 D3 frequency : D3 D2 D1 5-bit data input Chopping 32 to 124 kHz Frequency Setting Note High-order D2 D1 (8 to 31) D0 α Pulse Width set2/set1 0.25 to 8191.75 µs Setting 8-bit data (1 to 32767) input ∆t = 0.25 µs D0 ∆f = 4 kHz Note The frequency is 0 kHz if 0 to 7 is input. <5th byte> Bit D7 <5th byte> Data EXTα EXTβ Bit - - D7 1 or 0 β ROTATION β ch CCW/CW D6 1 or 0 β ENABLE β ch ON/OFF 0 Note 5 ENABLE α D5 Note 5 ROTATION α D4 Note 5 Pulse Out α Pulse Out β D4 D6 Note1 Note2 ENABLE β Note1 ROTATION β Note2 Data D5 Setting β ch D3 Note 5 FF7 α FF7 β D3 6-bit data D2 Note 5 FF3 α FF3 β D2 input D1 Note 5 Checksum Note3 FF2 β D1 D0 Note 5 Chopping Note4 FF1 β D0 Notes 1. H level : Conducts, L level : Stops Function Number of β Pulse Number pulses in 1 VD Setting (1 to 63) ∆n = 4 pulses Note Note The number of pulses can be varied in 4-pulse 2. H level : Reverse (CCW), steps. L level : Forward (CW) 3. H level : Normal data input, L level : Abnormal data input 4. Not output in internal oscillation mode. 5. Select one of D0 to D6 and input “1”. If two or more of D0 to D6 are selected, they are positively ORed for output. <6th byte> Bit <6th byte> Data Function D7 Setting Bit Data α ch Output current D7 15-bit data Setting D6 4-bit data α ch setting 2 EVR : 100 D6 β ch pulse D5 input Current Set2 to 250 mV D5 cycle: Setting (0 to 15) Note D4 D4 D3 D2 D1 4-bit data input D0 α ch Current Set1 β Pulse Width 0.25 to 8191.75 µs α ch Output current D3 Low-order setting 1 EVR : 100 D2 8-bit data (1 to 32767) input ∆t = 0.25 µs to 250 mV D1 Setting (0 to 15) Note D0 Note A voltage of about double EVR is output to the FIL pin. 10 Function Data Sheet S15973EJ1V0DS Setting µPD16835A <7th byte> Bit <7th byte> Data Function D7 Setting Bit β ch Output D6 4-bit data β ch current setting 2 D5 input Current Set2 EVR: 100 to 250 mV Setting (0 to 15) D4 D3 D7 1 or 0 D6 15-bit data Function Current Set β 7-bit data β ch current setting 1 D2 D1 input Current Set1 EVR: 100 to 250 mV D1 Setting (0 to 15)Note High-order D3 4-bit data set2/set1 cycle: D4 D2 Setting β ch pulse D5 Note β ch Output D0 Data β Pulse Width 0.25 to 8191.75 µs Setting (1 to 32767) input ∆t = 0.25 µs D0 Note A voltage of about double EVR is output to the FIL pin. <8th byte> Bit <8th byte> Data Function Setting Bit Data D7 1 or 0 D7 1 or 0 D6 1 or 0 D6 1 or 0 D5 1 or 0 D5 1 or 0 D4 1 or 0 D4 1 or 0 D3 1 or 0 D3 1 or 0 D2 1 or 0 D2 1 or 0 D1 1 or 0 D1 1 or 0 D0 1 or 0 D0 1 or 0 Checksum Checksum Note Note Data is input so that the sum of the 1st through the 8th bytes is 00H. Function Checksum Setting Checksum Note Note Data is input so that the sum of the 1st through the 8th bytes is 00H. Data Sheet S15973EJ1V0DS 11 µPD16835A Data Configuration Data can be input in either of two ways. Initial data can be input when the power is first applied, or standard data can be input during normal operation. Input serial data with the LSB first, i.e., starting from the D0 bit (LSB) of the 1st byte. Therefore, the D7 bit of the 8th byte is the most significant bit (MSB). When inputting initial data, set a start point wait time that specifies the delay from power application to pulse output, and the start point drive wait time. At the same time, also set a chopping frequency and a reference voltage (EVR) that determines the output current of each channel. Because the µPD16835A has an EXT pin for monitoring the internal operations, the parameter to be monitored can be selected by initial data. When inputting standard data, input the rotation direction of each channel, the number of pulses, and the data for the pulse cycle. Initial data or standard data is selected by using bits D5 to D7 of the 1st byte (see Table 5-1). Table 5-1. Data Selection Mode (1st byte) D7 D6 D5 1 1 1 Initial data Data type 0 0 0 Standard data Remark If the high-order three bits are high, the initial data is selected; if they are low, the standard data is selected. Data other than (0, 0, 0) and (1, 1, 1) must not be input. Input the serial data during start point wait time. Details of Data Configuration How to input initial data and standard data is described below. (1) Initial data input <1st byte> The 1st byte specifies the type of data (initial data or standard data) and determines the presence or absence of the EXP pin output. Bits D5 to D7 of this byte specify the type of data as shown in Table 5-1, while bits D0 to D3 select the EXP output (open drain). Table 5-2. 1st Byte Data Configuration Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 1 1 1 0 0 or 1 0 or 1 0 or 1 0 or 1 The EXP pin goes low (current sink) when the input data is “0”, and high (high impedance state) when the input data is “1”. Pull this pin up to VDD for use. Input “0” to bit D4. 12 Data Sheet S15973EJ1V0DS µPD16835A <2nd byte> The 2nd byte specifies the delay between data being read and data being output. This delay is called the start up wait time, and the motor can be driven from that point at which the start up wait time is “0”. This time is counted at the rising edge of VD. The start up wait time can be set to 65.28 ms (when a 4-MHz clock is input), and can be fine-tuned by means of 8-bit division (256-µs step: with 4-MHz clock). The start up wait time is set to 65.28 ms when all the bits of the 2nd byte are set to “1”. Caution Always input data other than “0” to this byte because the start up wait time is necessary for latching data. If “0” is input to this byte, data cannot be updated. Transfer standard data during the start up wait time. <3rd byte> The 3rd byte specifies the delay between the start point wait time being cleared and the output pulse being generated. This time is called the start up drive wait time, and the output pulse is generated from the point at which the start up drive wait time reaches “0”. The start up drive wait time is counted at the falling edge of the start up wait time. The start up drive wait time can be set to 65.28 ms (with 4-MHz clock) and can be fine-tuned by means of 8-bit division (256-µs step: with 4-MHz clock). The start up drive wait time is set to 65.28 ms when all the bits of the 3rd byte are “1”. Caution Always input data other than “0” to this byte because the start up drive wait time is necessary for latching data. If “0” is input to this byte, data cannot be updated. <4th byte> The 4th byte selects a chopping frequency by using 5-bit data. It also selects whether the chopping frequency is created by dividing the original oscillation (external clock) or whether the internal oscillator is used. The chopping frequency is selected by bits D0 to D4. Bit D7 specifies the method used to create the chopping frequency. When this bit is “0”, the original oscillation (external clock input to OSCIN) is used; when it is “1”, the internal oscillator is used. Bits D5 and D6 are fixed to “0”. The chopping signal is output after the initial data has been input and the first standard data has been latched (see Timing Chart). Table 5-3. 4th Byte Data Configuration (Initial data) Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 The chopping frequency is set to 0 kHz and to a value in the range of 32 to 124 kHz (in 4-kHz steps), as follows. Although the chopping frequency is set by 5 bits of data, it is internally configured using 7-bit data (with the loworder 2 bits fixed to 0). Data Sheet S15973EJ1V0DS 13 µPD16835A Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 0 0 0 0 0 0 Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 0 0 0 1 1 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 0 0 1 0 0 0 Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 0 0 1 0 0 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 0 1 1 1 1 1 fOSC = 0 kHz fOSC = 0 kHz fOSC = 32 kHz fOSC = 36 kHz fOSC = 124 kHz <5th byte> The 5th byte selects a parameter to be output to the EXT pin (logic operation monitor pin). Input data to bits D0 to D6 of this byte. Bit D7 is fixed to “0”. There are two EXT pins. EXTα indicates the operating status of α ch, and EXTβ indicates that of β ch. The relationship between each bit and each EXT pin is as shown in Table 5-4. Table 5-4. 5th Byte Data Configuration (Initial data) Bit Data D7 0 D6 0 or 1 EXTα EXTβ Not used Not used ENABLE α ENABLE β D5 0 or 1 ROTATION α ROTATION β D4 0 or 1 PULSEOUT α PULSEOUT β D3 0 or 1 FF7 α FF7 β D2 0 or 1 FF3 α FF3 β D1 0 or 1 CHECKSUM FF2 β D0 0 or 1 CHOPPING FF1 β The checksum bit is cleared to “0” in the event of an error. Normally, it is “1”. If two or more signals that output signals to EXTα and EXTβ are selected, they are positively ORed for output. Caution The CHOPPING signal is not output in internal oscillation mode. 14 Data Sheet S15973EJ1V0DS µPD16835A Remark The meanings of the symbols listed in Table 5-4 are as follows: ENABLE : Output setting (H : Conducts, L : Stops) ROTATION : Rotation direction (H : Reverse (CCW), L : Forward (CW)) PULSEOUT : Output pulse signal FF7 : Presence/absence of pulse in LATCH cycle (Outputs H level if output pulse information exists in standard data.) FF3 : Pulse gate (output while pulse exists) FF2 : Outputs H level during start up wait time + start up drive wait time FF1 : Outputs H level during start up wait time CHECKSUM : Checksum output (H : when normal data is transmitted, L : when abnormal data is transmitted) CHOPPING : Chopping wave output (in original oscillation mode only) <6th byte> The 6th byte sets the peak output current value of α ch. The output current is determined by the EVR reference voltage. The 250-mV (TYP.) voltage input from an external source to the VREF pin is internally doubled and input to a 4-bit D/A converter. By dividing this voltage by 4-bit data, an EVR reference voltage can be set inside the IC within the range of 200 to 500 mV, in units of 20 mV. The µPD16835A can set two values of the EVR reference voltage in advance. This is done by using bits D0 to D3 or D4 to D7. Which of the two EVR reference voltage values is to be used is specified by the CURRENT SET bit in the standard data. If all the bits of the 6th byte are “0”, the EVR reference voltage of 200 mV is selected; if they are “1”, the EVR reference voltage of 500 mV is selected. Table 5-5. 6th Byte Data Configuration (Initial data) Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Remark Bits D4 to D7 : Reference voltage 2 (EVR α2) Bits D0 to D3 : Reference voltage 1 (EVR α1) <7th byte> The 7th byte specifies the peak output current value of β ch. The output current is determined by the EVR reference voltage. The 250-mV (TYP.) voltage input from an external source to the VREF pin is internally doubled and input to a 4-bit D/A converter. By dividing this voltage by 4-bit data, an EVR reference voltage can be set inside the IC within a range of 200 to 500 mV, in units of 20 mV. The µPD16835A can set two values of the EVR reference voltage in advance. This is done using bits D0 to D3 or D4 to D7. Which of the two EVR reference voltage values is to be used is specified by the CURRENT SET bit in the standard data. If all the bits of the 7th byte are “0”, the EVR reference voltage of 200 mV is selected; if they are “1”, the EVR reference voltage of 500 mV is selected. Data Sheet S15973EJ1V0DS 15 µPD16835A Table 5-6. 7th Byte Data Configuration (Initial data) Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Remark Bits D4 to D7 : Reference voltage 2 (EVR β2) Bits D0 to D3 : Reference voltage 1 (EVR β1) <8th byte> The 8th byte is checksum data. Normally, the sum of the 8-byte data is 00H. If the sum is not 00H because data transmission is abnormal, the stepping operation is inhibited and the checksum output pin (EXT pin) is kept “L”. (2) Standard data input <1st byte> The 1st byte specifies the type of data and whether the EXP pin output is used, such as when the initial data is input. Table 5-7. 1st Byte Data Configuration Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 1 1 1 0 0 or 1 0 or 1 0 or 1 0 or 1 The EXP pin goes low (current sink) when the input data is “0”, and high (high impedance state) when the input data is “1”. Input “0” to bit D4. <2nd byte> The 2nd byte specifies the rotation direction of the α channel, enables output of the α channel, and the number of pulses (252 pulses MAX.) during the 1VD period (in 1 cycle of FF2) of the α channel. Bit D7 is used to specify the rotation direction. The rotation is in the forward direction (CW mode) when this bit is “0”; it is in the reverse direction (CCW mode) when the bit is “1”. Bit D6 is used to enable the output of the α channel. The α channel enters the high impedance state when this bit is “0”; it is in conduction mode when the bit is “1”. The number of pulses is set by bits D0 to D5. It is set by 6 bits in terms of software. However, the actual circuit uses an 8-bit counter with the low-order two bits fixed to “0”. Therefore, the number of pulses that is actually generated during start up wait time + start up drive wait (FF2) cycle is the number of pulses input x 4. The number of pulses can be set to a value in the range of 0 to 252, in units of 4 pulses. 16 Data Sheet S15973EJ1V0DS µPD16835A Table 5-8. 2nd Byte Data Configuration (Standard data) Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Rotation direction ENABLE Number of pulses <3rd and 4th bytes> The 3rd and 4th bytes select the pulse cycle of the α channel and which of the two reference voltages, created in the initial mode, is to be used (CURRENT SETα). The pulse cycle is specified using 15 bits : bits D0 (least significant bit) to D7 of the 3rd byte, and bits D0 to D6 (most significant bit) of the 4th byte. The pulse cycle can be set to a value in the range of 0.25 to 8191.75 µs in units of 0.25 µs (with a 4-MHz clock). CURRENT SETα is specified by bit D7 of the 4th byte. When this bit is “0”, reference voltage 1 (EVRα1) is selected; when it is “1”, reference voltage 2 (EVRα2) is selected. For further information, refer to the description of the 6th byte of the initial data. Table 5-9. 4th Byte Data Configuration (Standard data) Table 5-10. 3rd Byte Data Configuration (Standard data) Bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 CURRENT SETα Most significant Least significant bit bit (Reference) 6th Byte Data Configuration for Initial Data Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Remark Bits D4 to D7 : Reference voltage 2 (EVR α2) Bits D0 to D3 : Reference voltage 1 (EVR α1) <5th byte> The 5th byte specifies the rotation direction of the β channel, enables output of the β channel, and the number of pulses (252 pulses MAX.) during the 1VD period (in one cycle of FF2) of the β channel. Bit D7 is used to specify the rotation direction. The rotation is in the forward direction (CW mode) when this bit is “0”; it is in the reverse direction (CCW mode) when the bit is “1”. Bit D6 is used to enable the output of the β channel. The β channel goes into a high impedance state when this bit is “0”; it is in the conduction mode when the bit is “1”. The number of pulses is set by bits D0 to D5. It is set by six bits in terms of software. However, the actual circuit uses an 8-bit decoder with the low-order two bits fixed to “0”. Therefore, the number of pulses that is actually generated during start up wait time + start up drive wait (FF2) cycle is the number of pulses input x 4. The number of pulses can be set in a range of 0 to 252 and in units of 4 pulses. Data Sheet S15973EJ1V0DS 17 µPD16835A Table 5-11. 5th Byte Data Configuration (Standard data) Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Rotation direction ENABLE Number of pulses <6th and 7th bytes> The 6th and 7th bytes select the pulse cycle of the β channel and which of the two reference voltages, created in the initial mode, is to be used (CURRENT SETβ). The pulse cycle is specified using 15 bits : bits D0 (least significant bit) to D7 of the 6th byte, and bits D0 to D6 (most significant bit) of the 7th byte. The pulse cycle can be set to a value in the range of 0.25 to 8191.75 µs in units of 0.25 µs (with a 4-MHz clock). CURRENT SETβ is specified by bit D7 of the 7th byte. When this bit is “0”, reference voltage 1 (EVRβ1) is selected; when it is “1”, reference voltage 2 (EVRβ2) is selected. For further information, refer to the description of the 7th byte of the initial data. Table 5-12. 7th Byte Data Configuration (Standard data) Table 5-13. 6th Byte Data Configuration (Standard data) Bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 CURRENT SETβ Most significant bit Least significant bit (Reference) 7th Byte Data Configuration for Initial Data Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Remark Bits D4 to D7 : Reference voltage 2 (EVR β2) Bits D0 to D3 : Reference voltage 1 (EVR β1) <8th byte> The 8th byte is checksum data. Normally, the sum of the 8-byte data is 00H. If the sum is not 00H because data transmission is abnormal, the stepping operation is inhibited and the checksum output pin (EXT pin) is held at “L”. 18 Data Sheet S15973EJ1V0DS µPD16835A (Data Update Timing) The standard data (pulse width, number of pulses, rotation direction, current setting, and ENABLE) of this product are set and updated at the following latch timing. Table 5-14. Data Update Timing ENABLE change 1→1 0→1 1→0 0→0 Pulse width FF2↓ FF2↓ FF2↓ − Number of pulses FF2↓ FF2↓ FF2↓ − Rotation direction FF2↓ FF2↓ FF2↓ − Current setting FF2↓ FF1↓ FF2↓ − ENABLE FF2↓ FF1↓ FF2↓ − The timing at which data is to be updated differs, as shown in Table 5-14, depending on the enabled status. For example, suppose the enable signal is currently “0” (output high impedance) and “1” (output conduction) is input by the next data. In this case, the pulse width, number of pulses, and rotation direction signals are updated at FF2(upon the completion of start up wait), and the current setting and ENABLE signals are updated at FF1 (upon completion of start up drive wait). VD FF1 Start up wait FF2 Start up wait + start up drive wait Pulse output Pulse width, number of pulses, and rotation direction are updated. Current setting and ENABLE are updated (ENABLE change: 0 to 1). VD (1) LATCH I1 Initial data identification (2) (3) S1 Standard data identification S2 S3 I1 data is output. FF1, FF2 output Data Sheet S15973EJ1V0DS 19 µPD16835A (1) Pulse width (2) Internal data retained. (3) Updated to S2 data at FF2 Not output Output reset Rotation direction Number of pulses Internal output retained Not output Internal data retained. Not output Output reset Current setting Internal output retained Not output Updated to S2 data at either FF1 or FF2 ENABLE Internal output retained Not output by enable data of (2) The initial mode of this product is as follows. The IC operation can be initialized as follows: (1) Turns ON VDD. (2) Make RESET input “L”. (3) Input serial initial data. In initial mode, the operating status of the IC is as shown in Table 5-15. Table 5-15. Operations in Initial Mode Item Specifications Current consumption 100 µA OSC Oscillation stops. Input of external clock is inhibited. VD Input inhibited. FF1 to FF7 “L” level PULSE OUT “L” level EXP0 to EXP3 Undefined in the case of (1) above. Previous value is retained in the case of (2) above. Can be updated by serial data in the case of (3) above. Serial operation Can be accessed after initialization in the case of (1) above. Can be accessed after RESET has gone “H” in the case of (2) above. Can be accessed in the case of (3) above. Step pulse output is inhibited and FF7 is made “L” if the following conditions are satisfied. (1) If the set number of pulses (2nd/5th: standard data) is 00H. (2) If the checksum value is other than 00H. (3) If the start up wait time is set to 1 VD or longer. (4) If the start up wait time + start up drive wait time is set to 1 VD or longer. (5) If start up wait is completed earlier than LATCH (↓). (6) If VD is not input. 20 Data Sheet S15973EJ1V0DS µPD16835A Cautions on Correct Use (1) With this product, input the data for start up wait and start up drive wait. Because the standard data are set or updated by these wait times, if the start up wait time and start up drive wait time are not input, the data are not updated. (2) The start up wait time must be longer than LATCH. (3) If the rising of the start up drive wait time is the same as the falling of the last output pulse, a count error occurs, and the IC may malfunction. (4) Input the initial data in a manner that it does not straddle the video sync signal (VD). If it does, the initial data is not latched. (5) Transmit the standard data during the start up wait time (FF1). If it is input at any other time, the data may not be transmitted correctly. (6) If the LGND potential is undefined, the data may not be input correctly. Keep the LGND potential to the minimum level. It is recommended that LGND and PGND be divided for connection (single ground) to prevent the leakage of noise from the output circuit. Data Sheet S15973EJ1V0DS 21 µPD16835A 6. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Symbol Condition Rating Unit VDD –0.5 to +6.0 V VM –0.5 to +11.2 V Input voltage VIN –0.5 to VDD+ 0.5 V Reference voltage VREF 500 mV H bridge drive current Note 1 IM(DC) DC ±150 mA/phase Instantaneous H bridge drive IM(pulse) PW ≤ 10 ms, Duty ≤ 5% ±300 mA/phase current Note 1 Power consumption Note 2 PT 1.0 W Peak junction temperature TCH(MAX.) 150 °C Storage temperature Tstg –55 to +150 °C Notes 1. Permissible current per phase with the IC mounted on a PCB. 2. When the IC is mounted on a glass epoxy PCB (10 cm x 10 cm x 1 mm). Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings. Recommended Operating Range Parameter Supply voltage Symbol MIN. TYP. MAX. Unit VDD 2.7 5.5 V VM 4.8 11 V Input voltage VIN Reference voltage VREF 0 EXP pin input voltage VEXPIN VDD V EXP pin input current IEXPIN 100 µA H bridge drive current IM(DC) +100 mA 225 250 −100 −200 Note 1 VDD V 275 mV H bridge drive current IM(pulse) Clock frequency (OSCIN) fCLK Note 2 3.9 Clock frequency amplitude VfCLK Note 2 0.7 VDD Serial clock frequency (SCLK) fSCLK Video sync signal width PW(VD) Note 3 250 ns LATCH signal wait time t(VD-LATCH) Note 4 400 ns Note 4 4 +200 mA 4.2 MHz VDD V 5.0 MHz SCLK wait time t(SCLK-LATCH) 400 ns SDATA setup time tsetup Note 4 80 ns SDATA hold time thold Note 4 80 ns Note 3 Chopping frequency fOSC Reset signal pulse width tRST 100 32 Operating temperature TA −10 Peak junction temperature TCH(MAX.) Notes 1. PW ≤ 10 ms, duty ≤ 5% 2. COSC = 33 pF, VREF = 250 mV 3. fCLK = 4 MHz 4. Serial data delay time(see the figure on the next page.) 22 Data Sheet S15973EJ1V0DS 124 kHz µs +70 °C 125 °C µPD16835A VD t (VD-LATCH) LATCH 64 clocks (8 bits x 8 bytes) SCLK t (SCLK-LATCH) t (SCLK-LATCH) Ignored because LATCH is at L level. LATCH SDATA SCLK Ignored because LATCH is at L level. 50% D1 50% t (SCLK-LATCH) D2 D3 50% tsetup thold Data Sheet S15973EJ1V0DS 23 µPD16835A ELECTRICAL CHARACTERISTICS DC Characteristics (Unless otherwise specified, VDD = 3.3 V, VM = 6.0 V, VREF = 250 mV, TA = 25°C, fCLK = 4 MHz, COSC = 33 pF, CFIL = 1000 pF, EVR = 100 mV (0000)) Parameter Symbol Condition MIN. TYP. MAX. Unit Off VM pin current IMO(RESET) No load, reset period 1.0 µA VDD pin current IDD Output open 3.0 mA VDD pin current IDD(RESET) Reset period 100 µA High level input voltage VIH LATCH, SCLK, SDATA, VD, Low level input voltage VIL RESET, OSCIN Input hysteresis voltage VH Monitor output voltage 1 VOM α (H), VOM β (H) 5th byte (EXT α, β) VOM α (L), VOM β (L) 5th byte Monitor output voltage 2 VOEXP(H) Pull up (VDD) (EXP0 to EXP3 : open drain) VOEXP(L) IOEXP = 100 µA High level input current IIH VIN = VDD Low level input current IIL VIN = 0 V Reset pin high level input IIH(RST) VRST = VDD IIL(RST) VRST = 0 RIND LATCH, SCLK, SDATA, VD RON IM = 100 mA Chopping frequency (internal fOSC(1) DATA: 00000 (4th byte) oscillation: COSC = 100 pF) fOSC(2) DATA: 11111 (4th byte) Step frequency fSTEP Minimum step VD delay time Note 2 ∆tVD Sine wave peak output IM 0.7 VDD V 0.3 VDD 300 V mV 0.9 VDD V 0.1 VDD V VDD V 0.1 VDD V 0.06 mA µA −1.0 1.0 µA current Reset pin low level input µA −1.0 current Input pull down resistor H bridge ON resistance Note 1 50 3.5 kΩ 5.0 Ω 0 100 124 kHz 150 4 kHz 250 L = 25 mH/R = 100 Ω (1 kHz) current Note 3 200 52 ns mA EVR = 200 mV (1010) RS = 6.8 Ω, fOSC = 64 kHz FIL pin voltage Note 4 FIL pin step voltage Note 4 VEVR EVR = 200 mV (1010) VEVRSTEP Minimum step 370 400 430 20 mV mV AC Characteristics (Unless otherwise specified, VDD = 3.3 V, VM = 6.0 V, TA = 25°C, fCLK = 4 MHz) Parameter Symbol H bridge output circuit turn on tONH Condition MIN. TYP. MAX. Unit IM = 100 mA Note 5 1.0 2.0 µs IM = 100 mA Note 5 1.0 2.0 µs time H bridge output circuit turn off tOFFH time Notes 1. Total of ON resistance at top and bottom of output H bridge 2. By OSCIN and VD sync circuit 3. FB pin is monitored. 4. FIL pin is monitored. A voltage about twice that of the EVR value is output to the FIL pin. 5. 10 to 90% of the pulse peak value without filter capacitor (CFIL) 24 Data Sheet S15973EJ1V0DS TIMING CHART (1) Initialization RESET VD LATCH Initial DATA I1 Standard EXP: 1 Standard : 1 S2 EXP ENABLE: 1 S1 Dummy data EXP : 0 ENABLE: 0 Standard S3 EXP : 1 error DATA Standard Standard : 0 S4 EXP ENABLE: 1 S5 EXP : 1 ENABLE: 0 OSCOUT (original oscillation) Input at rising edge of RESET Start point wait (FF1) Output by I1 data Data Sheet S15973EJ1V0DS Start point wait + start point drive wait (FF2) Output by I1 data Output by S2 data setting ENABLE OUTNote 1 Output by S5 data setting Output by chopping setting of I1 data Chopping pulse Output by EXP setting of S1 data Output by EXP setting of I1 data EXP0 to EXP3 Output by EXP setting of S2DATA S4DATA output Pulse error S2DATA output PULSE OUT PULSE GATE (FF3) Outputs high level for standard data while a pulse output signal exists (LATCH cycle) PULSE CHECKNote 2 (FF7) CHECK SUMNote 3 High level because data is normal. No pulse output because data is erroneous Low level because data is abnormal. to high, and at the falling edge of FF2 when the level changes from high to low. D0 D1 D2 (LSB) Data is held at rising edge of SCLK. D3 D4 D5 D6 D7 2. FF7 is an output signal that is used to check for the presence or absence of a pulse in the standard data, is updated at the falling edge of LATCH and reset once at the rising edge of LATCH. If CHECK SUM is other than “00H”, FF7 goes low, inhibiting pulse output, even if a pulse is generated. 25 3. CHECK SUM output is updated at the falling edge of LATCH. µPD16835A SDATA 8th byte Restore to high level because data is normal. Notes 1. ENABLE is set at the falling edge of FF1 when the level changes from low SCLK 1st byte Enable Outputs high level while pulse is being generated µPD16835A TIMING CHART (2) CLK (PULSE OUT) MOB (CW mode) Current direction: A2 A1 H bridge α , β 1ch output status Current direction: A1 Current direction: B2 A2 Current direction: B2 B1 B1 H bridge α , β 2ch output status Current direction: B1 B2 (Expanded view) Note2 Note1 CW mode CCW mode Note1 CW mode CLK PULSE OUT Position No. 1 2 3 4 5 6 5 4 3 2 3 4 CCW H bridge 1ch output status CW CW CCW CW CW H bridge 2ch output status CCW CW CW CCW Notes1. In CW mode : Position No. is incremented. 2. In CCW mode : Position No. is decremented. Remarks 1. The current value of the actual wave is approximated to the value shown on the next page. 2. The C1, C2, D1, and D2 pins of β channel correspond to the A1, A2, B1, and B2 pins of α channel. 3. The CW mode is set if the D7 bit of the 2nd and 5th bytes of the standard data is “0”. 4. The CCW mode is set if the D7 bit of the 2nd and 5th bytes of the standard data is “1”. 26 Data Sheet S15973EJ1V0DS µPD16835A RELATION BETWEEN ROTATION ANGLE, PHASE CURRENT, AND VECTOR QUANTITY (64-DIVISION MICRO STEP) (Values of µPD16835A for reference) Step Rotation angle (θ ) A phase current B phase current Vector quantity MIN. TYP. MAX. MIN. TYP. MAX. θ0 0 − 0 − − 100 − TYP. 100 θ1 5.6 2.5 9.8 17.0 − 100 − 100.48 θ2 11.3 12.4 19.5 26.5 93.2 98.1 103 100 θ3 16.9 22.1 29.1 36.1 90.7 95.7 100.7 100.02 θ4 22.5 31.3 38.3 45.3 87.4 92.4 97.4 100.02 θ5 28.1 40.1 47.1 54.1 83.2 88.2 93.2 99.99 θ6 33.8 48.6 55.6 62.6 78.1 83.1 88.1 99.98 θ7 39.4 58.4 63.4 68.4 72.3 77.3 82.3 99.97 θ8 45 65.7 70.7 75.7 65.7 70.7 75.7 99.98 θ9 50.6 72.3 77.3 82.3 58.4 63.4 68.4 99.97 θ 10 56.3 78.1 83.1 88.1 48.6 55.6 62.6 99.98 θ 11 61.9 83.2 88.2 93.2 40.1 47.1 54.1 99.99 θ 12 67.5 87.4 92.4 97.4 31.3 38.3 45.3 100.02 θ 13 73.1 90.7 95.7 100.7 22.1 29.1 36.1 100.02 θ 14 78.8 93.2 98.1 103 12.4 19.5 26.5 100 θ 15 84.4 − 100 − 2.5 9.8 17.0 100.48 θ 16 90 − 100 − − 0 − 100 Remark These data do not indicate guaranteed values. Data Sheet S15973EJ1V0DS 27 µPD16835A 7. PACKAGE DRAWING 38-PIN PLASTIC SSOP (7.62 mm (300)) 38 20 detail of lead end F G 1 P 19 A L E H I J S C N S B K D M M NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 12.7±0.3 B 0.65 MAX. C 0.65 (T.P.) D 0.37 +0.05 −0.1 E 0.125±0.075 F 1.675±0.125 G 1.55 H 7.7±0.2 I 5.6±0.2 J 1.05±0.2 K 0.2 +0.1 −0.05 L 0.6±0.2 M 0.10 N 0.10 P +7° 3° −3° P38GS-65-BGG-1 28 Data Sheet S15973EJ1V0DS µPD16835A 8. RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E). Type of Surface Mount Device µPD16835AGS-BGG: 38-pin plastic shrink SOP (7.62 mm (300)) Process Infrared Ray Reflow Soldering conditions Peak temperature: 235°C or below (Package surface temperature), Symbol IR35-00-3 Reflow time: 30 seconds or less (at 210°C or higher), Maximum number of reflow processes: 3 time or less, Number of days: None Note, Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt% or below) is recommended. Vapor Phase Soldering Peak temperature: 215°C or below (Package surface temperature), VP15-00-3 Reflow time: 40 seconds or less (at 200°C or higher), Maximum number of reflow processes: 3 time or less, Number of days: None Note, Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt% or below) is recommended. Wave Soldering Solder temperature: 260°C or below, Flow time: 10 seconds or less, WS60-00-1 Maximum number of flow processes: 1 time, Pre-heating temperature: 120°C or below (Package surface temperature), Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt% or below) is recommended. Partial Heating Method Pin temperature: 300°C or below, − Heat time: 3 seconds or less (Per each side of the device). Note Number of days the device can be stored after the dry pack has been opened, at conditions of 25°C, 65%RH. Caution Apply only one kind of soldering condition to a device, except for “partial heating method”, or the device will be damaged by heat stress. Data Sheet S15973EJ1V0DS 29 µPD16835A [MEMO] 30 Data Sheet S15973EJ1V0DS µPD16835A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S15973EJ1V0DS 31 µPD16835A • The information in this document is current as of January, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. 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(Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4