DATA SHEET MOS INTEGRATED CIRCUIT µPD720110A USB2.0 HUB CONTROLLER The µPD720110A is an USB 2.0 hub device that comply with the Universal Serial Bus (USB) Specification Revision 2.0 and work up to 480 Mbps. USB2.0 compliant transceivers are integrated for upstream and all downstream ports. The µPD720110A works backward compatible either when any one of downstream ports is connected to an USB 1.1 compliant device, or when the upstream port is connected to a USB 1.1 compliant host. Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing. µPD720110A User’s Manual: S15738E FEATURES • Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps) • Certified by USB implementers forum and granted with USB 2.0 high-Speed Logo • High-speed or full-speed packet protocol sequencer for Endpoint 0/1 • 4 (Max.) downstream facing ports • All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction. • Supports split transaction to handle full-speed and low-speed transaction at downstream facing ports when Hub controller is working at high-speed mode. • One Transaction Translator per Hub and supports 4 non-periodic buffers • Supports self-powered mode only • Supports Over-current detection and Individual power control • Supports configurable vendor ID and product ID with external Serial ROM • Supports “non-removable” attribution on individual port • Uses 30 MHz X’tal, 30 MHz clock input, or 48 MHz clock input • Supports downstream port status with LED • HS detection indicator output • 3.3 V power supply The information in this document is subject to change without notice. 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Document No. S15737EJ5V0DS00 (5th edition) Date Published August 2004 NS CP (N) Printed in Japan NEC Electronics Corporation 2004 µPD720110A ORDERING INFORMATION Part Number Package µPD720110AGC-8EA 100-pin plastic LQFP (Fine pitch) (14 × 14) BLOCK DIAGRAM To Host/Hub downstream facing port Upstream facing port UP_PHY CDR SERDES UPC FS_REP SIE_2H CDR ALL_TT F_TIM DP(1)_PHY Downstream facing port #1 EP1 EP0 ROM I/F ROM DPC External Serial ROM DP(2)_PHY Downstream facing port #2 DP(3)_PHY Downstream facing port #3 APLL DP(4)_PHY Downstream facing port #4 CLKSEL X1_CLK/X2 OSB PPB(4:1) CSB(4:1) 2 Data Sheet S15737EJ5V0DS To Hub/Function upstream facing port To Hub/Function upstream facing port To Hub/Function upstream facing port To Hub/Function upstream facing port µPD720110A APLL : Generates all clocks of Hub. ALL_TT : Translates the high-speed transactions (split transactions) for full/low-speed device to full/low-speed transactions. ALL_TT buffers the data transfer from either upstream or downstream direction. For OUT transaction, ALL_TT buffers data from upstream port and sends it out to the downstream facing ports after speed conversion from high-speed to full/low-speed. For IN transaction, ALL_TT buffers data from downstream ports and sends it out to the upstream facing ports after speed conversion from full/low-speed to high-speed. CDR : Data & clock recovery circuit DPC : Downstream Port Controller handles Port Reset, Enable, Disable, Suspend and DP(n)_PHY : Downstream transceiver supports high-speed (480 Mbps), full-speed (12 Mbps), and EP0 : Endpoint 0 controller Resume low-speed (1.5 Mbps) transaction EP1 : Endpoint 1 controller F_TIM (Frame Timer) : Manages hub’s synchronization by using micro-SOF which is received at upstream port, and generates SOF packet when full/low-speed device is attached to downstream facing port. FS_REP : Full/low-speed repeater is enabled when the µPD720110A is worked at full-speed mode OSB : Oscillator Block ROM : Contains default Descriptors ROM I/F : Interface block for external Serial ROM which contains user-defined Descriptors SERDES : Serializer and Deserializer SIE_2H : Serial Interface Engine (SIE) controls USB2.0 and 1.1 protocol sequencer UP_PHY : Upstream Transceiver supports high-speed (480 Mbps), full-speed (12 Mbps) UPC : Upstream Port Controller handles Suspend and Resume transaction Data Sheet S15737EJ5V0DS 3 µPD720110A PIN CONFIGURATION (TOP VIEW) • 100-pin plastic LQFP (Fine pitch) (14 × 14) 76 80 85 90 1 75 5 70 10 65 15 60 20 55 25 50 45 40 35 VSS PWMODE NUMPORT VBUSM PORTRMV1 PORTRMV2 CSB1 CSB2 CSB3 CSB4 VSS PPB1 PPB2 PPB3 PPB4 HSMODE AMBERBP1 GREENBP1 AMBERBP2 GREENBP2 AMBERBP3 GREENBP3 AMBERBP4 GREENBP4 VSS 30 51 26 VDD VSS X1_CLK X2 VDD PLLLOCK OSL TS1 CLKSEL TS2 TS3 TS4 TS5 TS6 SYSRSTB VSS TS7 TS8 TSO SMD TS9 TS10 SCL SDA VDD 95 100 VSS RSDPD4 DPD4 VDD DMD4 RSDMD4 VSS RSDPD3 DPD3 VDD DMD3 RSDMD3 VSS RSDPD2 DPD2 VDD DMD2 RSDMD2 VSS RSDPD1 DPD1 VDD DMD1 RSDMD1 VSS µPD720110AGC-8EA 4 Data Sheet S15737EJ5V0DS VDD RPU VSS RSDPU DPU VDD DMU RSDMU VSS PC1 AVSS PC2 AVDD AVSS VSS N.C. RREF AVSS AVDD AVSS CLK30MO EPERR PORTRMV4 PORTRMV3 VDD µPD720110A Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 VDD 26 VSS 51 VDD 76 VSS 2 VSS 27 PWMODE 52 PORTRMV3 77 RSDMD1 3 X1_CLK 28 NUMPORT 53 PORTRMV4 78 DMD1 4 X2 29 VBUSM 54 EPERR 79 VDD 5 VDD 30 PORTRMV1 55 CLK30MO 80 DPD1 6 PLLLOCK 31 PORTRMV2 56 AVSS 81 RSDPD1 7 OSL 32 CSB1 57 AVDD 82 VSS 8 TS1 33 CSB2 58 AVSS 83 RSDMD2 9 CLKSEL 34 CSB3 59 RREF 84 DMD2 10 TS2 35 CSB4 60 N.C. 85 VDD 11 TS3 36 VSS 61 VSS 86 DPD2 12 TS4 37 PPB1 62 AVSS 87 RSDPD2 13 TS5 38 PPB2 63 AVDD 88 VSS 14 TS6 39 PPB3 64 PC2 89 RSDMD3 15 SYSRSTB 40 PPB4 65 AVSS 90 DMD3 16 VSS 41 HSMODE 66 PC1 91 VDD 17 TS7 42 AMBERBP1 67 VSS 92 DPD3 18 TS8 43 GREENBP1 68 RSDMU 93 RSDPD3 19 TSO 44 AMBERBP2 69 DMU 94 VSS 20 SMD 45 GREENBP2 70 VDD 95 RSDMD4 21 TS9 46 AMBERBP3 71 DPU 96 DMD4 22 TS10 47 GREENBP3 72 RSDPU 97 VDD 23 SCL 48 AMBERBP4 73 VSS 98 DPD4 24 SDA 49 GREENBP4 74 RPU 99 RSDPD4 25 VDD 50 VSS 75 VDD 100 VSS Data Sheet S15737EJ5V0DS 5 µPD720110A 1. PIN INFORMATION (1/2) Pin Name I/O Buffer Type Active Function Level X1_CLK I Input System clock input or oscillator in X2 O Output Oscillator out SYSRSTB I 5 V tolerant Input CLK30MO O (I/O) Low Asynchronous chip reset Output 30 MHz clock output CLKSEL I Input Clock select signal RPU A Analog External 1.5 kΩ pull-up resistor control DPD(4:1) B USB high speed D+ I/O Downstream high-speed data D+ DPU B USB high speed D+ I/O Upstream high-speed data D+ DMD(4:1) B USB high speed D− I/O Downstream high-speed data D− DMU B USB high speed D− I/O Upstream high-speed data D− RSDPD(4:1) O USB full-speed D+ O Downstream full-speed data D+ and RS resistor terminal RSDPU O USB full-speed D+ O Upstream full-speed data D+ and RS resistor terminal RSDMD(4:1) O USB full-speed D− O Downstream full-speed data D− and RS resistor terminal RSDMU O USB full-speed D− O Upstream full-speed data D− and RS resistor terminal RREF A Analog Reference resistor PC1 A Analog Capacitor for PLL PC2 A Analog Capacitor for PLL CSB(4:1) I (I/O) 5 V tolerant input Low Port’s overcurrent status input PPB(4:1) O 5 V tolerant N-ch open drain Low Port’s power supply control output NUMPORT I Input Number of available ports PWMODE I Input Power mode select VBUSM I Input VBus monitor PORTRMV(2:1) I Input Removable/Non-removable select PORTRMV(4:3) I (I/O) Input Removable/Non-removable select OSL O (I/O) Output High Indication for suspend state HSMODE O Output Low Indication for high-speed operation AMBERBP(4:1) O Output Low Indication for downstream port status with amber colored LED GREENBP(4:1) O Output Low Indication for downstream port status with green colored LED SCL O (I/O) SDA I/O SMD I EPERR 6 O (I/O) Output Serial ROM clock out I/O with 5 kΩ pull-up R Serial ROM data Input Serial ROM input enable Output Indication for serial ROM error Data Sheet S15737EJ5V0DS µPD720110A (2/2) Pin Name I/O Buffer Type Active Function Level PLLLOCK O (I/O) Output Indication when PLL is locked TS(1) I Input with 12 kΩ pull-down R Test signal TS(10:2) I Input Test signal I/O Test signal TSO I/O VDD VDD AVDD VDD for analog circuit VSS VSS AVSS VSS for analog circuit N.C. Not connected Remarks 1. “5 V tolerant“ means that the buffer is 3 V buffer with 5 V tolerant circuit. 2. The signal marked as “(I/O)” in the above table operates as I/O signals during testing. However, they do not need to be considered in normal use. Data Sheet S15737EJ5V0DS 7 µPD720110A 2. ELECTRICAL SPECIFICATIONS 2.1 Buffer List • 5 V schmitt buffer • 3.3 V oscillator block • 3.3 V input buffer • 3.3 V IOL = 6 mA output buffer • 3.3 V IOL = 12 mA output buffer • 3.3 V IOL = 6 mA schmitt I/O buffer with 5 kΩ pull-up resistor • 5 V IOL = 12 mA output buffer • 5 V IOL = 12 mA N-ch open drain buffer • USB2.0 interface SYSRSTB, CSB(4:1) X1_CLK, X2 CLKSEL, TS(10:1), SMD, PWMODE, NUMPORT, VBUSM, PORTRMV(4:1) PLLLOCK, OSL, TSO, SCL, CLK30MO EPERR SDA HSMODE, AMBERBP(4:1), GREENBP(4:1) PPB(4:1) RPU, DPU, DMU, RSDPU, RSDMU, DPD(4:1), DMD(4:1), RSDPD(4:1), RSDMD(4:1), RREF, PC1, PC2 Above, “5 V” refers to a 3 V buffer that is 5 V tolerant (has 5 V maximum voltage). Therefore, it is possible to have a 5 V connection for an external bus, but the output level will be only up to 3 V, which is the VDD voltage. 8 Data Sheet S15737EJ5V0DS µPD720110A 2.2 Terminology Terms Used in Absolute Maximum Ratings Parameter Power supply voltage Symbol VDD Meaning Indicates voltage range within which damage or reduced reliability will not result when power is applied to a VDD pin. Input voltage VI Indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. Output voltage VO Indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. Output current IO Indicates absolute tolerance values for DC current to prevent damage or reduced reliability when a current flow out of or into an output pin. Operating temperature TA Storage temperature Tstg Indicates the ambient temperature range for normal logic operations. Indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current are applied to the device. Terms Used in Recommended Operating Range Parameter Symbol Power supply voltage VDD High-level input voltage VIH Meaning Indicates the voltage range for normal logic operations occur when VSS = 0V. Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * If a voltage that is equal to or greater than the “MIN.” value is applied, the input voltage is guaranteed as high level voltage. Low-level input voltage VIL Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * If a voltage that is equal to or lesser than the “MAX.” value is applied, the input voltage is guaranteed as low level voltage. Hysteresis voltage VH Indicates the differential between the positive trigger voltage and the negative trigger voltage. Terms Used in DC Characteristics Parameter Off-state output leakage current Symbol IOZ Meaning Indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. Output short circuit current IOS Indicates the current that flows when the output pin is shorted (to GND pins) when output is at high-level. Low-level output current IOL Indicates the current that flows to the output pins when the rated low-level output voltage is being applied. High-level output current IOH Indicates the current that flows from the output pins when the rated highlevel output voltage is being applied. Data Sheet S15737EJ5V0DS 9 µPD720110A 2.3 Electrical Specifications Absolute Maximum Ratings Parameter Symbol Power supply voltage VDD Input voltage VI Condition Rating Unit −0.5 to +4.6 V 3.3 V input voltage VI < VDD + 0.5 V −0.5 to +4.6 V 5 V input voltage VI < VDD + 3.0 V −0.5 to +6.6 V 3.3 V output voltage VO < VDD + 0.5 V −0.5 to +4.6 V 5 V output voltage VO < VDD + 3.0 V −0.5 to +6.6 V Output voltage VO Operating temperature TA 0 to +70 °C Storage temperature Tstg −65 to +150 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Recommended Operating Ranges Parameter Symbol Operating voltage VDD High-level input voltage VIH Condition TYP. MAX. Unit 3.14 3.30 3.46 V 3.3 V High-level input voltage 2.0 VDD V 5.0 V High-level input voltage 2.0 5.5 V 3.3 V Low-level input voltage 0 0.8 V 5.0 V Low-level input voltage 0 0.8 V 0.3 1.5 V 10 ms 90 ms Low-level input voltage VIL Hysteresis voltage Input rise time for SYSRSTB Reset time VH Note tr tRST 0.005 Note Drive Low on SYSRSTB pin when only in Power On Reset timing. 10 MIN. Data Sheet S15737EJ5V0DS µPD720110A Figure 2-1. Power On Reset Timing VDD VDD VDD(MIN) 2.7 V RST 0.3 V VSS tRST tr Power supply ON DC Characteristics Parameter Off-state output leakage current Symbol IOZ Output short circuit current IOS Low-level output current IOL Condition MIN. VO = VDD or GND Note MAX. Unit ±10 µA −250 mA 3.3 V low-level output current VOL = 0.4 V 6 mA 3.3 V low-level output current VOL = 0.4 V 12 mA 5.0 V low-level output current VOL = 0.4 V 12 mA 3.3 V high-level output current VOH = 2.4 V −6 mA 3.3 V high-level output current VOH = 2.4 V −12 mA 5.0 V high-level output current VOH = 2.4 V −2 mA High-level output current IOH Note The output short circuit time is one second or less and is only for one pin on the LSI. Data Sheet S15737EJ5V0DS 11 µPD720110A USB Interface Block Parameter Serial Resistor between DPx (DMx) and Symbol Conditions RS MIN MAX Unit 35.64 36.36 Ω 40.5 49.5 Ω RSDPx (RSDMx). Output pin impedance ZHSDRV Includes RS resistor Bus pull-up resistor on upstream facing port RPU 1.425 1.575 kΩ Bus pull-up resistor on downstream facing port RPD 14.25 15.75 kΩ Termination voltage for upstream facing port pullup (full-speed) VTERM 3.0 3.6 V High-level input voltage (drive) VIH 2.0 High-level input voltage (floating) VIHZ 2.7 Low-level input voltage VIL Differential input sensitivity VDI (D+) − (D−) 0.2 Differential common mode range VCM Includes VDI range 0.8 2.5 V High-level output voltage VOH RL of 14.25 kΩ to GND 2.8 3.6 V Low-level output voltage VOL RL of 1.425 kΩ to 3.6 V 0.0 0.3 V SE1 VOSE1 0.8 Output signal crossover point voltage VCRS 1.3 2.0 V High-speed squelch detection threshold (differential signal) VHSSQ 100 150 mV High-speed disconnect detection threshold (differential signal) VHSDSC 525 625 mV High-speed data signaling common mode voltage range VHSCM −50 +500 mV High-speed differential input signaling level See Figure 2-5. Input Levels for Low-/full-speed: V 3.6 V 0.8 V V Output Levels for Low-/full-speed: V Input Levels for High-speed: Output Levels for High-speed: High-speed idle state VHSOI −10.0 +10 mV High-speed data signaling high VHSOH 360 440 mV High-speed data signaling low VHSOL −10.0 +10 mV Chirp J level (different signal) VCHIRPJ 700 1100 mV Chirp K level (different signal) VCHIRPK −900 −500 mV 12 Data Sheet S15737EJ5V0DS µPD720110A Figure 2-2. Differential Input Sensitivity Range for Low-/full-speed Differential Input Voltage Range Differential Output Crossover Voltage Range 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 4.6 Input Voltage Range (Volts) Figure 2-3. Full-speed Buffer VOH/IOH Characteristics for High-speed Capable Transceiver VDD-3.3 VDD-2.8 VDD-2.3 VDD-1.8 VDD-1.3 VDD-0.8 VDD-0.3 VDD 0 Iout (mA) -20 -40 Min. -60 Max. -80 Vout (V) Figure 2-4. Full-speed Buffer VOL/IOL Characteristics for High-speed Capable Transceiver 80 Max. 60 Iout (mA) -1.0 Min. 40 20 0 0 0.5 1 1.5 2 2.5 3 Vout (V) Data Sheet S15737EJ5V0DS 13 µPD720110A Figure 2-5. Receiver Sensitivity for Transceiver at DP/DM Level 1 +400 mV Differential Point 3 Point 4 Point 1 0V Differential Point 2 Point 5 Point 6 −400 mV Differential Level 2 Unit Interval 0% 100% Figure 2-6. Receiver Measurement Fixtures Test Supply Voltage 15.8 Ω USB Connector Nearest Device Vbus D+ DGnd 15.8 Ω 143 Ω 14 50 Ω Coax 50 Ω Coax 143 Ω Data Sheet S15737EJ5V0DS + To 50 Ω Inputs of a High Speed Differential Oscilloscope, or 50 Ω Outputs of a High Speed Differential Data Generator − µPD720110A Power Consumption Parameter Symbol Power Consumption PW-0 Condition TYP. Unit Hub controller is operating at full-speed mode. 185 mA Hub controller is operating at high-speed mode. 270 mA Hub controller is operating at full-speed mode. 190 mA Hub controller is operating at high-speed mode. 400 mA Hub controller is operating at full-speed mode. 193 mA Hub controller is operating at high-speed mode. 460 mA Hub controller is operating at full-speed mode. 196 mA Hub controller is operating at high-speed mode. 525 mA 1.3 mA The power consumption under the state without suspend. All the ports does not connect to any function. PW-2 The power consumption under the state without suspend. The number of active ports is 2. PW-3 PW_S Note 2 The power consumption under the state without suspend. The number of active ports is 3. PW-4 Note 1 Note 2 The power consumption under the state without suspend. The Note 2 number of active ports is 4. The power consumption under suspend state. The internal clock is stopped. Notes 1. When any device is not connected to all the ports of HC, the power consumption for HC does not depend on the number of active ports. 2. The number of active ports is set by the value of Port No field in PCI configuration space EXT register. System Clock Ratings Parameter Clock frequency Symbol fCLK Condition X’tal MIN. TYP. MAX. Unit −500 30 +500 MHz ppm Oscillator block Clock Duty cycle tDUTY ppm −500 ppm 48 +500 ppm MHz 40 50 60 % Remarks 1. Recommended accuracy of clock frequency is ± 100 ppm. 2. Required accuracy of X’tal or oscillator block is including initial frequency accuracy, the spread of X’tal capacitor loading, supply voltage, temperature, and aging, etc. Data Sheet S15737EJ5V0DS 15 µPD720110A AC Characteristics (VDD = 3.14 to 3.46 V, TA = 0 to +70°C) USB Interface Block (1/4) Parameter Symbol Conditions MIN. MAX. Unit Low-speed Electrical Characteristics Rise time (10% to 90%) tLR CL = 50 pF to 150 pF, RS = 36 Ω 75 300 ns Fall time (90% to 10%) tLF CL = 50 pF to 150 pF, RS = 36 Ω 75 300 ns Differential rise and fall time matching tLRFM (tLR/tLF) Note 80 125 % Low-speed data rate tLDRATHS Average bit rate 1.49925 1.50075 Mbps Hub differential data delay (Figure 2-9) tLHDD 300 ns Hub differential driver jitter (including cable) (Figure 2-9): Downstream facing port To next transition For paired transitions tLDHJ1 tLDHJ2 −45 −45 +45 +45 ns ns tLUHJ1 tLUHJ2 −45 −15 +45 +15 ns ns tLSOP −60 +60 ns tLEOPD 0 200 ns tLHESK −300 +300 ns 4 20 ns 4 20 ns 90 111.11 % 11.9940 12.0060 Mbps 0.9995 1.0005 ms 42 ns −3.5 −4.0 +3.5 +4.0 ns ns −2 +5 ns Upstream facing port To next transition For paired transitions Data bit width distortion after SE0 (Figure 2-9) Hub EOP delay relative to THDD (Figure 2-10) Hub EOP output width skew (Figure 2-10) Full-speed Electrical Characteristics Rise time (10% to 90%) tFR CL = 50 pF, RS = 36 Ω Fall time (90% to 10%) tFF CL = 50 pF, RS = 36 Ω Differential rise and fall time matching tFRFM (tFR/tFF) Full-speed data rate tFDRATHS Average bit rate Frame interval tFRAME Consecutive frame interval jitter tRFI No clock adjustment Note Source jitter total (including frequency tolerance) (Figure 2-11): To next transition For paired transitions Source jitter for differential transition to tDJ1 tDJ2 tFDEOP SE0 transition (Figure 2-12) Note Excluding the first transition from the Idle state. 16 Data Sheet S15737EJ5V0DS µPD720110A (2/4) Parameter Symbol Conditions MIN. MAX. Unit −18.5 −9 +18.5 +9 ns ns 175 ns Full-speed Electrical Characteristics (Continued) Receiver jitter (Figure 2-13): To Next Transition For Paired Transitions tJR1 tJR2 Source SE0 interval of EOP (Figure 2-12) tFEOPT 160 Receiver SE0 interval of EOP (Figure 2-12) tFEOPR 82 Width of SE0 interval during differential transition tFST 14 ns Hub differential data delay (with cable) tHDD1 70 ns Hub differential data delay (without cable) (Figure 2-9) tHDD2 44 ns ns Hub differential driver jitter (including cable) (Figure 2-9): tHDJ1 tHDJ2 −3 −1 +3 +1 ns ns Data bit width distortion after SE0 Figure 2-9) tFSOP −5 +5 ns Hub EOP delay relative to THDD (Figure 2-10) tFEOPD 0 15 ns Hub EOP output width skew (Figure 2-10) tFHESK −15 +15 ns Rise time (10% to 90%) tHSR 500 ps Fall time (90% to 10%) tHSF 500 ps Driver waveform See Figure 2-7. High-speed data rate tHSDRAT 479.760 480.240 Mbps Microframe interval tHSFRAM 124.9375 125.0625 µs Consecutive microframe interval difference tHSRFI 4 highspeed Bit times Data source jitter See Figure 2-7. Receiver jitter tolerance See Figure 2-5. Hub data delay (without cable) tHSHDD 36 highspeed+4 ns Bit times Hub data jitter See Figure 2-5, Figure 2-7. Hub delay variation range tHSHDV 5 highspeed Bit times 2.5 2.5 2000 12000 µs µs 2.0 2.5 µs To next transition For paired transitions High-speed Electrical Characteristics Hub Event Timings Time to detect a downstream facing port tDCNN connect event (Figure 2-15): Awake hub Suspended hub Time to detect a disconnect event at a hub’s downstream facing port (Figure 2-14) tDDIS Data Sheet S15737EJ5V0DS 17 µPD720110A (3/4) Parameter Symbol Conditions MIN. MAX. Unit Hub Event Timings (Continued) Duration of driving resume to a tDRSMDN 20 ms downstream port (only from a controlling hub) Time from detecting downstream resume to rebroadcast tURSM 1.0 ms Duration of driving reset to a downstream facing port (Figure 2-16) tDRST 10 20 ms Time to detect a long K from upstream tURLK 2.5 100 µs Time to detect a long SE0 from upstream tURLSE0 2.5 10000 µs Duration of repeating SE0 upstream (for low-/full-speed repeater) tURPSE0 23 FS Bit times Inter-packet delay (for high-speed) of packets traveling in same direction tHSIPDSD 88 Bit times Inter-packet delay (for high-speed) of packets traveling in opposite direction tHSIPDOD 8 Bit times Inter-packet delay for device/root hub tHSRSPIPD1 Only for a SetPortFeature (PORT_RESET) request 192 response with detachable cable for highspeed Time of which a Chirp J or Chirp K must be tFILT Bit times µs 2.5 continuously detected (filtered) by hub or device during Reset handshake Time after end of device Chirp K by which tWTDCH 100 µs hub must start driving first Chirp K in the hub’s chirp sequence tDCHBIT 40 60 µs Time before end of reset by which a hub must end its downstream chirp sequence tDCHSE0 100 500 µs Time from internal power good to device pulling D+ beyond VIHZ (Figure 2-16) tSIGATT 100 ms Debounce interval provided by USB system software after attach (Figure 2-16) tATTDB 100 ms Maximum duration of suspend averaging interval tSUSAVGI 1 s Period of idle bus before device can initiate resume tWTRSM 5 Duration of driving resume upstream tDRSMUP 1 Resume recovery time tRSMRCY Time to detect a reset from upstream for non high-speed capable devices tDETRST Reset recovery time (Figure 2-16) tRSTRCY Time for which each individual Chirp J or Chirp K in the chirp sequence is driven downstream by hub during reset 18 Remote-wakeup is enabled Data Sheet S15737EJ5V0DS ms 15 10 2.5 ms ms 10000 µs 10 ms µPD720110A (4/4) Parameter Symbol Conditions MIN. MAX. Unit Hub Event Timings (Continued) Inter-packet delay for full-speed tIPD 2 Bit times Inter-packet delay for device response with detachable cable for full-speed tRSPIPD1 6.5 Bit times SetAddress() completion time tDSETADDR 50 ms Time to complete standard request with no data tDRQCMPLTND 50 ms Time to deliver first and subsequent (except last) data for standard request tDRETDATA1 500 ms Time to deliver last data for standard request tDRETDATAN 50 ms Time for which a suspended hub will see a tFILTSE0 2.5 tWTRSTFS 2.5 3000 ms tWTREV 3.0 3.125 ms tWTRSTHS 100 875 ms tUCH 1.0 µs continuous SE0 on upstream before beginning the high-speed detection handshake Time a hub operating in non-suspended full-speed will wait after start of SE0 on upstream before beginning the high-speed detection handshake Time a hub operating in high-speed will wait after start of SE0 on upstream before reverting to full-speed Time a hub will wait after reverting to fullspeed before sampling the bus state on upstream and beginning the high-speed will wait after start of SE0 on upstream before reverting to full-speed Minimum duration of a Chirp K on ms upstream from a hub within the reset protocol Time after start of SE0 on upstream by tUCHEND 7.0 ms Time between detection of downstream chip and entering high-speed state tWTHS 500 µs Time after end of upstream Chirp at which tWTFS 2.5 ms which a hub will complete its Chirp K within the reset protocol 1.0 hub reverts to full-speed default state if no downstream Chirp is detected Data Sheet S15737EJ5V0DS 19 µPD720110A Clock & Overcurrent Response Timing Parameter Symbol Condition MIN. TYP. MAX. 33.33 Unit CLK30MO cycle time tC3C ns CLK30MO high level width tC3H 15.9 17.5 ns CLK30MO low level width tC3L 15.9 17.5 ns Overcurrent response time from CSB low to PPB high (Figure 2-19) tOC 500 625 µs Figure 2-7. Transmit Waveform for Transceiver at DP/DM Level 1 +400 mV Differential Point 3 Point 4 Point 1 0V Differential Point 2 Point 5 Point 6 −400 mV Differential Level 2 Unit Interval 0% 100% Figure 2-8. Transmitter Measurement Fixtures Test Supply Voltage 15.8 Ω USB Connector Nearest Device Vbus D+ DGnd 15.8 Ω 143 Ω 20 50 Ω Coax 50 Ω Coax 143 Ω Data Sheet S15737EJ5V0DS + To 50 Ω Inputs of a High Speed Differential Oscilloscope, or 50 Ω Outputs of a High Speed Differential Data Generator − µPD720110A Timing Diagram Figure 2-9. Hub Differential Delay, Differential Jitter, and SOP Distortion Upstream End of Cable Crossover Point Upstream Port of Hub 50% Point of Initial Swing VSS VSS Downstream Port of Hub Hub Delay Downstream tHDD1 VSS 50% Point of Initial Swing Hub Delay Downstream tHDD2 Downstream Port of Hub VSS A. Downstream Hub Delay with Cable B. Downstream Hub Delay without Cable Downstream Port of Hub Crossover Point VSS Upstream Port or End of Cable Hub Delay Upstream tHDD1 tHDD2 VSS Crossover Point C. Upstream Hub Delay with or without Cable Upstream end of cable Upstream port Downstream port Receptacle Plug Host or Hub Hub Function Downstream signaling Upstream signaling Hub Differential Jitter: tHDJ1 = tHDDx(J) − tHDDx(K) or tHDDx(K) − tHDDx(J) Consecutive Transitions tHDJ2 = tHDDx(J) − tHDDx(J) or tHDDx(K) − tHDDx(K) Paired Transitions Bit after SOP Width Distortion (same as data jitter for SOP and next J transition): tFSOP = tHDDx(next J) − tHDDx(SOP) Low-speed timings are determined in the same way for: tLHDD, tLDHJ1, tLDJH2, tLUHJ1, tLUJH2, and tLSOP Data Sheet S15737EJ5V0DS 21 µPD720110A Figure 2-10. Hub EOP Delay and EOP Skew Upstream End of Cable 50% Point of Initial Swing Upstream Port of Hub VSS Crossover Point Extended VSS tEOP- tEOP+ tEOP- tEOP+ Downstream Port of Hub Downstream Port of Hub VSS VSS A. Downstream EOP Delay with Cable B. Downstream EOP Delay without Cable Crossover Point Extended Downstream Port of Hub VSS tEOP- tEOP+ Crossover Point Extended Upstream Port or End of Cable VSS C. Upstream EOP Delay with or without Cable EOP Delay: tFEOPD = tEOPy − tHDDx (tEOPy means that this equation applies to tEOP- and tEOP+) EOP Skew: tFHESK = tEOP+ − tEOPLow-speed timings are determined in the same way for: tLEOPD and tLHESK 22 Data Sheet S15737EJ5V0DS µPD720110A Figure 2-11. USB Differential Data Jitter for Full-speed tPERIOD Differential Data Lines Crossover Points Consecutive Transitions N × tPERIOD + tDJ1 Paired Transitions N × tPERIOD + tDJ2 Figure 2-12. USB Differential-to-EOP Transition Skew and EOP Width for Full-speed tPERIOD Differential Data Lines Crossover Point Extended Crossover Point Diff. Data-toSE0 Skew N × tPERIOD + tFDEOP, tLDEOP Source EOP Width: tFEOPT tLEOPT Receiver EOP Width: tFEOPR tLEOPR Figure 2-13. USB Receiver Jitter Tolerance for Full-speed tPERIOD Differential Data Lines tJR tJR1 tJR2 Consecutive Transitions N × tPERIOD + tJR1 Paired Transitions N × tPERIOD + tJR2 Data Sheet S15737EJ5V0DS 23 µPD720110A Figure 2-14. Low-/full-speed Disconnect Detection D+/DVIHZ (min) VIL D-/D+ VSS tDDIS Device Disconnected Disconnect Detected Figure 2-15. Full-/high-speed Device Connect Detection D+ VIH DVSS tDCNN Device Connected Connect Detected Figure 2-16. Power-on and Connection Events Timing Hub port power OK Reset Recovery Time Attach Detected Hub port power-on ≥ 4.01 V t2SUSP VBUS tDRST USB System Software reads device speed VIH (min) VIH D+ or D− tSIGATT ∆t1 24 tATTDB Data Sheet S15737EJ5V0DS tRSTRCY µPD720110A Figure 2-17. Clock Output tC3C CLKO30MO tC3L tC3H Figure 2-18. CSB/PPB Timing 500 µs 500 µs 500 µs 500 µs Hub power supply BUS reset Up port D+ line PPB pin output Output cut-off CSB pin input DEVICE connection inrush current Port power supply ON Overcurrent generation CSB pin operation region Power supply ON Bus power: Up port connection Self-power: Power supply ON CSB detection delay time CSB active period Note The active period of the CSB pin is in effect only when the PPB pin is ON. There is a delay time of approximately 500 µs duration at the CSB pin. Figure 2-19. Overcurrent Response Timing VDD CSB(4:1) VSS tOC VDD PPB(4:1) VSS Data Sheet S15737EJ5V0DS 25 µPD720110A 3. PACKAGE DRAWING 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) A B 75 76 51 50 detail of lead end S C D R Q 26 25 100 1 F G H I J M K P S N S L M NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 16.00±0.20 B 14.00±0.20 C 14.00±0.20 D 16.00±0.20 F 1.00 G 1.00 H 0.22 +0.05 −0.04 I J 0.08 0.50 (T.P.) K 1.00±0.20 L 0.50±0.20 M 0.17 +0.03 −0.07 N 0.08 P 1.40±0.05 Q 0.10±0.05 R 3° +7° −3° S 1.60 MAX. S100GC-50-8EU, 8EA-2 26 Data Sheet S15737EJ5V0DS µPD720110A 4. RECOMMENDED SOLDERING CONDITIONS The µPD720110A should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) µPD720100AGC-8EA: 100-pin plastic LQFP (Fine pitch) (14 × 14) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Symbol IR35-102-3 Count: Three times or less Exposure limit: 2 days Partial heating Note (after that, prebake at 125°C for 10 hours) Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) – Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Data Sheet S15737EJ5V0DS 27 µPD720110A [MEMO] 28 Data Sheet S15737EJ5V0DS µPD720110A [MEMO] Data Sheet S15737EJ5V0DS 29 µPD720110A [MEMO] 30 Data Sheet S15737EJ5V0DS µPD720110A NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet S15737EJ5V0DS 31 µPD720110A USB logo is a trademark of USB Implementers Forum, Inc. • The information in this document is current as of August, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. 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