DATA SHEET MOS INTEGRATED CIRCUIT µPD75212A 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The µPD75212A is a microcomputer with a CPU capable of 1-, 4-, and 8-bit data processing, ROM, RAM, I/O ports, a fluorescent display tube controller/driver, a watch timer, a timer/pulse generator capable of outputting 14-bit PWM, a serial interface and a vectored interrupt function integrated on a single-chip. The µPD75212A is a version of the µ PD75216A with a small ROM capacity (12K). The µPD75212A uses the VCR, ECR and CD fluorescent display tubes as display devices and is most suitable for applications requiring the timer/watch function and high-speed interrupt servicing. It can help to provide the unit with many functions and to decrease performance costs. Functions are described in detail in the following User’s Manual. Be sure to read when carrying out design work. µPD75216A User’s Manual: IEM-988 FEATURES • • • • Architecture equal to that of an 8-bit microcomputer High-speed operation : Minimum instruction execution time : 0.95 µs (when operated at 4.19 MHz) Instruction execution time variable function realizing a wide range of operating voltages On-chip large-capacity program memory : 12K bytes • Watch operation with an ultra low current consumption : 5 µA TYP. (at the 3 V operation) • On-chip programmable fluorescent display tube controller/driver • Timer function : 4 ch • 14-bit PWM output capability with the voltage synthesizer type electronic tuner • Buzzer output capability • Interrupt function with importance attached to applications • For power-off detection • For remote controlled reception • Product with an on-chip PROM : µPD75P216A, µPD75P218 (on-chip EPROM : WQFN package) APPLICATION FIELD VCR, CD player, ECR, etc. The information in this document is subject to change without notice. Document No. IC-2584D (O. D. No. IC-7552D) Date Published February 1994 P Printed in Japan The mark ★ shows major revised points. © NEC Corporation 1990 µPD75212A ORDERING INFORMATION Ordering Code µ PD75212ACW-××× µ PD75212AGF-×××-3BE Remarks Package 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP (14 × 20 mm) Quality Grade Standard Standard ××× is a ROM code number. Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. 2 µPD75212A LIST OF FUNCTIONS Item Function Instruction execution time • 0.95, 1.91, 15.3 µs (Main system clock : 4.19 MHz operation) • 122 µs (Subsystem clock : 32.768 kHz operation) On-chip memory ROM 12160 × 8 bits RAM 512 × 4 bits General register • 4-bit manipulation : 8 × 4 banks • 8-bit manipulation : 4 × 4 banks Input/output port 33 FIP ® dual-function pin included FIP dedicated pin excluded 8 20 CMOS input pin CMOS input/output pins • Direct LED drive capability : 8 • On-chip pull-down resistor by mask option capability : 4 1 CMOS output pin PWM/pulse output 4 P-ch open-drain, high-voltage, high-current output pin • LED drive capability • On-chip pull-down resistor by mask option capability FIP controller/driver • • • • • Timer 4 channels Serial interface • MSB start/LSB start switchable • Serial bus configuration capability Vectored interrupt External : 3, Internal : 5 Test input External : 1, Internal : 1 System clock oscillator • Ceramic/crystal oscillator for main system clock oscillation : 4.194304 MHz standard • Crystal oscillator for subsystem clock oscillation : 32.768 kHz standard Standby function STOP/HALT mode Mask option • Power-on reset, power-on flag • High-voltage port : Pull-down resistor or open-drain output • Port 6 : Pull-down resistor Operating temperature range –40 to +85 °C Operating voltage 2.7 to 6.0 V (standby data retention : 2.0 to 6.0 V) Package • 64-pin plastic shrink DIP (750 mil) • 64-pin plastic QFP (14 × 20 mm) No. of segments : 9 to 16 segments No. of digits : 9 to 16 digits Dimmer function : 8 levels On-chip pull-down resistor by mask option capability Key scan interrupt generation • • • • Timer/pulse generator : 14-bit PWM output enabled Watch timer : Buzzer output enabled Timer/event counter Basic interval timer : Watchdog timer application capability 3 µPD75212A CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ......................................................................................................... 6 2. BLOCK DIAGRAM ...................................................................................................................................... 8 3. PIN FUNCTIONS ........................................................................................................................................ 9 3.1 PORT PINS ............................................................................................................................................................. 9 3.2 NON-PORT PINS .................................................................................................................................................. 10 3.3 PIN INPUT/OUTPUT CIRCUIT LIST .................................................................................................................... 11 3.4 UNUSED PINS TREATMENT .............................................................................................................................. 12 3.5 P00/INT4 PIN AND RESET PIN OPERATING PRECAUTIONS ......................................................................... 13 3.6 XT1, XT2 AND P50 PIN OPERATING PRECAUTIONS ..................................................................................... 13 4. MEMORY CONFIGURATION ................................................................................................................... 14 5. PERIPHERAL HARDWARE FUNCTIONS ................................................................................................. 17 5.1 PORTS .................................................................................................................................................................... 17 5.2 CLOCK GENERATOR ............................................................................................................................................ 18 5.3 5.4 5.5 5.6 BASIC INTERVAL TIMER ..................................................................................................................................... 19 WATCH TIMER ...................................................................................................................................................... 20 TIMER/EVENT COUNTER ................................................................................................................................... 21 TIMER/PULSE GENERATOR ............................................................................................................................... 22 5.7 SERIAL INTERFACE ............................................................................................................................................. 23 5.8 FIP CONTROLLER /DRIVER ................................................................................................................................ 25 5.9 POWER-ON FLAG (MASK OPTION) ................................................................................................................... 27 6. INTERRUPT FUNCTIONS ......................................................................................................................... 28 7. STANDBY FUNCTIONS ............................................................................................................................ 30 8. RESET FUNCTIONS .................................................................................................................................. 31 9. INSTRUCTION SET ................................................................................................................................... 34 10. MASK OPTION SELECTION .................................................................................................................... 43 11. APPLICATION BLOCK DIAGRAM ............................................................................................................ 44 11.1 VCR TIMER TUNER ............................................................................................................................................. 44 11.2 CD PLAYER .......................................................................................................................................................... 45 11.3 ECR ....................................................................................................................................................................... 45 12. ELECTRICAL SPECIFICATIONS ............................................................................................................... 46 13. CHARACTERISTIC CURVES .................................................................................................................... 59 14. PACKAGE INFORMATION ....................................................................................................................... 63 4 µPD75212A 15. RECOMMENDED SOLDERING CONDITIONS ........................................................................................ 66 APPENDIX A. DEVELOPMENT TOOLS ......................................................................................................... 67 APPENDIX B. RELATED DOCUMENTS ......................................................................................................... 68 5 µPD75212A 1. PIN CONFIGURATION (TOP VIEW) P02/SO P03/SI P10/INT0 P11/INT1 P12/INT2 P13/TI0 VDD S4 S5 S6 S7 S8 S9 VPRE VLOAD T15/S10 T14/S11 T13/S12/PH0 T12/S13/PH1 T11/S14/PH2 T10/S15/PH3 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 RESET P53 P52 P51 P50 XT2 XT1 P20 P21 P22 P23/BUZ P30 P31 P32 P33 P60 P61 P62 P63 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 52 32 P01/SCK P42 53 31 P00/INT4 P43 54 30 S0 PPO 55 29 S1 X1 56 28 S2 X2 57 27 S3 VSS 58 26 VDD XT1 59 25 S4 XT2 60 24 S5 P50 61 23 S6 P51 62 22 S7 P52 63 21 S8 P53 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 S9 VLOAD T15/S10 T14/S11 T13/S12/PH0 T12/S13/PH1 T11/S14/PH2 T10/S15/PH3 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 µPD75212AGF-×××-3BE VPRE P41 RESET 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 µPD75212ACW-××× P40 S3 S2 S1 S0 P00/INT4 P01/SCK P02/SO P03/SI P10/INT0 P11/INT1 P12/INT2 P13/TI0 P20 P21 P22 P23/BUZ P30 P31 P32 P33 P60 P61 P62 P63 P40 P41 P42 P43 PPO X1 X2 VSS µPD75212A PIN NAME P00-P03 : Port 0 SCK P10-P13 P20-P23 P30-P33 P40-P43 : : : : Port Port Port Port SO : SI : INT0, INT1, INT4 : INT2 : Serial Output Serial Input External Vectored Interrupt 0, 1, 4 External Test Input 2 P50-P53 P60-P63 PH0-PH3 T0-T15 : : : : Port 5 Port 6 Port H Digit Output 0-15 TI0 X1, X2 XT1, XT2 RESET : : : : Timer Input 0 Main System Clock Oscillation 1, 2 Subsystem Clock Oscillation 1, 2 Reset Input S0-S15 PPO BUZ : Segment Output 0-15 : Pulse Output : Fixed Frequency Output VLOAD, VPRE : FIP Driver Power Supply Pin 1 2 3 4 : Serial Clock 7 INTBT TI0/P13 PROGRAM COUNTER(14) ALU CY 4 P00–P03 PORT1 4 P10–P13 PORT2 4 P20–P23 PORT3 4 P30–P33 PORT4 4 P40–P43 PORT5 4 P50–P53 PORT6 4 P60–P63 10 T0–T9 4 T10/S15/PH3– T13/S12/PH0 2 T14/S11,T15/ S10 10 S0–S9 SP(8) TIMER/EVENT COUNTER #0 BANK INTT0 TIMER/PULSE GENERATOR PORT0 GENERAL REG. 2. BLOCK DIAGRAM 8 BASIC INTERVAL TIMER PPO INTTPG SI/P03 SO/P02 SERIAL INTERFACE ROM PROGRAM MEMORY 12160 × 8 BITS DECODE AND CONTROL SCK/P01 RAM DATA MEMORY 512 × 4 BITS INTSIO INT0/P10 FIP CONTROLLER/ DRIVER INT1/P11 INT2/P12 INT4/P00 INTERRUPT CONTROL INTW WATCH TIMER f X/2 N CLOCK DIVIDER SYSTEM CLOCK GENERATOR SUB MAIN VPRE VLOAD CPU CLOCK Φ STAND BY CONTROL INTKS BUZ/P23 XT1 XT2 X1 X2 V DD VSS RESET 4 PH0–PH3 µPD75212A PORTH µPD75212A 3. PIN FUNCTIONS 3.1 PORT PINS I/O DualFunction Pin P00 Input INT4 P01 Input/output SCK F P02 Input/output SO G P03 Input SI B P10 Input INT0 P11 INT1 P12 INT2 P13 TI0 P20 P21 * Input / Output Circuit Type * Pin Name Input/ output ––– Function 4-bit input port (PORT0). 8-Bit After Reset I/O × Noise elimination function available Input B Input B Input E Input E Input E Input E Noise elimination function available 4-bit input port (PORT1). 4-bit input/output port (PORT2). × ––– P22 ––– P23 BUZ P30 to P33 Input/ output ––– Programmable 4-bit input/output port (PORT3). Input/output specifiable in bit-wise. P40 to P43 Input/ output ––– 4-bit input/output port (PORT4). LED direct drive capability. P50 to P53 Input/ output ––– 4-bit input/output port (PORT5). LED direct drive capability. P60 to P63 Input/ output ––– Programmable 4-bit input/output port (PORT6). Input/output specifiable in bit-wise. On-chip pull-down resistor available (mask option). Suitable for key input. × Input V PH0 Output T13/S12 4-bit P-ch open-drain, high-voltage, high-current output port (PORTH). LED direct drive capability. On-chip pull-down resistor available (mask option). × Low level (with an onchip pulldown resistor) or high impedance. I PH1 T12/S13 PH2 T11/S14 PH3 T10/S15 ● Schmitt-triggered inputs are circled. 9 µPD75212A 3.2 NON-PORT PINS Pin Name T0 to T9 I/O DualFunction Pin Output ––– T10/S15 to T13/S12 PH3 to PH0 T14/S11, T15/S10 ––– Function FIP controller/ driver output pins. Pull-down resistor can be incorporated in bit-wise (mask option). Digit output high-voltage high-current output. Digit/segment output dual-function high-voltage high-current output. Extra pins can be used as PORTH. Digit/segment output dual-function high-voltage high-current output. Static output also possible. S9 Segment output high-voltage output. Static output also possible. S0 to S8 Segment high-voltage output. After Reset Input / Output Circuit Type * Low level (With an onchip pulldown resistor) or high impedance (without a pull-down resistor) I High impedance D PPO Output ––– Timer/pulse generator pulse output. TI0 Input P13 External event pulse input for timer/event counter. SCK Input/output P01 Serial clock input/output. Input F SO Input/output P02 Serial data output pin or serial data input/output. Input G SI Input P03 Serial data input or normal input. Input B INT4 Input P00 Edge-detected vectored interrupt input (rising and falling edge detection). B INT0 Input P10 Edge-detected vectored interrupt input with noise elimination function (detection edge selection possible). B B INT1 P11 B INT2 Input P12 Edge-detected testable input (rising edge detection). BUZ Input/output P23 Fixed frequency output (for buzzer or system clock trimming). X1, X2 Input ––– Crystal/ceramic connect pin for main system clock oscillation. External clock input to X1 and its inverted clock input to X2. XT1 Input ––– XT2 ––– Crystal connect pin for subsystem clock oscillation. External clock input to XT1 and XT2 open. ––– System reset input (low level active). B VPRE ––– FIP controller/driver output buffer power supply. I VLOAD ––– FIP controller/driver pull-down resistor connect pin. I VDD ––– Positive power supply. VSS ––– GND potential. RESET * 10 Input Schmitt-triggered inputs are circled. Input E µPD75212A 3.3 PIN INPUT/OUTPUT CIRCUIT LIST TYPE A TYPE F VDD data IN/OUT Type D output disable P-ch IN Type B N-ch Input/Output Circuit Consisting of Type D Push-Pull Output and Type B Schmitt-Triggered Input CMOS-Specified Input Buffer TYPE B TYPE G VDD P-ch output disable data P-ch IN/OUT IN N-ch Type B Schmitt-Triggered Input Having Hysteresis Characteristics Input/Output Circuit Capable of Switching between Push-Pull Output and N-ch Open-Drain Output (with P-ch OFF). TYPE D TYPE V VDD data data IN/OUT P-ch OUT output disable Type D output disable N-ch Type A Pull-down Resistor Push-Pull Output which can be Set to Output High Impedance (with Both P-ch and N-ch Set to OFF) TYPE E TYPE I VDD data output disable (Mask Option) VDD IN/OUT Type D data P-ch N-ch Type A P-ch OUT Pull-down Resistor (Mask Option) VLOAD VPRE Input/Output Circuit Consisting of Type D Push-Pull Output and Type A Input Buffer 11 µPD75212A 3.4 UNUSED PINS TREATMENT Pin Recommended Connection P00/INT4 Connect to VSS P01/SCK Connect to VSS or VDD P02/SO P03/SI P10/INT0 to P12/INT2 Connect to VSS P13/TI0 P20 to P22 Input state : Connect to VSS or V DD P23/BUZ Ouput state : Leave open P30 to P33 P40 to P43 P50 to P53 P60 to P63 PPO Leave open S0 to S9 T15/S10 to T14/S11 T0 to T9 T10/S15/PH3 to T13/S12/PH0 XT1 Connect to VSS or VDD XT2 Leave open RESET when there is an on- Connect to VDD chip power-on reset circuit VLOAD when there is no onchip load resistor 12 Connect to VSS or VDD µPD75212A 3.5 P00/INT4 PIN AND RESET PIN OPERATING PRECAUTIONS P00/INT4 and RESET pins have the function (especially for IC test) to test µPD75212A internal operations in addition to the functions described in sections 3.1 and 3.2. The test mode is set when a voltage larger than VDD is applied to one of these pins. If noise larger than VDD is applied in normal operation, the test mode may be set thereby adversely affecting normal operation. Since there is a display output pin having a high-voltage amplitude (35 V) next to the P00/INT4 and RESET pins, if cables for the related signals are routed in parallel, wiring noise larger than VDD may be applied to the P00/INT4 and RESET pins causing errors. Thus, carry out wiring so that wiring noise can be minimized, If noise still cannot be suppressed, take the measure against noise using the following external components. • Connect diode with small VF (0.3 V or less) between VDD and P00/INT4, RESET • Connect a capacitor between the pins and VDD. VDD VDD VDD VDD P00/INT4, RESET P00/INT4, RESET 3.6 XT1, XT2 AND P50 PIN OPERATING PRECAUTIONS When selecting the 32.768 kHz subsystem clock connected to the XT1 and XT2 pins as the watch timer source clock, the signal to be input or output to the P50 pin next to the XT2 pin must be a signal required to be switched between high and low the minimum number of times (once or less per second). If the P50 pin signal is switched frequently between high and low, a spike is generated in the XT2 pin because of capacitance coupling of the P50 and XT2 pins and the correct watch functions cannot be achieved (the watch becomes fast). If it is necessary to allow the P50 pin signal to switch between high and low, mount an external capacitor to the P50 pin as shown below. µPD75212A P50 XT1 XT2 0.0068 µ F 32.768 kHz 13 µPD75212A 4. MEMORY CONFIGURATION • Program memory (ROM) ................................. 12160 words × 8 bits • 0000H to 0001H : Vector table for writing program start address by reset • 0002H to 000FH : Vector table for writing program start address by interrupt • 0020H to 007FH : Table area to be referred to by GETI instruction • Data Memory • Data area ....................................................... 512 words × 4 bits (000H to 1FFH) • Peripheral hardware area ............................ 128 words × 4 bits (F80H to FFFH) 14 µPD75212A Fig. 4-1 Program Memory Map Address 7 6 0000H MBE 0002H MBE RBE 0004H MBE RBE 0006H MBE RBE 0008H MBE RBE 000AH MBE RBE 000CH MBE RBE 000EH 0 RBE Internal Reset Start Address (Most Significant 6 Bits) Internal Reset Start Address (Least Significant 8 Bits) MBE RBE INTBT/INT4 Start Address INTBT/INT4 Start Address INT0 Start Address INT0 Start Address (Most Significant 6 Bits) (Least Significant 8 Bits) (Most Significant 6 Bits) (Least Significant 8 Bits) INT1 Start Address INT1 Start Address INTCSIO Start Address INTCSIO Start Address INTT0 Start Address INTT0 Start Address INTTPG Start Address INTTPG Start Address INTKS Start Address INTKS Start Address (Most Significant 6 Bits) (Least Significant 8 Bits) (Most Significant 6 Bits) (Least Significant 8 Bits) (Most Significant 6 Bits) (Least Significant 8 Bits) (Most Significant 6 Bits) (Least Significant 8 Bits) (Most Significant 6 Bits) (Least Significant 8 Bits) CALLF !faddr Instruction Entry Address BRCB !caddr Instruction Branch Address CALL !addr Instruction Subroutine Entry Address BR !addr Instruction Branch Address 0020H GETI Instruction Reference Table 007FH 0080H BR $ addr Instruction Relative Branch Address (-15 to -1 and +2 to +16) 07FFH Branch Destination Address and Subroutine Entry Address to be Set by GETI Instruction 0800H 0FFFH 1000H BRCB !caddr Instruction Branch Address 1FFFH 2000H 2F7FH Remarks BRCB !caddr Instruction Branch Address In all cases other than those listed above, branch to the address with only the lower 8 bits of the PC changed is enabled by BR PCDE and BR PCXA instructions. 15 µPD75212A Fig. 4-2 Data Memory Map General Register Area 000H (32 × 4) 01FH 020H Bank 0 Stack Area 256 × 4 General Static RAM (512 × 4) 0FFH 100H 256 × 4 Bank 1 Display Data Memory, etc. 1BFH 1C0H (64 × 4) 1FFH Not Incorporated F80H Peripheral Hardware Area 128 × 4 FFFH 16 Bank 15 µPD75212A 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 PORTS I/O ports have the following three functions. • CMOS input :8 • CMOS input/output : 20 • P-ch open-drain, high-voltage, high-current output : 4 Total 32 Table 5-1 Port Functions Port Name Function Operation and Feature Remarks Always read or test possible irrespective of the dual-function pin operating mode. Shares the pins with SI, SO, SCK and INT4. Always read or test possible, P10 and P11 are inputs with the noise elimination function. Shares the pins with INT0 to INT 2 and TI0. P23 shares the pin with BUZ. PORT5 Can be set to the input or output mode in 4-bit units. Ports 4 and 5 can input/output data in pairs in 8-bit units. Ports 4 and 5 can directly drive LEDs. PORT3 PORT6 Can be set bit-wise to the input or output mode. Port 6 can incorporate a pull-down resistor as a mask option. PORT0 4-bit input PORT1 PORT2 PORT4 PORTH 4-bit input/output 4-bit output P-ch open-drain high-voltage, high-current output port. Can drive an FIP and LED directly. Can incorporate a pull-down resistor bit-wise as a mask option. Shares the pins with T10/S15 to T13/S12. 17 µPD75212A 5.2 CLOCK GENERATOR The clock generator operations are determined by the processor clock control register (PCC) and the system clock control register (SCC). The clock generator has two types: main system clock and subsystem clock. The instruction execution time can be changed. • 0.95 µs, 1.91 µs, 15.3 µs (Main system clock: at 4.19 MHz operation) • 122 µs (Subsystem clock: at 32.768 kHz operation) Fig. 5-1 Clock Generator Block Diagram XT1 XT2 Subsystem Clock Oscillator fXT Watch Timer Timer/Pulse Generator Main System Clock Oscillator fX Selector X1 X2 • FIP Controller • Basic Interval Timer (BT) • Timer/Event Counter • Serial Interface • Watch Timer • INT0 Noise Eliminator 1/8~1/4096 fXX Frequency Divider 1/2 1/6 SCC Oscillation Stop Frequency Divider Selector SCC3 SCC0 1/4 • CPU • INT0 Noise Eliminator • INT1 Noise Eliminator PCC Internal Bus Φ PCC0 PCC1 4 HALT F/F HALT* STOP* PCC2 S PCC3 R PCC2 and PCC3 Clear STOP F/F Q Q Wait Release Signal from BT S RES Signal (Internal Reset) R * Instruction execution Remarks 18 Standby Release Signal from Interrupt Control Circuit 1. 2. 3. 4. fX = Main system clock frequency fXT = Subsystem clock frequency fXX = System clock frequency Φ = CPU clock 5. 6. 7. PCC: Processor clock control register SCC: System clock control register 1 clock cycle (tCY) of Φ is 1 machine cycle of an instruction. For tCY , see ”AC Characteristics“ in 12. ELECTRICAL SPECIFICATIONS. µPD75212A 5.3 BASIC INTERVAL TIMER The basic interval timer has the following functions: • • • • Interval timer operation to generate reference time Watchdog timer application to detect inadvertent program loop Wait time select and count upon standby mode release Count contents read Fig. 5-2 Basic Interval Timer Configuration From Clock Generator fXX/2 fXX/2 Clear 5 7 fXX/2 Set Basic Interval Timer (8-Bit Frequency Divider) MPX fXX/2 Clear 9 BT 12 BT Interrupt Request Flag IRQBT Vectored Interrupt Request Signal 3 BTM3 SET1* BTM2 BTM1 BTM0 Wait Release Signal During Standby Release BTM 4 8 Internal Bus * Instruction execution 19 µPD75212A 5.4 WATCH TIMER The µPD75212A incorporates one channel of watch timer. The watch timer has the following functions. • Sets the test flag (IRQW) at 0.5-second intervals. The standby mode can be released by IRQW. • 0.5-second interval can be set with the main system clock and subsystem clock. • The fast mode enables to set 128-time (3.91 ms) interval useful to program debugging and inspection. • The fixed frequencies (2.048 kHz) can be output to the P23/BUZ pin for use to generate buzzer sound and trim the system clock oscillator frequency. • Since the frequency divider can be cleared, the watch can be started from zero second. Fig. 5-3 Watch Timer Block Diagram fW (256 Hz : 3.91 ms) 7 2 From Clock Generator fXX 128 (32.768 kHz) Selector fW 14 2 fW Frequency Divider (32.768 kHz) fXT (32.768 kHz) INTW IRQW Set Signal Selector 2Hz 0.5 sec fW 16 (2.048 kHz) Clear Output Buffer P23/BUZ WM PORT2.3 WM7 WM6 WM5 WM4 WM3WM2 WM1 WM0 P23 Output Latch Bit 2 of PMGB Port 2 Input/Output Mode 8 Internal Bus Remarks 20 Values at f XX = 4.194304 MHz and fXT = 32.768 kHz are indicated in parentheses. µPD75212A 5.5 TIMER/EVENT COUNTER The µPD75212A incorporates one channel of timer/event counter. The timer/event counter has the following functions. • Program interval timer operation • Event counter operation • Count state read function Fig. 5-4 Timer/Event Counter Block Diagram Internal Bus 8 SET1 * 8 8 TM0 TMn7 TMn6 TMn5 TMn4 TMn3 TMn2 TMOD0 Modulo Register (8) TMn1 TMn0 8 Match Comparator (8) INTT0 IRQT0 Set Signal 8 Input Buffer P13/TI0 From Clock Generator T0 Count Register (8) MPX CP Clear Timer Operation Start IRQT0 Clear * Instruction execution. 21 µPD75212A 5.6 TIMER/PULSE GENERATOR The µPD75212A incorporates one channel of timer/pulse generator which can be used as a timer or a pulse generator. The timer/pulse generator has the following functions. (a) Functions available in the timer mode • 8-bit interval timer operation (IRQTPG generation) enabling the clock source to be varied at 5 levels • Square wave output to PPO pin (b) Functions available in the PWM pulse generation mode • 14-bit accuracy PWM pulse output to the PPO pin (Used as a digital-to-analog converter and applicable to tuning) 2 15 • Fixed time interval ( = 7.81 ms : at 4.19 MHz operation) interrupt generation fXX If pulse output is not necessary, the PPO pin can be used as a 1-bit output port. Note If the STOP mode is set while the timer/pulse generator is in operation, miss-operation may result. To prevent that from occurring, preset the timer/pulse generator to the stop state using its mode register. Fig. 5-5 Timer/Pulse Generator Block Diagram (Timer Mode) Internal Bus 8 8 MODL Modulo Register L (8) MODH Modulo Register H (8) TPGM3 (Set to "1") INTTPG IRQTPG Set Signal Modulo Latch H (8) 8 Match Comparator (8) Output Buffer Selector T F/F PPO Frequency Divider fX 1/2 TPGM1 CP Prescalar Select Latch (5) Clear 22 Set 8 Count Register (8) Clear TPGM4TPGM5 TPGM7 µPD75212A Fig. 5-6 Timer/Pulse Generator Block Diagram (PWM Pulse Generation Mode) Internal Bus 8 8 MODH Modulo Register H (8) MODL Modulo Register L (6) (2) TPGM3 MODL7-2 (6) MODH (8) Modulo Latch (14) Output Buffer TPGM1 fx PWM Pulse Generator 1/2 Selector PPO Frequency Divider INTTPG TPGM5 (IRQTPG Set Signal) 215 ( = 7.81 ms : at 4.19 MHz operation) fX TPGM7 5.7 SERIAL INTERFACE The µPD75212A serial interface has the following functions. • Clocked 8-bit send/receive operation (simultaneous send/receive) • Clocked 8-bit serial bus operation (data input/output from the SO pin. N-ch open-drain SO output) • Start LSB/MSB switching The above functions facilitate data communication with another microcomputer of µPD7500 series and 78K series via serial bus and coupling with peripheral devices. 23 24 Fig 5-7 Serial Interface Block Diagram Internal Bus 8 8 Selector P03/SI SET1 *2 SIO7 SIO SIOM Shift Register (8) *1 P02/SO 8 SIO0 SIOM7SIOM6SIOM5SIOM4SIOM3SIOM2SIOM1SIOM0 SO Output Latch Serial Clock Counter (3) INTSIO IRQSIO Set Signal Overflow Clear IRQSIO Clear Signal Serial Start P01/SCK R Q Φ S fxx/2 4 fxx/2 10 MPX 1. CMOS output and N-ch open drain output switchable output buffer. 2. Instruction execution µPD75212A * µPD75212A 5.8 FIP CONTROLLER/DRIVER The FIP controller/driver incorporated in the µPD75212A has the following functions: • Generates the segment and digit signals by automatically reading the display data memory executing DMA operation. • Can select up to a total of 26 display devices in the range of 9 to 16 segments and 9 to 16 digits. • Can apply the remaining display output as static output. • Can adjust the brightness at 8 levels using the dimmer function. • Can apply key scan operations. • Generates interrupt at the key scan timing (IRQKS) • Can generate key scan data output from the segment output pin. • Owns the high-voltage output pin (40 V) which can directly drive the FIP. • Segment special pins (S0 to S9) : VOD = 40 V, IOD = 3 mA • Digit output pins (T0 to T15) : VOD = 40 V, IOD = 15 mA • Can incorporate pull-down resistors bit-wise as mask options. Differences between µPD75212A and µPD75238 display output function are shown in Table 5-2. Table 5-2 Differences between µPD75212A and µPD75238 Display Output Function µPD75212A High-voltage output display FIP output total : 26 µPD75238 FIP output total : 34 Segment output : 9 to 16 Segment output : 9 to 24 Digit output Digit output : 9 to 16 : 9 to 16 Display data area 1C0H to 1FFH 1A0H to 1FFH Output dual-function pin S12 to S15 (PORTH) S0 to S23 (PORT10 to PORT15) Key scan register KS0, KS1 KS0 to KS2 25 µPD75212A Fig. 5-8 FIP Controller/Driver Block Diagram Internal Bus 4 Display Mode Register Display Data Memory (64 × 4 Bits) Key Scan Registers (KS0, KS1) 4 Digit Select Register Key Scan Flag (KSF) 4 Dimmer Select Register Port H 12 4 INTKS IRQKS Generation Signal Digit Signal Generator Segment Data Latch (16) 4 4 Selector 10 2 2 4 4 Selector 2 10 4 High-Voltage Output Buffer 10 S0-S9 Note 2 4 T15/S10, T13/S12/PH0T14/S11 T10/S15/PH3 10 T0-T9 VLOAD VPRE The FIP controller/driver can only operate in the high and intermediate-speeds (PCC = 0011B or 0010B) of the main system clock (SCC.0 = 0). It may cause errors with any other clock or in the standby mode. Thus, be sure to stop FIP controller operation (DSPM.3 = 0) and then shift the unit to any other clock mode or the standby mode. 26 µPD75212A 5.9 POWER-ON FLAG (MASK OPTION) The power-on flag (PONF) is automatically set (1) when the power-on reset circuit is activated and the poweron reset signal is generated (See Fig. 8-1 Reset Signal Generator). The PONF is mapped at bit 0 of address FD1H in the data memory space and can be tested by the memory bit manipulation instructions (SKT, SKF, SKTCLR) or cleared (CLR1). Note The PONF cannot be set by SET1 instruction. 27 µPD75212A 6. INTERRUPT FUNCTIONS The µPD75212A has eight types of interrupt sources and can generate multiple interrupts with priority order. It is also equipped with two types of test sources. INT2 is an edge detected testable input. The µPD75212A interrupt control circuit has the following functions: • Hardware-controller vectored interrupt function which can control interrupt acknowledge with the interrupt enable flag (IE×××) and the interrupt master enable flag (IME). • Function of setting any interrupt start address. • Multiple interrupt function which can specify priority order with the interrupt priority select register (IPS). • Interrupt request flag (IRQ×××) test function. (Interrupt generation can be checked by software.) • Standby mode release function. (Interrupt to be released by interrupt enable flag can be selected.) 28 Fig. 6-1 Interrupt Control Circuit Block Diagram Internal Bus 4 2 2 IM1 IM0 INT BT Both Edges Detection Circuit INT4 /P00 INT0 /P10 * INT1 /P11 * Edge Detection Circuit Edge Detection Circuit IRQ4 IRQ0 IRQ1 INTT0 IRQT0 Priority Control Circuit Vector Table Address Generator Circuit IRQTPG INTKS IRQKS INTW IRQW Noise eliminator VRQn Standby Release Signal IRQ2 29 µPD75212A * IST Decoder IRQSIO Rising Edge Detection Circuit IPS XXX ) IRQBT INTSIO INTTPG INT2 /P12 (IME) Interrupt Enable Flag (IE 2 µPD75212A 7. STANDBY FUNCTIONS Two standby modes (STOP mode and HALT mode) are available for the µPD75212A to decrease power consumption in the program standby mode. Table 7-1 Operation Status in Standby Mode STOP Mode HALT Mode STOP instruction HALT instruction System clock when set Setting enabled only with main system clock. Setting enabled with either main system clock or subsystem clock. Clock oscillator Oscillation stops only with main system clock. Stops only with CPU clock Φ (Oscillation continued). Basic interval timer Operation stopped. Operation (IRQBT set at reference time intervals). Serial interface Operation enabled only when external SCK input is selected for serial clock. Operation enabled when serial clock other than Φ is specified. Timer/event counter Operation enabled only when TI0 pin input is specified for count clock. Operation enabled. Timer/pulse generator Operation stopped. Operation enabled. Watch timer Operation enabled only fXT is selected for Operation enabled. count clock. FIP controller/driver Operation disabled (display off mode set before disabling). CPU Operation stopped. Operating State Set instruction Release signal 30 Interrupt request signal (except INT0, INT1, INT2) enabled by interrupt enable flag or RESET input. µPD75212A 8. RESET FUNCTIONS The reset signal (RES) generator has a configuration shown in Fig. 8-1. Fig. 8-1 Reset Signal Generator RESET Internal Reset Signal (RES) Power-On Reset Generator SWB SWA Power-On Flag (PONF) Bit Manipulation Instruction Execution Internal Bus Mask Option The power-on reset generator is a circuit to generate a one-shot pulse upon detection of the start-up of the power voltage. This pulse is used in the following three ways according to SWA, SWB mask option specification shown in Fig. 8-1. (Refer to 10. MASK OPTION SELECTION.) 31 µPD75212A Fig. 8-2 Reset Operation by Power-On Reset ★ Supply Voltage * Wait (31.3ms:4.19MHz) 0V Internal Reset Signal (RES) HALT Mode Operating Mode Internal Reset Operation * Wait time does not include a time from RES signal generation to oscillation start. Fig. 8-3 Reset Operation by RESET Input ★ Wait (31.3ms:4.19MHz) RESET Input Operating Mode or Standby Mode HALT Mode Internal Reset Operation Each hardware state after reset operation is shown in Table 8-1. 32 Operating Mode µPD75212A Table 8-1 Hardware Statuses after Reset Hardware Program counter (PC) PSW Carry flag (CY) ★ RESET Input in Standby Mode RESET Input upon Power-on Reset or in Operation Sets the low-order 6 bits of program memory address 0000H to PC13-8 and the contents of address 0001H to PC7-0. Sets the low-order 6 bits of program memory address 0000H to PC13-8 and the contents of address 0001H to PC7-0. Hold Undefined Skip flag (SK0 to SK2) 0 0 Interrupt status flag (IST0, IST1) 0 0 Sets bit 6 of program memory address 0000H to RBE and bit 7 to MBE. Sets bit 6 of program memory address 0000H to RBE and bit 7 to MBE. Undefined Undefined Hold*1 Undefined General registers (X, A, H, L, D, E, B, C) Hold Undefined Bank select registers (MBS, RBS) 0, 0 0, 0 Undefined Undefined Bank enable flags (MBE, RBE) Stack pointer (SP) Data memory (RAM) Basic interval timer Counter (BT) Mode register (BTM) 0 0 Timer/event counter Counter (T0) 0 0 FFH FFH 0 0 Hold Undefined Modulo register (TMOD0) Mode register (TM0) Timer/pulse generator Modulo register (MODH, MODL) Mode register (TPGM) 0 0 Watch timer Mode register (WM) 0 0 Serial interface Shift register (SIO) Hold Undefined Clock generator Processor clock control register (PCC) 0 0 System clock control register (SCC) 0 0 Interrupt Interrupt request flag (IRQ×××) Reset (0) Reset (0) Interrupt enable flag (IE×××) 0 0 Priority select register (IPS) 0 0 INT0 and INT1 mode registers (IM0, IM1) 0, 0 0, 0 Output buffer Off Off Output latch Clear (0) Clear (0) 0 0 Hold Undefined 0 0 1000B 1000B 0 0 Hold Undefined Off Off Hold 1 or undefined*2 Digital port Mode register (SIOM) Input/output mode register (PMGA, PMGB) Port H Output latch FIP controller/ driver Display mode register (DSPM) Digit select register (DIGS) Dimmer select register (DIMS) Display data memory Output buffer Power on flag (PONF) * Only bit 4 set to 1, other bits set to 0 Only bit 4 set to 1, other bits set to 0 1. Data of data memory addresses 0F8H to 0FDH becomes indeterminate by RESET input. 2. 1 upon power-on reset, indeterminate after RESET input in operation. 33 µPD75212A 9. INSTRUCTION SET (1) Operand identifier and description Enter an operand in the operand column of each instruction using the description method relating to the operand identifier of the instruction (For details, refer to RA75X Assembler Package User’s Manual Language Volume (EEU-730)). If more than one description method is available, select one. Capital alphabetic letters, plus and minus signs are keywords. Describe them as they are. In the case of immediate data, describe appropriate numerical values or labels. Symbols can be described as labels in place of mem, fmem, pmem, bit, etc. (For details, refer to µ PD75216A User’s Manual (IEM-988)). Available labels are limited for fmem and pmem. Identifier * 34 Description Method reg reg 1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp rp1 rp2 rp’ rp’1 XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA’, BC’, DE’, HL’ BC, DE, HL, XA’, BC’, DE’, HL’ rpa rpa1 HL, HL+, HL-, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem bit 8-bit immediate data or label* 2-bit immediate data or label fmem pmem FB0H to FBFH and FF0H to FFFH immediate data or labels FC0H to FFFH immediate data or labels addr caddr faddr 0000H to 2F7FH immediate data or labels 12-bit immediate data or label 11-bit immediate data or label taddr 20H to 7FH immediate data (bit0 = 0) or label PORTn IE××× RBn MBn PORT0 to PORT6 IEBT, IESIO, IET0, IETPG, IE0, IE1, IEKS, IEW, IE4 RB0 to RB3 MB0, MB1, MB15 For 8-bit data processing, only even addresses can be specified. µPD75212A (2) Legend for operation description A : A register; 4-bit accumulator B : B register C D E H : : : : C register D register E register H register L X XA BC : : : : L register X register Register pair (XA); 8-bit accumulator Register pair (BC) DE HL XA’ BC’ : : : : Register pair (DE) Register pair (HL) Expanded register pair (XA’) Expanded register pair (BC’) DE’ HL’ PC SP : : : : Expanded register pair (DE’) Expanded register pair (HL’) Program counter Stack pointer CY PSW MBE RBE : : : : Carry flag; Bit accumulator Program status word Memory bank enable flag Register bank enable flag PORTn IME IPS IE××× : : : : Port n (n Interrupt Interrupt Interrupt RBS MBS PCC • : : : : Register bank select register Memory bank select register Processor clock control register Address and bit delimiter (××) ××H : Contents addressed by ×× : Hexadecimal data = 0 to 6) master enable flag priority select register enable flag 35 µPD75212A (3) Description of symbols in the addressing area column *1 MB = MBE • MBS (MBS = 0, 1, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (00H to 7FH) MB = 15 (80H to FFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) *4 MB = 15, fmem = FB0H to FBFH, FF0H to FFFH *5 MB = 15, pmem = FC0H to FFFH *6 addr = 0000H to 2F7FH *7 addr = (Current PC) – 15 to (Current PC) – 1, (Current PC) + 2 to (Current PC) + 16 *8 caddr = 0000H to 0FFFH 1000H to 1FFFH 2000H to 2F7FH *9 faddr = 0000H to 07FFH *10 taddr = 0020H to 007FH Remarks (4) (PC13, 12 = 00B) or (PC13, 12 = 01B) or (PC13, 12 = 10B) 1. MB indicates accessible memory bank. 2. 3. 4. In *2, MB = 0 irrespective of MBE and MBS. In *4 and *5, MB = 15 irrespective of MBE and MBS. *6 to *10 indicate addressable areas. Data Memory Addressing Program Memory Addressing Description of the machine cycle column S indicates the number of machine cycles required for skip operation by an instruction having skip function. The S value varies as follows: • When not skipped ................................................................................................... S = 0 • When 1-byte or 2-byte instructions are skipped ................................................. S = 1 • When 3-byte instructions are skipped (BR !addr, CALL !addr instruction) ..... S = 2 Note GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle(=tCY) of CPU clock Φ and three time periods are available according to PCC setting. 36 µPD75212A Note 1 Mnemonic Transfer MOV Note 2 XCH Note MOVT Operands No. of Machine Bytes Cycle Operation Addressing Area Skip Condition A, #n4 1 1 A←n4 Stack A reg1, #n4 2 2 reg1←n4 XA, #n8 2 2 XA←n8 Stack A HL, #n8 2 2 HL←n8 Stack B rp2, #n8 2 2 rp2←n8 A, @HL 1 1 A←(HL) *1 A, @HL+ 1 2+S A←(HL), then L←L+1 *1 L=0 A, @HL– 1 2+S A←(HL), then L←L–1 *1 L = FH A, @rpa1 1 1 A←(rpa1) *2 XA, @HL 2 2 XA←(HL) *1 @HL, A 1 1 (HL)←A *1 @HL, XA 2 2 (HL)←XA *1 A, mem 2 2 A←(mem) *3 XA, mem 2 2 XA←(mem) *3 mem, A 2 2 (mem)←A *3 mem, XA 2 2 (mem)←XA *3 A, reg 2 2 A←reg XA, rp' 2 2 XA←rp' reg1, A 2 2 reg1←A rp'1, XA 2 2 rp'1←XA A, @HL 1 1 A↔(HL) *1 A, @HL+ 1 2+S A↔(HL), then L←L+1 *1 L=0 A, @HL– 1 2+S A↔(HL), then L←L–1 *1 L = FH A, @rpa1 1 1 A↔(rpa1) *2 XA, @HL 2 2 XA↔(HL) *1 A, mem 2 2 A↔(mem) *3 XA, mem 2 2 XA↔(mem) *3 A, reg1 1 1 A↔reg1 XA, rp' 2 2 XA↔rp' XA, @PCDE 1 3 XA←(PC13–8+DE)ROM XA, @PCXA 1 3 XA←(PC13–8+XA)ROM 1. Instruction Group 2. Table reference 37 µPD75212A Note Mnemonic Bit transfer MOV1 ADDS ADDC Operation SUBS SUBC AND OR XOR Note 38 Operand No. of Machine Bytes Cycle Operation Addressing Area Skip Condition CY, fmem.bit 2 2 CY←(fmem.bit) *4 CY, pmem.@L 2 2 CY←(pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY←(H+mem3–0.bit) *1 fmem.bit, CY 2 2 (fmem.bit)←CY *4 pmem.@L, CY 2 2 (pmem 7–2+L3–2.bit(L 1–0))←CY *5 @H+mem.bit, CY 2 2 (H+mem3–0.bit)←CY *1 A, #n4 1 1+S A←A+n4 carry XA, #n8 2 2+S XA←XA+n8 carry A, @HL 1 1+S A←A+(HL) XA, rp' 2 2+S XA←XA+rp' carry rp'1, XA 2 2+S rp'1←rp'1+XA carry A, @HL 1 1 A, CY←A+(HL)+CY XA, rp' 2 2 XA, CY←XA+rp'+CY rp'1, XA 2 2 rp'1, CY←rp'1+XA+CY A, @HL 1 1+S A←A–(HL) XA, rp' 2 2+S XA←XA–rp' borrow rp'1, XA 2 2+S rp'1←rp'1–XA borrow A, @HL 1 1 A, CY←A–(HL)–CY XA, rp' 2 2 XA, CY←XA–rp'–CY rp'1, XA 2 2 rp'1, CY←rp'1–XA–CY A, #n4 2 2 A←A n4 A, @HL 1 1 A←A (HL) XA, rp' 2 2 XA←XA rp' rp'1, XA 2 2 rp'1←rp'1 XA A, #n4 2 2 A←A n4 A, @HL 1 1 A←A (HL) XA, rp' 2 2 XA←XA rp'1, XA 2 2 rp'1←rp'1 A, #n4 2 2 A←A n4 A, @HL 1 1 A←A (HL) XA, rp' 2 2 XA←XA rp'1, XA 2 2 rp'1←rp'1 Instruction Group *1 *1 *1 *1 *1 *1 rp' XA *1 rp' XA carry borrow µPD75212A Increment/decrement Note 2 Note 1 Mnemonic Operation Addressing Area Skip Condition A 1 1 CY←A0, A 3←CY, An–1←An NOT A 2 2 A←A INCS reg 1 1+S reg←reg+1 reg = 0 rp1 1 1+S rp1←rp1+1 rp1 = 00H @HL 2 2+S (HL)←(HL)+1 *1 (HL) = 0 mem 2 2+S (mem)←(mem)+1 *3 (mem) = 0 reg 1 1+S reg←reg–1 reg = FH rp' 2 2+S rp'←rp'–1 rp = FFH reg, #n4 2 2+S Skip if reg = n4 reg = n4 @HL, #n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 1 1+S Skip if A = (HL) *1 A = (HL) XA, @HL 2 2+S Skip if XA = (HL) *1 XA = (HL) A, reg 2 2+S Skip if A = reg A = reg XA, rp' 2 2+S Skip if XA = rp' XA = rp' SET1 CY 1 1 CY←1 CLR1 CY 1 1 CY←0 SKT CY 1 1+S NOT1 CY 1 1 DECS Compare Carry flag manipulation No. of Machine Bytes Cycle RORC SKE Note Operands Skip if CY = 1 CY = 1 CY←CY 1. Instruction Group 2. Accumulator manipulation 39 µPD75212A Note Mnemonic SET1 CLR1 Memory bit manipulation SKT SKF SKTCLR AND1 OR1 XOR1 BR 40 No. of Machine Bytes Cycle Operation Addressing Area Skip Condition mem.bit 2 2 (mem.bit)←1 *3 fmem.bit 2 2 (fmem.bit)←1 *4 pmem.@L 2 2 (pmem7–2+L3–2.bit(L1–0))←1 *5 @H + mem.bit 2 2 (H+mem3–0.bit)←1 *1 mem.bit 2 2 (mem.bit)←0 *3 fmem.bit 2 2 (fmem.bit)←0 *4 pmem.@L 2 2 (pmem7–2+L3–2.bit(L1–0))←0 *5 @H+mem.bit 2 2 (H+mem3–0.bit)←0 *1 mem.bit 2 2+S Skip if (mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0)) = 1 *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit) = 1 *1 (@H+mem.bit) = 1 mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0)) = 0 *5 (pmem.@L) = 0 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit) = 0 *1 (@H+mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0))=1 and clear *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit)=1 and clear *1 (@H+mem.bit)=1 CY, fmem.bit 2 2 CY←CY (fmem.bit) *4 CY, pmem.@L 2 2 CY←CY (pmem7–2+L3–2.bit(L 1–0)) *5 CY, @H+mem.bit 2 2 CY←CY (H+mem3–0.bit) *1 CY, fmem.bit 2 2 CY←CY (fmem.bit) *4 CY, pmem.@L 2 2 CY←CY (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY←CY (H+mem3–0.bit) *1 CY, fmem.bit 2 2 CY←CY (fmem.bit) *4 CY, pmem.@L 2 2 CY←CY (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY←CY (H+mem3–0.bit) *1 addr — — PC13–0←addr *6 (Optimum instruction is selected from among BR !addr, BRCB !caddr and BR $addr by an assembler.) Branch Note Operands !addr 3 3 PC13–0←addr *6 $addr 1 2 PC13–0←addr *7 BRCB !caddr 2 2 PC13–0←PC13,12+caddr11–0 *8 BR PCDE 2 3 PC13–0←PC13–8+DE PCXA 2 3 PC13–0←PC13–8+XA Instruction Group µPD75212A Note Mnemonic Operands !addr 3 3 (SP–4) (SP–1) (SP–2)←PC11–0 (SP–3)← MBE, RBE, PC13, 12 PC13–0←addr, SP←SP–4 *6 CALLF !faddr 2 2 (SP–4) (SP–1) (SP–2)←PC11–0 (SP–3)← MBE, RBE, PC13, 12 PC13–0←000, faddr, SP←SP–4 *9 1 3 MBE, RBE, PC13, 12←(SP+1) Subroutine stack control Unconditional 1 3+S RETI 1 3 ×, ×, PC13, 12←(SP+1) PC11–0←(SP) (SP+3) (SP+2) PSW←(SP+4) (SP+5), SP←SP+6 rp 1 1 (SP–1) (SP–2)←rp, SP←SP–2 BS 2 2 (SP–1)←MBS, (SP–2)←RBS, SP←SP–2 rp 1 1 rp←(SP+1) (SP), SP←SP+2 BS 2 2 MBS←(SP+1), RBS←(SP), SP←SP+2 2 2 IME (IPS.3)←1 2 2 IE×××←1 2 2 IME (IPS.3)←0 IE××× 2 2 IE×××←0 A, PORTn 2 2 A←PORTn XA, PORTn 2 2 XA←PORTn+1, PORTn PORTn, A 2 2 PORTn←A PORTn, XA 2 2 PORTn+1, PORTn←XA HALT 2 2 Set HALT Mode (PCC.2←1) STOP 2 2 Set STOP Mode (PCC.3←1) NOP 1 1 No Operation RBn 2 2 RBS←n (n = 0 to 3) MBn 2 2 MBS←n (n = 0, 1, 15) EI Interrupt control MBE, RBE, PC13, 12←(SP+1) PC11–0←(SP) (SP+3) (SP+2) SP←SP+4 then skip unconditionally RETS POP Input/output Skip Condition PC11–0←(SP) (SP+3) (SP+2) SP←SP+4 PUSH Special CPU control Addressing Area Operation CALL RET * No. of Machine Bytes Cycle IE××× DI IN * OUT * SEL (n = 0 to 6) (n = 4) (n = 2 to 6) (n = 4) *10 MBE = 0 or MBE = 1 and MBS = 15 must be set for execution of IN/OUT instruction. Note Instruction Group 41 µPD75212A Note Mnemonic taddr Special GETI * Operands * 1 3 Operation • TBR instruction PC13–0←(taddr)4–0+(taddr+1) ---------------------------------------------------• TCALL instruction (SP–4)(SP–1)(SP–2)←PC11–0 (SP–3)← MBE, RBE, PC13, 12 PC13–0←(taddr)4–0+(taddr+1) SP←SP–4 ---------------------------------------------------• (taddr) (taddr+1) instruction executed in the case of instruction except TBR and TCALL instructions Addressing Area Skip Condition *10 ------------------------ -----------------------Depends on instructions referred to. TBR and TCALL instructions are assembled pseudo-instructions to define the GETI instruction table. Note 42 No. of Machine Bytes Cycle Instruction Group µPD75212A 10. MASK OPTION SELECTION The µPD75212A has the following mask options enabling or disabling on-chip components. (1) Pin Pin Mask Option Pull-down resistor incorporation enabled bit-wise P60 to P63 T0/T9 T10/S15/PH3 to T13/S12/PH0 T14/S11, T15/S10 S0 to S9 Deletion of subsystem clock oscillator feedback resistor possible XT1, XT2 Note 1. In a system not using subsystem clocks, power consumption in the STOP mode can be decreased by removing the feedback resistor from the oscillator. 2. The feedback resistor must be incorporated when using subsystem clock. (2) Power-on reset generator, power-on flag (PONF) One of the following three can be selected. Switch Selection (See Fig. 8-1) Power-On Reset Generator Power-On Flag (PONF) Internal Reset Signal (RES) SWA SWB ON ON Incorporated Incorporated Generate automatically ON OFF Incorporated Incorporated Not generate automatically OFF OFF Not incorporated Not incorporated ––––– 43 µPD75212A 11. APPLICATION BLOCK DIAGRAM 11.1 VCR TIMER TUNER Main Power Supply + Super Capacitor Power Failure Detection Electronic Tuner Tape Count Pulse Tape Up/Down LPF VDD INT4 PPO VSS T0–T9 10 µPD75212A INT1 S0–S15 16 Fluorescent Display Panel (FIP) 16 Segments × 10 Digits Timer Tuner Remote Controlled Reception Tape Counter Key Matrix (16 × 4) PORT6 SCK System Controller SO Microcomputer SI SCK SO µ PD75104/75106 EEPROM™ INT0 µ PD6252 BUZ µ PC2800A X1 44 Remote Controlled Signal X2 XT1 XT2 BZ Piezoelectric Buzzer µPD75212A 11.2 CD PLAYER T0–S13 14 SCK SI/SO SIO Servo Control IC Fluorescent Display Panel (FIP) 12 Segments × 14 Digits S0–S11 12 Loading Circuit µPD75212A Key Matrix (12 × 4) PORT6 BUZ BZ Remote Controlled Signal INT0 µ PC2800A X1 X2 11.3 ECR Main Power Supply Power Failure Detection + VDD VSS INT4 T0–T15 16 S0–S9 10 Fluorescent Display Panel (FIP) 10 Segments × 16 Digits RAM µ PD75212A Key Matrix (10 × 4) Printer PPO BZ X1 X2 XT1 XT2 45 µPD75212A 12. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C) PARAMETER SYMBOL Power supply voltage Input voltage TEST CONDITIONS RATING UNIT VDD –0.3 to +7.0 V VLOAD VDD –40 to VDD +0.3 V VPRE VDD –12 to VDD +0.3 V VI –0.3 to VDD +0.3 V –0.3 to VDD +0.3 V VDD –40 to VDD +0.3 V VO Pins except display output pins VOD Display output pins Output voltage Output current high Output current low IOL PT Total loss*1 ★ IOH 1 pin except display output pins –15 mA S0 to S9 1 pin –15 mA T0 to T15 1 pin –30 mA Total of pins except display output pins –20 mA Total of display output pins –120 mA 1 pin 17 mA Total of pins 60 mA Plastic QFP 450 mW Plastic shrink DIP 600 mW Operating temperature Topt –40 to +85 °C Storage temperature Tstg –65 to +150 °C Note Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore, the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. OPERATING VOLTAGE (Ta = –40 to +85 °C) MIN. MAX. UNIT CPU *2 *3 6.0 V Display controller 4.5 6.0 V Time/pulse generator 4.5 6.0 V Other hardware *2 2.7 6.0 V PARAMETER TEST CONDITIONS CAPACITANCE ( Ta = 25 °C, VDD = 0 V ) PARAMETER Input capacitance SYMBOL CIN Except display output Output capacitance COUT Display output Input /output capacitance 46 TEST CONDITIONS CIO f = 1 MHz Unmeasured pin returned to 0 V MIN. TYP. MAX. UNIT 15 pF 15 pF 35 pF 15 pF µPD75212A * 1. Calculation of total loss Design so that the sum of the following three power consumption values for the µPD75212ACW/GF will be less than the total loss PT (It is recommended to use the system with 80 % or less of the rating). : Given as VDD (MAX.) × IDD1 (MAX.) : There are normal output pin loss and display output pin loss. It is necessary to add a loss derived from the flow of maximum current to each output pin. ➂ Pull-down register loss : Power loss due to a pull-down resistor incorporated in the display output pin ➀ CPU loss ➁ Output pin loss by mask option. Example Suppose 4-LED output with 9SEG × 11DIGIT, VDD = 5 V + 10 % and 4.19 MHz oscillation and let a current of 3 mA, 15 mA and up to 10 mA flow to the segment pin, timing pin and LED output pin, respectively. Further, let the voltage of fluorescent display tube (VLOAD voltage) be –30 V and normal voltage be small. ➀ CPU loss : 5.5 V × 9.0 mA = 49.5 mW ➁ Pin loss : Segment pin ..... 2 V × 3 mA × 9 = 54 mW Timing pin ......... 2 V × 15 mA = 30 mW 10 × 2 V × 10 mA × 4 = 53 mW 15 (30 + 5.5 V)2 × 10 = 504.1 mW Pull-down resistor loss ........ 25 kΩ LED output ........ ➂ PT = ➀ + ➁ + ➂ = 690.6 mW In this example, since the allowable total loss is 600 mW for the shrink DIP package, it is necessary to decrease power consumption by decreasing the number of on-chip pull-down resistors. In this example, power consumption can be adjusted to 577.8 mW by incorporating pull-down resistors in only 11 digit outputs and 7 segment outputs and externally mounting pull-down resistors to the 2 remaining segment outputs. 2. Except the system clock oscillator, display controller and timer/pulse generator. 3. The operating voltage range varies depending on the cycle time. Refer to the section describing AC characteristics. 47 µPD75212A MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V ) RESONATOR RECOMMENDED CIRCUIT X1 Ceramic resonator*1 X2 C1 C2 X1 TEST CONDITIONS Oscillator frequency (fXX) *2 VDD = Oscillation voltage range Oscillation stabilization time *3 After VDD reaches the minimum value in the oscillation voltage range Oscillator frequency (fXX) *2 X2 Crystal resonator*1 MIN. C2 X1 X2 External clock µPD74HCU04 TYP. 2.0 2.0 VDD = 4.5 to 6.0 V C1 * PARAMETER Oscillation stabilization time *3 4.19 MAX. UNIT 5.0 *4 MHz 4 ms 5.0 *4 MHz 10 ms 30 ms X1 input frequency (fX) *2 2.0 5.0 *4 MHz X1 input high and low level widths (tXH, tXL) 100 250 ns 1. Refer to RECOMMENDED OSCILLATOR CONSTANTS. 2. Oscillator characteristics only. Refer to the description of AC characteristics for details of instruction execution time. 3. Time required for oscillation to become stabilized after VDD reaches the minimum value in the oscillation voltage range or STOP mode release. 4. When oscillator frequency is “4.19 < fXX < – 5.0 MHz”, do not select “PCC = 0011” as instruction execution time. If “PCC = 0011” is selected, 1 machine cycle becomes less than 0.95 µs, with the result that the specified MIN. value of 0.95 µs cannot be observed. ★ Note When the main system clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. • The wiring should be kept as short as possible. • No other signal lines should be crossed. Keep away from lines carrying a high fluctuating current. • The oscillator capacitor grounding point should always be at the same potential as VSS. Do not connect to a ground pattern carrying a high current. • A signal should not be taken from the oscillator. 48 µPD75212A SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) RESONATOR RECOMMENDED CIRCUIT XT1 R C3 C4 XT1 External clock * TEST CONDITIONS Oscillator frequency (fXT) *2 XT2 Crystal resonator*1 PARAMETER XT2 MIN. TYP. MAX. UNIT 32 32.768 35 kHz 1.0 2 s 10 s VDD = 4.5 to 6.0 V Oscillation stabilization time *3 XT1 input frequency (fXT) 32 100 kHz XT1 input high and low level widths (tXTH, tXTL) 10 32 µs Leave Open 1. Recommended resonators are shown in following page. 2. Oscillator characteristics only. Refer to the description of AC characteristics for instruction execution time. 3. Oscillation stabilization time is a time required for oscillation to become stabilized after VDD reaches the minimum value in the oscillation voltage range. Note When the subsystem clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. • The wiring should be kept as short as possible. • No other signal lines should be crossed. Keep away from lines carrying a high fluctuating current. • The oscillator capacitor grounding point should always be at the same potential as VSS. Do not connect to a ground pattern carrying a high current. • A signal should not be taken from the oscillator. The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to misoperation due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. 49 ★ µPD75212A RECOMMENDED OSCILLATOR CONSTANTS MAIN SYSTEM CLOCK : CERAMIC OSCILLATOR (Ta = –40 to +85 °C) MANUFACTURER EXTERNAL CAPACITANCE (pF) PRODUCT NAME C1 C2 30 30 OSCILLATION VOLTAGE RANGE (V) MIN. MAX. 4.0 6.0 REMARKS CSA 2.00MG CSA 4.19MG CSA 4.91MG Murata Mfg. Co., Ltd. CAT 2.00MG CST 4.19MG On-chip C type Not required Not required CST 4.91MG 47 47 33 33 30 30 KBR–2.0MS KBR–4.0MS Kyocera Corp. KBR–4.19MS 4.0 6.0 4.0 6.0 KBR–4.19MS FCR 3.58M2 FCR 4.00M2 TDK FCR 4.19M2 FCR 4.19MC Not required Not required On-chip C type MAIN SYSTEM CLOCK : CRYSTAL RESONATOR (Ta = –40 to +85 °C) MANUFACTURER FREQUENCY (MHz) Kinseki Note LOAD HOLDER CAPACITANCE CL (pF) 2.00 HC–18/U 4.19 HC–49/U 4.91 HC-43/U 16 EXTERNAL CAPACITANCE (pF) OSCILLATION VOLTAGE RANGE (V) C1 C2 MIN. MAX. 20 20 4.0 6.0 REMARKS Carry out fine adjustment of crystal oscillator frequency on the external capacitance C1. SUBSYSTEM CLOCK : 32.768 kHz CRYSTAL RESONATOR (Ta = –10 to +60 °C) MANUFACTURER Kinseki Citizen Watch Co. Note 50 LOAD MODEL CAPACITANCE NAME CL (pF) EXTERNAL CAPACITANCE (pF) OSCILLATION VOLTAGE RANGE (V) C3 (pF) C4 (pF) R (kΩ) P–3 12 22 22 330 CFS–308 14 22 33 330 MIN. (V) MAX. (V) 2.7 6.0 Carry out fine adjustment of crystal oscillator frequency on the external capacitance C3. REMARKS µPD75212A DC CHARACTERISTICS (Ta = –40 to 85 °C, VDD = 2.7 to 6.0 V) PARAMETER Input voltage high SYMBOL TEST CONDITIONS MIN. MAX. UNIT VIH1 Except below 0.7 V DD VDD V VIH2 Ports 0, 1, RESET 0.75 VDD VDD V VIH3 X1, X2, XT1 VDD–0.4 VDD V 0.65 VDD Port 6 VDD V VIH4 0.7 V DD VDD V VDD = 4.5 to 6.0 V Input Voltage low TYP. VIL1 Except below 0 0.3 V DD V VIL2 Ports 0, 1, 6, RESET 0 0.2 V DD V VIL3 X1, X2, XT1 0 0.4 V VOH All output pins V DD = 4.5 to 6.0 V, IOH = –1 mA VDD–1.0 Output voltage high Ports 4, 5 Output voltage low VOL IOH = –100 µA V VDD–0.5 V 0.4 V DD = 4.5 to 6.0 V, IOL = 15 mA V DD = 4.5 to 6.0 V, IOL = 1.6 mA All output pins IOL = 400 µA 2.0 V 0.4 V 0.5 V 3 µA 20 µA –3 µA –20 µA Input leakage current high ILIH1 Input leakage current low ILIL1 ILIL2 X1, X2, XT1 Output leakage current high ILOH All output pins VOUT = VDD 3 µA Output leakage current low ILOL1 Except display output VOUT = 0 V –3 µA –10 µA Except X1,X2,XT1 VIN = VDD ILIH2 X1, X2, XT1 Except X1,X2,XT1 VIN = 0 V ILOL2 Display output S0 to S9 Display output current IOD T0 to T15 Built-in pull-down resistor (mask option) RP6 RL IDD1 IDD2 IDD4 IDD5 VPRE = VDD – 9 ±1 V*1 VDD = 4.5 to 6.0 V VPRE = 0 V VOD = VPRE = VDD – 9 ±1 V*1 VDD – 2 V VPRE = 0 V Port 6 VIN = VDD VDD = 4.5 to 6.0 V Display output VOD – VLOAD = 35 V –3 –5.5 mA –1.5 –3.5 mA –15 –22 mA –7 –15 mA 20 80 200 kΩ 1000 kΩ 70 135 kΩ VDD = 5 V ±10 %*3 3.0 9.0 mA VDD = 3 V ±10 %*4 0.55 1.5 mA VDD = 5 V ±10 % 600 1800 µA VDD = 3 V ±10 % 200 600 µA VDD = 3 V ±10 % 32 kHz crystal oscillation*5 HALT mode VDD = 3 V ±10 % 40 120 µA 5 15 µA VDD = 5 V ±10 % 0.5 20 µA VDD = 3 V ±10 % 0.1 10 µA 4.19 MHz crystal oscillation C1 = C2 = 15 pF Supply current*2 IDD3 VOUT = VLOAD = VDD – 35 V XT1 = 0 V STOP mode 20 HALT mode 25 51 µPD75212A * 1. The following external circuit is recommended. µPD75212A +5 V VDD RD9, 1EL RD9, 1EL :Zener Diode (NEC) Zener Voltage = 8.29 to 9.30 V VPRE 68 kΩ VLOAD –30 V VSS 2. Current to the on-chip pull-down resistor and power-on reset circuit (mask option) is not included. 3. When the processor clock control register (PCC) is set to 0011 and is operated in the high-speed mode. 4. When the PCC register is set to 0000 and is operated in the low-speed mode. 5. When the system clock control register (SCC) is set to 1001 and is operated with the subsystem clock with main system clock oscillation stopped. POWER-ON RESET CIRCUIT CHARACTERISTICS (MASK OPTION) (Ta = –40 to +85 °C) PARAMETER SYMBOL Power-on reset operating voltage high VDDH Power-on reset operating voltage low MAX. UNIT 4.5 6.0 V VDDL 0 0.2 V Power supply voltage rise time tr 10 *1 µs Power supply voltage off time toff 1 Power-on reset circuit*2 current consumption * TEST CONDITIONS MIN. VDD = 5 V ±10 % VDD = 2.7 V VDDH VDD VDDL toff 52 s 10 100 µA 2 20 µA IDDPR 1. 2 17/fXX (31.3 ms at fXX = 4.19 MHz) 2. Current with on-chip power-on reset circuit or power-on flag. Remarks TYP. Start the power supply smoothly. tr µPD75212A AC CHARACTERISTICS (Ta = –40 to +85 °C , VDD = 2.7 to 6.0 V) PARAMETER SYMBOL TEST CONDITIONS Operation with main system clock CPU clock cycle time (minimum instruction execution time = 1 machine cycle) *1 tCY TI0 input frequency fTI MIN. VDD = 4.5 to 6.0 V Operation with subsystem clock VDD = 4.5 to 6.0 V TI0 input high and lowlevel widths tTIH, SCK high and low-level widths tKH, 0.95 32 µs 3.8 32 µs 125 µs 0 0.6 MHz 0 165 kHz 122 µs 3 µs Input 0.8 µs Output 0.95 µs Input 3.2 µs Output 3.8 µs Input 0.4 µs tKCY/2–50 ns 1.6 µs tKCY/2–150 ns tTIL tKCY UNIT 0.83 VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V SCK cycle time MAX. 114 TYP. VDD = 4.5 to 6.0 V Output tKL Input Output SI setup time (to SCK↑) tSIK 100 ns SI hold time (from SCK↑) tKSI 400 ns SO output delay time from SCK↓ tKSO Interrupt input high and low-level widths RESET low-level width VDD = 4.5 to 6.0 V ns 1000 ns INT0 *2 µs INT1 2tCY µs INT2, 4 10 µs 10 µs tINTH, tINTL tRSL 300 53 µPD75212A tCY VS VDD (Main System Clock in Operation) 1. CPU clock (Φ) cycle time is determined by the oscillator frequency of the connected resonator, the system clock control register (SCC) and the 40 processor clock control register (PCC). The cycle time tCY characteristics for power supply voltage VDD when the main system clock is in operation is shown below. 6 2. 2tCY or 128/fXX is set by interrupt mode register (IM0) setting. 32 30 5 Operation Guaranteed Range 4 Cycle Time tCY [µs] * 3 2 1 0.5 0 1 2 3 4 5 Power Supply Voltage VDD [V] 54 6 µPD75212A AC Timing Test Points (Except X1 and XT1 Inputs) 0.75 VDD 0.75 VDD Test Points 0.2 VDD 0.2 VDD Clock Timing 1/fX tXL tXH X1 Input VDD – 0.4 V 0.4 V 1/fXT tXTL tXTH XT1 Input VDD – 0.4 V 0.4 V TI0 Timing 1/fTI tTIL tTIH TI0 55 µPD75212A Serial Transfer Timing tKCY tKH tKL SCK tSIK SI tKSI Input Data tKSO SO Output Data Interrupt Input Timing tINTL INT0,1,2,4 RESET Input Timing tRSL RESET 56 tINTH µPD75212A DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40 to +85 °C) PARAMETER SYMBOL Data retention power supply voltage VDDDR Data retention power supply current *1 IDDDR Release signal set time tSREL Oscillation stabilization wait time *2 tWAIT * TEST CONDITIONS MIN. TYP. 2.0 VDDDR = 2.0V 0.1 MAX. UNIT 6.0 V 10 µA µs 0 Release by RESET Release by interrupt request 217/fX ms *3 ms 1. Current to the on-chip pull-down resistor and power-on reset circuit (mask option) is not included. 2. Oscillation stabilization wait time is time to stop CPU operation to prevent unstable operation upon oscillation start. 3. According to the setting of the basic interval timer mode register (BTM) (see below). BTM3 BTM2 BTM1 BTM0 Wait Time (Values at fXX = 4.19 MHz in parentheses) — 0 0 0 220/fXX (approx. 250 ms) — 0 1 1 217/fXX (approx. 31.3 ms) — 1 0 1 215/fXX (approx. 7.82 ms) — 1 1 1 213/fXX (approx. 1.95 ms) Data Retention Timing (STOP Mode Release by RESET) Internal Reset Operation HALT Mode Operating Mode STOP Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution RESET tWAIT 57 µPD75212A Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT Mode Operating Mode STOP Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT 58 µPD75212A 13. CHARACTERISTIC CURVES IDD vs VDD (Ta = 25 °C) 5000 High-Speed Mode (0011) Medium-Speed Mode (0010) Low-Speed Mode (0000) 1000 HALT Mode (0100) Supply Current IDD [µA] 500 Subsystem Clock Operating Mode 100 Subsystem Clock HALT Mode 50 STOP Mode (1000) Power-on reset circuit and power-on flag incorporated 10 5 X1 X2 XT1 XT2 330 kΩ 32.768 kHz 4.19 MHz 15 pF 15 pF 3 4 Supply Voltage V DD [V] 5 22 pF 33 pF 1 0 Remarks 1 2 6 Values of the processor clock control register (PCC) are indicated in parenthesis. 59 µPD75212A IOL vs VOL (Ports 0, 2, 3, 6) (Ta = 25 °C) 20 VDD = 5 V VDD = 6 V VDD = 4 V Output Current Low IOL [mA] 15 VDD = 3 V 10 VDD = 2.7 V 5 0 0 1 2 3 4 5 Output Voltage Low VOL [V] IOH vs (VDD – VOH ) (Ports 0, 2, 3, 6) (Ta = 25 °C) –20 VDD = 5 V –15 Output Current High IOH [mA] VDD = 6 V VDD = 4 V –10 VDD = 3 V –5 VDD = 2.7 V 0 0 1 2 3 VDD– VOH [V] 60 4 5 µPD75212A IOL vs VOL (Ports 4, 5) (Ta = 25 °C) 20 VDD = 5 V 6V 4V VDD = 3 V Output Current Low IOL [mA] 15 VDD = 2.7 V 10 5 0 0 1 2 3 Output Voltage Low VOL [V] 4 5 IOH vs (VDD – VOH) (Ports 4, 5) (Ta = 25 °C) –20 VDD = 6 V Output Current High IOH [mA] –15 VDD = 5 V VDD = 4 V –10 VDD = 3 V –5 VDD = 2.7 V 0 0 1 2 3 4 5 VDD– VOH [V] 61 µPD75212A IOD vs (VDD to VOD) (T0 to T15) (Ta = 25 °C) –40.0 VDD – VPRE = 8 V –30.0 Display Output Current IOD [mA] VDD – VPRE = 10 V VDD – VPRE = 6 V –20.0 VDD – VPRE = 4 V –10.0 0 0 1 2 3 VDD– VOD [V] 4 5 IOD vs (VDD – VOD) (S0 to S9) (Ta = 25 °C) –10.0 Display Output Current IOD [mA] VDD – VPRE = 10 V VDD – VPRE = 8 V VDD – VPRE = 6 V –5.0 VDD – VPRE = 4 V 0 0 1 2 3 VDD– VOD [V] 62 4 5 µPD75212A 14. PACKAGE INFORMATION 64 PIN PLASTIC SHRINK DIP (750 mil) 64 33 1 32 A K H G J I L F D N M NOTE M B C ITEM MILLIMETERS R INCHES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. A 58.68 MAX. 2.311 MAX. B 1.78 MAX. 0.070 MAX. 2) Item "K" to center of leads when formed parallel. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.9 MIN. 0.035 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.08 MAX. 0.200 MAX. K 19.05 (T.P.) 0.750 (T.P.) L 17.0 0.669 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.17 0.007 R 0~15° 0~15° P64C-70-750A,C-1 63 µPD75212A 64 PIN PLASTIC QFP (14×20) A B detail of lead end 33 32 51 52 C D S R Q 64 1 20 19 F G H I M J K M P N L NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. 64 ITEM MILLIMETERS INCHES A 23.6±0.4 0.929±0.016 B 20.0±0.2 0.795 +0.008 –0.009 C 14.0±0.2 0.551+0.009 –0.008 D 17.6±0.4 0.693±0.016 F 1.0 0.039 G 1.0 0.039 H 0.40±0.10 0.016 +0.004 –0.005 0.008 I 0.20 J 1.0 (T.P.) 0.039 (T.P) K 1.8±0.2 0.071 +0.008 –0.009 L 0.8±0.2 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N P Q R S 0.10 0.004 2.7 0.106 0.1±0.1 0.004±0.004 5°±5° 5°±5° 3.0 MAX. 0.119 MAX. P64GF-100-3B8,3BE,3BR-2 µPD75212A 64-pin ceramic QFP for ES (reference) (unit : mm) 14.2 64 52 51 19 20 33 32 18.0 1 0.4 0.15 2.25 1.0 20 12.0 Note Bottom View 1. Care is needed since the metal cap is connected to pin 26 and set to the positive power supply level. 2. Care is needed since the lead of the base is formed obliquely. 3. The lead length is not stipulated since the cutting of the lead ends is not progresscontrolled. 65 µPD75212A 15. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the conditions recommended below. For details of recommended soldering conditions, refer to the information document “Semiconductor Device Mount Manual” (IEI-1207). For soldering methods and conditions other than those recommended below, contact our salesman. Table 15-1 Surface Mounting Type Conditions µPD75212AGF-×××-3BE : 64-pin plastic QFP (14 × 20 mm) Soldering Method * Soldering Conditions Recommended Condition Symbol Wave soldering Solder bath temperature: 260 °C or less, Duration: 10 sec. max. Number of times: Once, Time limit: 7 days* (thereafter 10 hours prebaking required at 125 °C) Preheating temperature : 120 °C max. (package surface temperature) WS60-107-1 Infrared reflow Package peak temperature: 230 °C, Duration: 30 sec. max. (at 210 °C or above), Number of times: Once, Time limit: 7 days*(thereafter 10 hours prebaking required at 125 °C) IR-30-107-1 VPS Package peak temperature: 215 °C, Duration: 40 sec. max. (at 200 °C or above), Number of times: Once, Time limit: 7 days* (thereafter 10 hours prebaking required at 125 °C) VP15-107-1 Pin part heating Pin part temperature: 300 °C or below , Duration: 3 sec. max. (per device side) ––– For the storage period after dry-pack decompression storage conditions are max. 25 °C, 65 % RH. Note Use of more than one soldering method should be avoided (except in the case of pin part heating). Notice A Version of this product with improved recommended soldering condition is available. For details (improvements such as infrared reflow peak temperature extension (235 °C), number of times: twice, relaxation of time limit, etc.), contact NEC sales personnel. Table 15-2 Insertion Type Soldering Conditions µPD75212ACW-××× : 64-pin plastic shrink DIP (750 mil) Soldering Method Wave soldering (lead part only) Solder bath temperature: 260 °C or below , Duration: 10 sec. max. Pin part heating Pin part temperature: 260 °C or below , Duration: 10 sec. max. Note 66 Soldering Conditions Ensure that the application of wave soldering is limited to the lead part and no solder touches the main unit directly. µPD75212A APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for the development of systems using the µPD75212A. IE-75000-R*1 IE-75001-R In-circuit emulator for the 75X series IE-75000-R-EM*2 Emulation board for the IE-75000-R and IE-75001-R EP-75216ACW-R Emulation probe for µPD75216ACW Software Hardware EP-75216AGF-R * EV-9200G-64 Emulation probe for µPD75216AGF provided with the 64-pin conversion socket EV-9200G-64 PG-1500 PROM programmer PA-75P216ACW PROM programmer adapter for µPD75P216ACW/75P218CW in connection with PG-1500 PA-75P218GF PROM programmer adapter for µPD75P218GF in connection with PG-1500 PA-75P218KB PROM programmer adapter for µPD75P218KB in connection with PG-1500. IE control program Host machine PG-1500 controller • PC-9800 series (MS-DOS™ Ver.3.30 to Ver.5.00A*3) RA75X relocatable assembler • IBM PC/AT™ (PC DOS™ Ver.3.1) 1. Maintenance product 2. Not incorporated in the IE-75001-R 3. The task swap function, which is provided with Ver.5.00/5.00A, is not available with this software. Remarks For development tools manufactured by a third party, see the 75X Series Selection Guide (IF-151). 67 µPD75212A APPENDIX B. RELATED DOCUMENTS Device Related Documents Document Name Document No. User’s Manual Instruction Application Table Application Note 75X Series Selection Guide Development Tools Related Documents Document Name Document No. Hardware IE-75000-R/IE-75001-R User’s Manual IE-75000-R-EM User’s Manual EP-75216ACW-R User’s Manual EP-75216AGF-R User’s Manual Software PG-1500 User’s Manual RA75X Assembler Package User’s Manual Operation Volume Language Volume PG-1500 Controller User’s Manual Other Documents Document Name Document No. Package Manual Surface Mount Technology Manual Quality Grade on NEC Semiconductor Devices NEC Semiconductor Device Reliability & Quality Control Electrostatic Discharge (ESD) Test Semiconductor Devices Quality Guarantee Guide Microcomputer Related Products Guide Other Manufactures Volume Note 68 The contents of the above related documents are subjected to change without notice. The latest documents should be used for design, etc. µPD75212A 69 µPD75212A [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special : Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92.6 EEPROM is a trademark of NEC Corporation. FIP is a trademark of NEC Corporation. MS-DOS is a trademark of Microsoft Corporation. PC DOS, PC/AT are trademarks of IBM Corporation.