DATA SHEET MOS INTEGRATED CIRCUIT µPD753012, 753016, 753017 4-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µ PD753017 is one of the 75XL series 4-bit single-chip microcontroller chips and has a data processing capability comparable to that of an 8-bit microcontroller. It has an on-chip LCD controller/driver with a larger ROM capacity and extended CPU functions compared with the conventional µ PD75316B, and can provide high-speed operation. It can be supplied in a small plastic TQFP package (12 × 12 mm) and is suitable for small sets using LCD panels. For details of functions refer to the following User’s Manual. µ PD753017 User’s Manual : U11282E FEATURES • Low voltage operation: VDD = 2.2 to 5.5 V · Can be driven by two 1.5 V batteries • Capable of high-speed operation and variable instruction execution time for power saving · 0.95, 1.91, 3.81, 15.3 µ s (at 4.19 MHz operation) • On-chip memory · 0.67, 1.33, 2.67, 10.7 µs (at 6.0 MHz operation) · Program memory (ROM): 12288 × 8 bits (µ PD753012) · 122 µ s (at 32.768 kHz operation) 16384 × 8 bits ( µ PD753016) • Internal programmable LCD controller/driver 24576 × 8 bits ( µ PD753017) • Small plastic TQFP (12 × 12 mm) · Data memory (RAM): · Suitable for small sets such as cameras • One-time PROM: µ PD75P3018 1024 × 4 bits APPLICATION Remote controllers, camera-contained VCRs, cameras, gas meters, etc. ORDERING INFORMATION Part number Package µ PD753012GC-XXX-3B9 80-pin plastic QFP (14 × 14 mm) µ PD753012GK-XXX-BE9 80-pin plastic TQFP (fine pitch) (12 × 12 mm) µ PD753016GC-XXX-3B9 80-pin plastic QFP (14 × 14 mm) µ PD753016GK-XXX-BE9 80-pin plastic TQFP (fine pitch) (12 × 12 mm) µ PD753017GC-XXX-3B9 80-pin plastic QFP (14 × 14 mm) µ PD753017GK-XXX-BE9 80-pin plastic TQFP (fine pitch) (12 × 12 mm) Remark XXX indicates a ROM code suffix. In this document, unless otherwise specified, the description is made based on µPD753017 as typical product. The information in this document is subject to change without notice. Document No. U10140EJ2V0DS00 (2nd edition) Date Published December 1997 N Printed in Japan The mark shows major revised points. © 1995 µPD753012, 753016, 753017 FUNCTIONAL OUTLINE Parameter Function • 0.95, 1.91, 3.81, 15.3 µs (main system clock: at 4.19 MHz operation) • 0.67, 1.33, 2.67, 10.7 µs (main system clock: at 6.0 MHz operation) • 122 µs (subsystem clock: at 32.768 kHz operation) Instruction execution time On-chip memory ROM 12288 × 8 bits (µPD753012) 16384 × 8 bits (µPD753016) 24576 × 8 bits (µPD753017) RAM 1024 × 4 bits General-purpose register • 4-bit operation: 8 × 4 banks • 8-bit operation: 4 × 4 banks Input/ output port CMOS input 8 CMOS input/output 16 CMOS output 8 Also used for segment pins N-ch open-drain input/output 8 Withstands 13 V, on-chip pull-up resistors can be specified by using mask option Total 40 LCD controller/driver On-chip pull-up resistors can be specified by using software: 23 • Segment number selection • Display mode selection : 24/28/32 segments (can be changed to CMOS output port in 4 time-unit; max. 8) : Static 1/2 duty (1/2 bias) 1/3 duty (1/2 bias) 1/3 duty (1/3 bias) 1/4 duty (1/3 bias) On-chip split resistor for LCD drive can be specified by using mask option 2 Timer 5 channels • 8-bit timer/event counter: 3 channels (can be used for 16-bit timer/event counter, carrier generator, or timer with gate) • Basic interval timer/watchdog timer: 1 channel • Watch timer: 1 channel Serial interface • 3-wire serial I/O mode ... MSB or LSB can be selected for transferring top bit • 2-wire serial I/O mode • SBI mode Bit sequential buffer 16 bits Clock output (PCL) • Φ, 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation) • Φ, 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation) Buzzer output (BUZ) • 2, 4, 32 kHz (main system clock: at 4.19 MHz operation or subsystem clock: at 32.768 kHz operation) • 2.93, 5.86, 46.9 kHz (main system clock: at 6.0 MHz operation) Vectored interrupts External: 3, Internal: 5 Test input External: 1, Internal: 1 System clock oscillator • Ceramic or crystal oscillator for main system clock oscillation • Crystal oscillator for subsystem clock oscillation Standby function STOP/HALT mode Power supply voltage VDD = 2.2 to 5.5 V Package • 80-pin plastic QFP (14 × 14 mm) • 80-pin plastic TQFP (fine pitch) (12 × 12 mm) µPD753012, 753016, 753017 CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ................................................................................................... 5 2. BLOCK DIAGRAM ............................................................................................................................... 7 3. PIN 3.1 3.2 3.3 3.4 FUNCTION .................................................................................................................................... 8 Port Pins ...................................................................................................................................... 8 Pins Other than Port Pins ........................................................................................................ 10 Pin Input/Output Circuits ......................................................................................................... 12 Recommended Connection for Unused Pins ......................................................................... 14 4. SWITCHING FUNCTION BETWEEN MK I MODE AND MK II MODE ...................................... 15 4.1 Differences between Mk I Mode and Mk II Mode .................................................................... 15 4.2 Setting Method of Stack Bank Select Register (SBS) ........................................................... 16 5. MEMORY CONFIGURATION ............................................................................................................17 6. PERIPHERAL HARDWARE FUNCTIONS ....................................................................................... 21 6.1 Digital Input/Output Ports ........................................................................................................ 21 6.2 Clock Generator ........................................................................................................................22 6.3 Subsystem Clock Oscillator Control Functions .................................................................... 23 6.4 Clock Output Circuit .................................................................................................................24 6.5 Basic Interval Timer/Watchdog Timer ..................................................................................... 25 6.6 Watch Timer ..............................................................................................................................26 6.7 Timer/Event Counter .................................................................................................................27 6.8 Serial Interface ..........................................................................................................................31 6.9 LCD Controller/Driver ............................................................................................................... 33 6.10 Bit Sequential Buffer … 16 Bits ...............................................................................................35 7. INTERRUPT FUNCTION AND TEST FUNCTION ........................................................................... 36 8. STANDBY FUNCTION .......................................................................................................................38 9. RESET FUNCTION ............................................................................................................................ 39 10. MASK OPTION .................................................................................................................................. 42 11. INSTRUCTION SETS AND THEIR OPERATIONS ........................................................................ 43 12. ELECTRICAL SPECIFICATIONS ...................................................................................................... 55 13. PACKAGE DRAWINGS ..................................................................................................................... 68 14. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 70 3 µPD753012, 753016, 753017 APPENDIX A µPD75316B, 753017 AND 75P3018 FUNCTION LIST ................................................ 72 APPENDIX B DEVELOPMENT TOOLS ................................................................................................. 74 APPENDIX C RELATED DOCUMENTS ................................................................................................. 78 4 µPD753012, 753016, 753017 1. PIN CONFIGURATION (TOP VIEW) • 80-pin plastic QFP (14 × 14 mm) µPD753012GC-XXX-3B9, 753016GC-XXX-3B9, µPD753017GC-XXX-3B9 • 80-pin plastic TQFP (fine pitch) (12 × 12 mm) µPD753012GK-XXX-BE9, 753016GK-XXX-BE9, S27/BP3 S28/BP4 7 8 54 53 9 10 11 52 51 50 12 13 14 49 48 47 15 16 17 46 45 44 18 43 19 20 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 COM0 COM1 COM2 S29/BP5 S30/BP6 S31/BP7 57 56 55 P60/KR0 X2 X1 Note IC XT2 XT1 VDD P33 P32 P31/SYNC P30/LCDCL P23/BUZ P22/PCL/PTO2 P21/PTO1 P20/PTO0 P13/TI0 P12/INT2/TI1/TI2 P11/INT1 P10/INT0 P03/SI/SB1 P50 P51 P52 P53 P00/INT4 P01/SCK P02/SO/SB0 S22 S23 S24/BP0 S25/BP1 S26/BP2 4 5 6 VLC2 P40 P41 P42 P43 VSS S16 S17 S18 S19 S20 S21 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 VLC1 S14 S15 1 2 3 COM3 BIAS VLC0 S12 S13 S7 S6 S5 S4 S3 S2 S1 S0 RESET P73/KR7 P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 S11 S10 S9 S8 µPD753017GK-XXX-BE9 Note Connect the IC (Internally Connected) pin directly to VDD. 5 µPD753012, 753016, 753017 Pin Name P00-P03 : Port 0 VLC0-VLC2 : LCD Power Supply 0-2 P10-P13 : Port 1 BIAS : LCD Power Supply Bias Control P20-P23 : Port 2 LCDCL : LCD Clock P30-P33 : Port 3 SYNC : LCD Synchronization P40-P43 : Port 4 TI0-TI2 : Timer Input 0-2 P50-P53 : Port 5 PTO0-PTO2 : Programmable Timer Output 0-2 P60-P63 : Port 6 BUZ : Buzzer Clock P70-P73 : Port 7 PCL : Programmable Clock BP0-BP7 : Bit Port INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4 KR0-KR7 : Key Return INT2 SCK : Serial Clock X1, X2 : Main System Clock Oscillation 1, 2 SI : Serial Input XT1, XT2 : Subsystem Clock Oscillation 1, 2 SO : Serial Output VDD : Positive Power Supply SB0, SB1 : Serial Bus 0, 1 VSS : Ground RESET : Reset Input IC : Internally Connected S0-S31 : Segment Output 0-31 COM0-COM3 : Common Output 0-3 6 : External Test Input 2 INTT1 TI1/TI2/ P12/INT2 TIMER/EVENT COUNTER #1 PTO2/P22/PCL TOUT0 TIMER/EVENT COUNTER #2 INTT2 BASIC INTERVAL /WATCHDOG TIMER PROGRAM Note 1 COUNTER INTBT TI0/P13 PTO0/P20 BUZ/P23 CY ALU SBS BANK TOUT0 INTW SO/SB0/P02 P00-P03 PORT1 4 P10-P13 PORT2 4 P20-P23 PORT3 4 P30-P33 PORT4 4 P40-P43 PORT5 4 P50-P53 PORT6 4 P60-P63 PORT7 4 P70-P73 24 S0-S23 8 S24/BP0S31/BP7 4 COM0-COM3 3 VLC0-VLC2 WATCH TIMER GENERAL REG. SI/SB1/P03 4 SP (8) TIMER/EVENT COUNTER #0 INTT0 PORT0 fLCD CLOCKED SERIAL INTERFACE ROMNote 2 PROGRAM MEMORY DECODE AND CONTROL INTCSI TOUT0 INT0/P10 INT1/P11 LCD CONTROLLER /DRIVER INTERRUPT CONTROL INT4/P00 CPU CLOCK Φ fx/2N KR0/P60- 8 KR7/P73 BIT SEQ. BUFFER (16) CLOCK OUTPUT CONTROL PCL/PTC2/P22 Notes 1. 7 2. CLOCK DIVIDER SYSTEM CLOCK GENERATOR SUB MAIN XT1 XT2 X1 X2 fLCD STAND BY CONTROL SYNC/P31 IC VDD VSS RESET µPD753012 and 753016 have a 14-bit configuration, and µPD753017 has a 15-bit configuration. Capacity of the ROM depends on the product. BIAS LCDCL/P30 µPD753012, 753016, 753017 RAM DATA MEMORY 1024 X 4 BITS SCK/P01 INT2/P12 2. BLOCK DIAGRAM PTO1/P21 µPD753012, 753016, 753017 3. PIN FUNCTION 3.1 Port Pins (1/2) Input/Output Dual Function Pin P00 Input INT4 P01 Input/Output SCK P02 Input/Output SO/SB0 F -B P03 Input/Output SI/SB1 M -C P10 Input INT0 Pin Name P11 INT1 P12 TI1/TI2/INT2 P13 TI0 P20 Input/Output PTO0 P21 PTO1 P22 PCL/PTO2 P23 BUZ P30 Input/Output LCDCL P31 SYNC P32 – P33 – Function 4-bit input port (PORT0). For P01 to P03, on-chip pull-up resistors can be specified in software in 3-bit units. 8-bit I/O At Reset I/O Circuit TYPE Note 1 × Input B F -A 4-bit input port (PORT1). On-chip pull-up resistors can be specified in software in 4-bit units. Noise eliminator can be selected (Only P10/INT0) × input B -C 4-bit input/output port (PORT2). On-chip pull-up resistors can be specified in software in 4-bit units. × Input E-B Programmable 4-bit input/output port (PORT3). This port can be specified input/output in bit units. On-chip pull-up resistor can be specified in software in 4-bit units. × Input E-B P40-P43 Note 2 Input/Output – N-ch open-drain 4-bit input/output port (PORT4). A pull-up resistor can be contained bit-wise (mask option). Withstand voltage is 13 V in open-drain mode. High level (when pull-up resistors are contained) or high impedance M-D P50-P53 Note 2 Input/Output – N-ch open-drain 4-bit input/output port (PORT5). A pull-up resistor can be contained bit-wise (mask option). Withstand voltage is 13 V in open-drain mode. High level (when pull-up resistors are provided) or high impedance M-D Notes 1. 2. Circled characters indicate the Schmitt-trigger input. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port), low level input leakage current increases when input or bit manipulation instruction is executed. 8 µPD753012, 753016, 753017 3.1 Port Pins (2/2) Pin Name P60 Input/Output Dual Function Pin Input/Output KR0 P61 KR1 P62 KR2 P63 KR3 P70 Input/Output KR4 P71 KR5 P72 KR6 P73 KR7 BP0 Output S24 BP1 S25 BP2 S26 BP3 S27 BP4 Output 8-bit I/O At Reset I/O Circuit TYPE Note 1 Programmable 4-bit input/output port (PORT6). This port can be specified for input/output bit-wise. On-chip pull-up resistors can be specified in software in 4-bit units. Input F -A 4-bit input/output port (PORT7). On-chip pull-up resistors can be specified in software in 4-bit units. Input F -A Note 2 H-A Function × 1-bit output port (BIT PORT) Also used for segment output pins. S28 BP5 S29 BP6 S30 BP7 S31 Notes 1. Circled characters indicate the Schmitt-trigger input. 2. For BP0 to BP7, VLC1 is selected as an input source. The output levels differ depending on BP0 to BP7 and the external circuit of the VLC1. Example BP0 to BP7 are connected each other internally in the µPD753017 as shown below. Therefore, the output levels of BP0 to BP7 are determined by the levels of R1, R2, and R 3 VDD µ PD753017 R2 BP0 VLC1 ON BP1 R1 ON R3 9 µPD753012, 753016, 753017 3.2 Pins Other than Port Pins (1/2) Pin Name TI0 Input/Output Dual Function Pin Input P13 TI1 P12/INT2 At Reset I/O Circuit TYPE Note 1 Inputs external event pulses to the timer/event counter. Input B -C Timer/event counter output Input E-B Input F -A Function TI2 PTO0 Output P20 PTO1 P21 PTO2 P22/PCL PCL P22/PTO2 BUZ P23 Any frequency output (for buzzer output or system clock trimming) P01 Serial clock input/output SO/SB0 P02 Serial data output Serial bus data input/output F -B SI/SB1 P03 Serial data input Serial bus data input/output M -C SCK Input/Output Clock output INT4 Input P00 Edge detection vectored interrupt input (both rising edge and falling edge detection) Input B INT0 Input P10 Edge detection vectored interrupt input (detection edge can be selected) Noise eliminator can be selected. (Only P10/INT0) With noise eliminator asynchronous selection possible Input B -C Edge-detection-testable input Asynchronous Input B -C INT1 P11 Asynchronous INT2 Input P12/TI1/TI2 KR0-KR3 Input P60-P63 Falling edge detection testable input Input F -A KR4-KR7 Input P70-P73 Falling edge detection testable input Input F -A S0-S23 Output – Segment signal output Note 2 G-D S24-S31 Output BP0-BP7 Segment signal output Note 2 H-A COM0-COM3 Output – Common signal output Note 2 G-B – – LCD drive power On-chip split resistor is enable (mask option). – – Output – Output for external split resistor disconnect Note 3 – Output P30 Clock output for externally expanded driver Input E-B Output P31 Clock output for externally expanded driver sync Input E-B Input – – Crystal/ceramic connection pin for the main system clock oscillator. When inputting the external clock, input the external clock to pin X1, and the reverse phase of the external clock to pin X2. – – V LC0 -VLC2 BIAS LCDCL SYNC Note 4 Note 4 X1 X2 Notes 1. 2. Circled characters indicate the Schmitt trigger input. Each displays output selects the following VLCX as input source. S0-S31: VLC1, COM0-COM2: VLC2, COM3: VLC0. 3. 4. When a split resistor is contained ....... Low level When no split resistor is contained ...... High impedance These pins are provided for future system expansion. At present, these pins are used only as pins P30 and P31. 10 µPD753012, 753016, 753017 3.2 Pins Other than Port Pins (2/2) Input/Output Dual Function Pin Function At Reset I/O Circuit TYPE Note XT1 Input – Crystal connection pin for the subsystem clock oscillator. When the external clock is used, input the external clock to pin XT1. In this case, pin XT2 must be left unconnected. Pin XT1 can be used as a 1bit input (test) pin. – – XT2 – Input – System reset input (low level active) – B IC – – Internally connected. Connect directly to VDD. – – V DD – – Positive power supply – – V SS – – GND – – Pin Name RESET Note Circled characters indicate the Schmitt trigger input. 11 µPD753012, 753016, 753017 3.3 Pin Input/Output Circuits The µPD753017 pin input/output circuits are shown schematically. TYPE A TYPE D VDD VDD data P-ch OUT P-ch IN N-ch output disable N-ch CMOS specification input buffer. Push-pull output that can be placed in output high impedance (both P-ch, N-ch off). TYPE E-B TYPE B VDD P.U.R. P.U.R. enable IN P-ch data Type D IN/OUT output disable Type A Schmitt trigger input having hysteresis characteristic. P.U.R. : Pull-Up Resistor TYPE F-A TYPE B-C VDD VDD P.U.R. P.U.R. enable P.U.R. P-ch P.U.R. enable P-ch data output disable IN/OUT Type D IN Type B P.U.R. : Pull-Up Resistor 12 P.U.R. : Pull-Up Resistor µPD753012, 753016, 753017 TYPE F-B TYPE H-A VDD P.U.R. P.U.R. enable P-ch output disable (P) SEG data VDD IN/OUT Type G-D P-ch IN/OUT data output disable bit port data N-ch Type D output disable output disable (N) P.U.R. : Pull-Up Resistor TYPE G-B TYPE M-C VDD VLC0 P.U.R. VLC1 P-ch P.U.R. enable N-ch P-ch IN/OUT OUT COM data N-ch data N-ch output disable P-ch VLC2 N-ch P.U.R. : Pull-Up Resistor TYPE G-D TYPE M-D VDD P.U.R. (Mask Option) VLC0 IN/OUT data VLC1 P-ch output disable N-ch VDD Input instruction OUT N-ch (+13 V withstand voltage) P-ch Note P.U.R. SEG data N-ch VLC2 N-ch Voltage limitation circuit (+13 V withstand voltage) P.U.R. : Pull-Up Resistor Note This pull-up resistor operates only when an input instruction is executed if the pull-up resistor is not connected by the mask option. (When the pin is at low level, current flows from VDD to the pin.) 13 µPD753012, 753016, 753017 3.4 Recommended Connection for Unused Pins Table 3-1. List of Recommended Connection for Unused Pins Pin Recommended Connection P00/INT4 Connect to VSS or V DD. P01/SCK Independently connect to VSS or V DD via resistor. P02/SO/SB0 P03/SI/SB1 Connected to VSS. P10/INT0, P11/INT1 Connect to VSS or V DD. P12/TI1/TI2/INT2 P13/TI0 P20/PTO0 P21/PTO1 P22/PTO2/PCL Input state : Individually connect to VSS or V DD via resistor. Output state : Leave unconnected. P23/BUZ P30/LCDCL P31/SYNC P32 P33 P40-P43 Input state : Connect to V SS. P50-P53 Output state : Connected to VSS. (Do not connect the pull-up resistor by mask option). P60/KR0-P63/KR3 P70/KR4-P73/KR7 Input state : Individually connected to V SS or V DD via resistor. Output state : Leave unconnected. S0-S23 Leave unconnected. S24/BP0-S31/BP7 COM0-COM3 14 VLC0-VLC2 Connect to VSS. BIAS Only if all of VLC0-VLC2 are unused, connect to VSS. In other cases, leave unconnected. XT1 Connect to VSS. XT2 Leave unconnected. IC Directly connect to VDD. µPD753012, 753016, 753017 4. SWITCHING FUNCTION BETWEEN MK I MODE AND MK II MODE 4.1 Differences between Mk I Mode and Mk II Mode The CPU of µPD753017 has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by the bit 3 of the stack bank select register (SBS). • Mk I mode: Upward compatible with µPD75316B. Can be used in the 75XL CPU with a ROM capacity of up to 16K bytes. • Mk II mode: Incompatible with µPD75316B. Can be used in all the 75XL CPU’s including those products whose ROM capacity is more than 16K bytes. Table 4-1. Differences between Mk I Mode and Mk II Mode Mk I Mode Mk II Mode Program memory (bytes) • µPD753012 : 12288 • µPD753016, 753017 : 16384 • µPD753012 : 12288 • µPD753016 : 16384 • µPD753017 : 24576 Number of stack bytes for subroutine instructions 2 bytes 3 bytes BRA !addr1 instruction CALLA !addr1 instruction Not available Available CALL !addr instruction 3-machine cycles 4-machine cycles CALLF !faddr instruction 2-machine cycles 3-machine cycles Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This mode enhances the software compatibility with products which have more than 16K bytes. When Mk II mode is selected, the number of stack bytes (usable area) in the execution of a subroutine call instruction increases by 1 per stack compared to Mk I mode. Furthermore, when a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine cycle. Therefore, when more importance is attached to RAM utilization or throughput than software compatibility, use the Mk I mode. 15 µPD753012, 753016, 753017 4.2 Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 10XXB Note at the beginning of a program. When using the Mk II mode, it must be initialized to 00XXBNote. Figure 4-1. Stack Bank Select Register Format Address 3 F84H SBS3 2 1 SBS2 SBS1 0 Symbol SBS0 SBS Stack area specification 0 0 Memory bank 0 0 1 Memory bank 1 1 0 Memory bank 2 1 1 Memory bank 3 0 0 must be set in the bit 2 position. Mode switching specification Note 0 Mk II mode 1 Mk I mode The desired numbers must be set in the XX positions. Caution Since SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select the Mk II mode. 16 µPD753012, 753016, 753017 5. MEMORY CONFIGURATION • Program memory (ROM) ............... 12288 × 8 bits (µPD753012) ............... 16384 × 8 bits ( µPD753016) ............... 24576 × 8 bits ( µPD753017) • Data memory (RAM) · Data area …1024 words × 4 bits (000H to 3FFH) · Peripheral hardware area…128 × 4 bits (F80H to FFFH) Figure 5-1. Program Memory Map (1/3) (a) µPD753012 7 0000H MBE 6 RBE 5 0 Internal reset start address (high-order 6 bits) Internal reset start address (Iow-order 8 bits) 0002H 0004H 0006H 0008H 000AH 000CH MBE MBE MBE MBE MBE MBE RBE RBE RBE RBE RBE RBE INTBT/INT4 start address (high-order 6 bits) INTBT/INT4 start address (Iow-order 8 bits) INT0 start address (high-order 6 bits) INT0 start address (Iow-order 8 bits) INT1 start address (high-order 6 bits) INT1 start address (Iow-order 8 bits) INTCSI start address (high-order 6 bits) INTCSI start address (Iow-order 8 bits) INTT0 start address (high-order 6 bits) INTT0 start address (Iow-order 8 bits) CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr1, BRA !addr1Note or CALLA !addr1Note instruction BRCB !caddr instruction branch address CALL !addr instruction subroutine entry address INTT1, INTT2 start address (high-order 6 bits) INTT1, INTT2 start address (Iow-order 8 bits) BR $addr instruction relative branch address (–15 to –1, +2 to +16) 0020H GETI instruction reference table Branch destination address and subroutine entry address when GETI instruction is executed 007FH 0080H 07FFH 0800H 0FFFH 1000H BRCB !caddr instruction branch address 1FFFH 2000H BRCB !caddr instruction branch address 2FFFH Note Can be used in Mk II mode only. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE, BR PCXA instruction. 17 µPD753012, 753016, 753017 Figure 5-1. Program Memory Map (2/3) (b) µPD753016 0000H 7 6 MBE RBE 5 0 Internal reset start address (high-order 6 bits) Internal reset start address (Iow-order 8 bits) 0002H 0004H 0006H 0008H 000AH 000CH MBE MBE MBE MBE MBE MBE RBE RBE RBE RBE RBE RBE INTBT/INT4 start address (high-order 6 bits) INTBT/INT4 start address (Iow-order 8 bits) INT0 start address (high-order 6 bits) INT0 start address (Iow-order 8 bits) INT1 start address (high-order 6 bits) INT1 start address (Iow-order 8 bits) INTCSI start address (high-order 6 bits) INTCSI start address (Iow-order 8 bits) INTT0 start address (high-order 6 bits) INTT0 start address (Iow-order 8 bits) CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction BRCB !caddr instruction branch address CALL !addr instruction subroutine entry address INTT1,INTT2 start address (high-order 6 bits) INTT1,INTT2 start address (Iow-order 8 bits) BR $addr instruction relative branch address (–15 to –1, +2 to +16) 0020H GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 0800H 0FFFH 1000H BRCB !caddr instruction branch address 1FFFH 2000H BRCB !caddr instruction branch address 2FFFH 3000H BRCB !caddr instruction branch address 3FFFH Note Can be used in Mk II mode only. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE, BR PCXA instruction. 18 µPD753012, 753016, 753017 Figure 5-1. Program Memory Map (3/3) (c) µPD753017 0000H 7 6 MBE RBE 5 0 Internal reset start address (high-order 6 bits) Internal reset start address (Iow-order 8 bits) 0002H 0004H 0006H 0008H 000AH 000CH MBE MBE MBE MBE MBE MBE RBE RBE RBE RBE RBE RBE INTBT/INT4 start address (high-order 6 bits) INTBT/INT4 start address (Iow-order 8 bits) INT0 start address (high-order 6 bits) INT0 start address (Iow-order 8 bits) INT1 start address (high-order 6 bits) INT1 start address (Iow-order 8 bits) INTCSI start address (high-order 6 bits) INTCSI start address (Iow-order 8 bits) INTT0 start address (high-order 6 bits) INTT0 start address (Iow-order 8 bits) CALLF !faddr instruction entry address BRCB !caddr instruction branch address BR !addr instruction branch address CALL !addr instruction branch address INTT1,INTT2 start address (high-order 6 bits) INTT1,INTT2 start address (Iow-order 8 bits) GETI instruction branch/call address 0020H GETI instruction reference table BR BCDE BR BCXA branch address BRA !addr1Note instruction branch address CALLA !addr1Note instruction branch address 007FH 0080H 07FFH 0800H BR $addr instruction relative branch address (–15 to –1, +2 to +16) 0FFFH 1000H BRCB !caddr instruction branch address 1FFFH 2000H BRCB !caddr instruction branch address 2FFFH 3000H BRCB !caddr instruction branch address 3FFFH 4000H BRCB !caddr instruction branch address 4FFFH 5000H BRCB !caddr instruction branch address 5FFFH Note Can be used in Mk II mode only. Caution The interrupt vector start address shown above consists of 14 bits. Set it in 16K space (0000H3FFFH). Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE, BR PCXA instruction. 19 µPD753012, 753016, 753017 Figure 5-2. Data Memory Map Data memory Memory bank 000H (32 × 4) General-purpose register area 01FH 020H 0 256 × 4 (224 × 4) 0FFH 100H 256 × 4 (224 × 4) 1DFH 1E0H (32 × 4) Display data memory Stack areaNote 1 1FFH 200H Data area static RAM (1024 × 4) 256 × 4 2 256 × 4 3 2FFH 300H 3FFH Not incorporated F80H Peripheral hardware area 128 × 4 FFFH Note For stack area, one memory bank can be selected among memory bank 0-3. 20 15 µPD753012, 753016, 753017 6. PERIPHERAL HARDWARE FUNCTIONS 6.1 Digital Input/Output Ports There are four types of I/O ports as follows. · CMOS input (PORT0, 1) : · CMOS input/output (PORT2, 3, 6, 7) : 16 · N-channel open-drain input/output (PORT4, 5) : · Bit port output (BP0-BP7) : Total 8 8 8 40 Table 6-1. Types and Features of Digital Ports Port (Pin Name) PORT0 (P00-P03) Function 4-bit input Also used for the INT4, SCK, SO/SB0, SI/SB1 pins. Dedicated 4-bit I/O port Also used for the INT0INT2 and TI0-TI2 pins. Can be set to input mode or output mode in 4-bit units. Also used for the PTO0PTO2, PCL, BUZ pins. Can be set to input mode or output mode in 1/4 bit units. Also used for the LCDCL, SYNC pins. 4-bit I/O (N-channel open-drain, 13 V withstanding) Can be set to input mode or output mode in 4-bit units. Ports 4 and 5 are paired and data can be input/ output in 8-bit units. On-chip pull-up resistor can be specified bit-wise by mask option. 4-bit I/O Can be set to input mode or output mode in 1/4-bit units. Ports 6 and 7 are paired and data can be input/ output in 8-bit units. Also used for the KR0-KR3 pins. 4-bit I/O PORT3 (P30-P33) PORT4 (P40-P43) PORT5 (P50-P53) PORT6 (P60-P63) PORT7 (P70-P73) BP0-BP7 Remarks Dual function pins also function as output pins depending on the operation mode when the serial interface function is used. PORT1 (P10-P13) PORT2 (P20-P23) Operation & Features Can be set to input mode or output mode in 4-bit units. 1-bit output Outputs data bit-wise. Can be switched to LCD drive segment output S24-S31 by software. Also used for the KR4-KR7 pins. — 21 µPD753012, 753016, 753017 6.2 Clock Generator Operation of the clock generator is determined by the processor clock control register (PCC) and system clock control register (SCC). The two clocks, the main system clock and subsystem clock, are available. The instruction excution time can be altered. • 0.95 µs, 1.91 µs, 3.81 µs, 15.3 µs (main system clock : at 4.19 MHz operation) • 0.67 µs, 1.33 µs, 2.67 µs, 10.7 µs (main system clock : at 6.0 MHz operation) • 122 µs (subsystem clock : at 32.768 kHz operation) Figure 6-1. Clock Generator Block Diagram · Basic interval timer (BT) · Timer/event counter · Serial interface · Watch timer · LCD controller/driver · INT0 noise eliminator · Clock output circuit XT1 VDD XT2 Subsystem clock oscillator fXT Main system clock oscillator fX LCD controller/driver Watch timer X1 VDD X2 1/1~1/4096 Divider 1/2 1/4 1/16 Selector WM.3 SCC Oscillation stop SCC3 Divider Selector 1/4 Internal bus SCC0 Φ · CPU · INT0 noise eliminator · Clock output circuit PCC PCC0 PCC1 4 HALT F/F PCC2 S HALTNote STOPNote PCC3 R PCC2, PCC3 Clear STOP F/F Q Q Wait release signal from BT S RESET signal R Standby release signal from interrupt control circuit Note Instruction execution Remarks 1. 22 fX = Main system clock frequency 2. fXT = Subsystem clock frequency 3. Φ = CPU clock 4. PCC: Processor Clock Control Register 5. SCC: System Clock Control Register 6. One clock cycle (tCY) of Φ equal to one machine cycle of the instruction. µPD753012, 753016, 753017 6.3 Subsystem Clock Oscillator Control Functions The µPD753017 subsystem clock oscillator has the following two control functions. • Selects by software whether an on-chip feedback resistor is to be used or notNote. • Reduces current consumption by decreasing the drive current of the on-chip inverter when the supply current is high (VDD ≥ 2.7 V). Note When not using the subsystem clock, set SOS.0 to 1 in software (on-chip feedback resistor is not used), connect XT1 to VSS, and leave XT2 unconnected, so that the current consumption of the subsystem clock oscillator can be reduced. The above functions can be used by switching the bits 0 and 1 of the sub-oscillator control register (SOS). (Refer to Figure 6-2.) Figure 6-2. Subsystem Clock Oscillator VDD SOS.0 Feedback resistor Inverter µ PD753017 SOS.1 XT1 XT2 VDD 23 µPD753012, 753016, 753017 6.4 Clock Output Circuit The clock output circuit is provided to output the clock pulses from the P22, PTO2, and PCL pins to the remote control waveform outputs and peripheral LSI’s, etc. • Clock output (PCL) : Φ, 524, 262, 65.5 kHz (at 4.19 MHz operation) Φ, 750, 375, 93.8 kHz (at 6.0 MHz operation) Figure 6-3. Clock Output Circuit Block Diagram From clock generator From timer/event counter (channel 2) fX/23 Selector fX/24 Output buffer Selector Φ PCL/PTO2/P22 fX/26 PORT2.2 CLOM3 0 CLOM1 CLOM0 CLOM P22 output latch Bit 2 of PMGB Port 2 I/O mode specification bit 4 Internal bus Remark Special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable. 24 µPD753012, 753016, 753017 6.5 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. • Interval timer operation to generate a reference time interrupt • Watchdog timer operation to detect a runaway of program and reset the CPU • Selects and counts the wait time when the standby mode is released • Reads the contents of counting Figure 6-4. Basic Interval Timer/Watchdog Timer Block Diagram From clock generator Clear fX/25 fX/27 MPX Clear Basic interval timer (8-bit frequency divider) Set fX/29 BT fX/212 3 Wait release signal when standby is released. BTM3 BTM2 BTM1 BTM0 BTM SET1Note 4 BT interrupt request flag Vectored interrupt IRQBT request signal Internal reset signal WDTM SET1Note 8 1 Internal bus Note Instruction execution 25 µPD753012, 753016, 753017 6.6 Watch Timer The µPD753017 has one channel of watch timer. The watch timer has the following functions. • Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released by the IRQW. • 0.5 sec interval can be created by both the main system clock and subsystem clock. Take fX = 4.194304 MHz for the main system clock frequency and fXT = 32.768 kHz for the subsystem clock. • Convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the fast feed mode. • Outputs the frequencies (2.048, 4.096, 32.768 kHz) to the P23 and BUZ pins, usable for buzzer and trimming of system clock frequencies. • Clears the frequency divider to make the clock start with zero seconds. Figure 6-5. Watch Timer Block Diagram fW (512 Hz : 1.95 ms) 26 fW (256 Hz : 3.91 ms) 27 fX 128 From clock generator (32.768 kHz) Selector fW (32.768 kHz) fXT (32.768 kHz) Divider fW 214 2 Hz 0.5 sec 4 kHz 2 kHz fW fW 23 24 fLCD Selector INTW IRQW set signal Clear Selector Output buffer P23/BUZ WM WM7 PORT2.3 0 WM5 WM4 WM3 8 WM2 WM1 WM0 P23 output latch PMGB bit 2 Port 2 input/ output mode Bit test instruction Internal bus The values enclosed in parentheses are applied when fX = 4.194304 MHz and fXT = 32.768 kHz. 26 µPD753012, 753016, 753017 6.7 Timer/Event Counter The µPD753017 has three channels of timer/event counter. The timer/event counter has the following functions. • Programmable interval timer operation • Square wave output of any frequency to the PTOn pin • Event counter operation • Divides the frequency of signal input via the TIn pin to 1-Nth of the original signal and outputs the divided frequency to the PTOn pin (frequency divider operation). • Supplies the serial shift clock to the serial interface circuit. • Calls the counting status. The timer/event counter operates in the following four modes as set by the mode register. Table 6-2. Operation Modes of Timer/Event Counter Channel Channel 0 Channel 1 × × Channel 2 Mode 8-bit timer/event counter mode Gate control function PWM pulse generator mode × 16-bit timer/event counter mode × Gate control function Carrier generator mode × Note × Note × Note Used for gate control signal generation 27 28 Figure 6-6. Timer/Event Counter Block Diagram (channel 0) Internal bus 8 SET1Note 8 8 – TM06 TM05 TM04 TM03 TM02 0 TOE0 TMOD0 TM0 TO enable flag Modulo register (8) 0 8 PORT1.3 TOUT0 Match Comparator (8) TOUT F/F PTO0/P20 Output buffer 8 Input buffer Reset T0 TI0/P13 fx/24 From fx/26 clock fx/28 generator fx/210 PORT2.0 PGMB bit 2 Port 2 input/output mode To serial interface P20 output latch INTT0 IRQT0 set signal Count register (8) MPX CP Clear Timer operation start RESET IRQT0 clear signal Note Instruction execution Caution When setting data to the TM0, be sure to set bits 0 and 1 to 0. µPD753012, 753016, 753017 To timer/event counter (channel 2) Figure 6-7. Timer/Event Counter Block Diagram (channel 1) Internal bus 8 TOE1 TM1 – 8 TM16 TM15 TM14 TM13 TM12 TM11 TM10 T1 enable flag TMOD1 Decoder PORT1.2 PORT2.1 P21 output latch PMGB.2 Port 2 input/output mode Modulo register (8) 8 TI1/TI2/P12/INT2 MPX CP TOUT F/F P21/PTO1 Output buffer Reset 8 Timer/event counter output (channel 2) fx/25 fx/26 From clock fx/28 generator fx/210 fx/212 Match Comparator (8) Input buffer T1 Count register (8) Clear RESET 16 bit timer/event counter mode IRQT1 clear signal Selector Timer/event counter match signal (channel 2) (When 16-bit timer/event counter mode) Timer/event counter reload signal (channel 2) Timer/event counter comparator (channel 2) (When 16-bit timer/event counter mode) INTT1 IRQT1 set signal 29 µPD753012, 753016, 753017 Timer operation start 30 Figure 6-8. Timer/Event Counter Block Diagram (channel 2) Internal bus 8 Decoder MPX (8) 8 Comparator (8) Iuput buffer TI1/TI2/ P12/INT2 From clock generator Modulo register (8) 8 Modulo register for high level period setup (8) PORT1.2 fx fx/2 fx/24 fx/26 fx/28 fx/210 8 TMOD2 Match CP TOE2 REMC NRZB NRZ Reload TOUT F/F Reset 8 MPX PORT2.2 PMGB.2 P22 Port 2 output latch input/output TC2 TGCE Selector TM26 TM25 TM24 TM23 TM22 TM21 TM20 8 TMOD2H T2 Count register (8) P22/PCL/PTO2 Output buffer Selector 8 TM2 Selector 8 Overflow Timer/event counter clock input (channel 1) Carrier generator mode Clear INTT2 IRQT2 set signal 16-bit timer/event counter mode IRQT2 clear signal Timer operation start RESET Timer event counter TOUT F/F (channel 0) Timer/event counter match signal (channel 1) (When 16-bit timer/event counter mode) Timer/event counter match signal (channel 1) (When carrier generator mode) From clock output circuit µPD753012, 753016, 753017 Timer/event counter clear signal (channel 1) (When 16-bit timer/event counter mode) µPD753012, 753016, 753017 6.8 Serial Interface The µPD753017 is provided with an 8-bit clocked serial interface. This serial interface operates in the following four modes: · Operation stop mode · 3-wire serial I/O mode · 2-wire serial I/O mode · SBI mode 31 32 Figure 6-9. Serial Interface Block Diagram Internal bus 8/4 Bit test 8 8 CSIM 8 Bit manipulation Bit test Slave address register (SVA) (8) SBIC Match signal RELT CMDT Address comparator (8) P03/SI/SB1 SO latch SET CLR Selector Shift register (SIO) D Q BSYE P02/SO/SB0 ACKE ACKT (8) Busy/ acknowledge output circuit Selector Bus release/ command/ acknowledge detector RELD CMDD ACKD Serial clock counter P01 output Iatch Serial clock control circuit IRQCSI set signal INTCSI control circuit Serial clock selector External SCK fX/23 fX/24 fX/26 TOUT F/F (from timer/event counter) µPD753012, 753016, 753017 INTCSI P01/SCK µPD753012, 753016, 753017 6.9 LCD Controller/Driver The µPD753017 incorporates a display controller which generates segment and common signals according to the display data memory contents and incorporates segment and common drivers which can drive the LCD panel directly. The µPD753017 LCD controller/driver functions are as follows: • Display data memory is read automatically by DMA operation and segment and common signals are generated. • Display mode can be selected from among the following five: <1> Static <2> 1/2 duty (time multiplexing by 2), 1/2 bias <3> 1/3 duty (time multiplexing by 3), 1/2 bias <4> 1/3 duty (time multiplexing by 3), 1/3 bias <5> 1/4 duty (time multiplexing by 4), 1/3 bias • A frame frequency can be selected from among four in each display mode. • A maximum of 32 segment signal output pins (S0-S31) and four common signal output pins (COM0-COM3). • The segment signal output pins (S24-S27 and S28-S31) can be changed to the output ports in 4-pin units. • Split-resistor can be incorporated to supply LCD drive power. (Mask option) · Various bias methods and LCD drive voltages can be applicable. · When display is off, current flow to the split resistor is cut. • Display data memory not used for display can be used for normal data memory. • It can also operate by using the subsystem clock. 33 34 Figure 6-10. LCD Controller/Driver Block Diagram Internal bus 4 Display data memory 1FFH 3 2 1 0 1FEH 3 2 1 0 1F9H 3 2 1 0 1F8H 3 2 1 0 1E0H 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 8 4 4 8 Display mode register Display control register Port 3 output latch 1 0 Port mode register group A Timing controller 1 0 fLCD Multiplexer S31/BP7 S30/BP6 S24/BP0 Common driver S23 S0 COM3 COM2 COM1 COM0 LCD drive voltage control VLC2 VLC1 VLC0 LCD drive mode changer Segment driver P31/ P30/ SYNC LCDCL µPD753012, 753016, 753017 Selector µPD753012, 753016, 753017 6.10 Bit Sequential Buffer … 16 Bits The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing a long data bit-wise. Figure 6-11. Bit Sequential Buffer Format Address Bit FC3H 3 Symbol L register 2 1 FC2H 0 3 2 BSB3 L = FH 1 FC1H 0 3 BSB2 L = CH L = BH 2 1 FC0H 0 3 BSB1 L = 8H L = 7H L = 4H L = 3H DECS L 2 1 0 BSB0 L = 0H INCS L Remarks 1. 2. In the pmem.@L addressing, the specified bit moves corresponding to the L register. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MBS specification. 35 µPD753012, 753016, 753017 7. INTERRUPT FUNCTION AND TEST FUNCTION µPD753017 has eight types of interrupt sources and two types of test sources. Among the test sources, INT2 is provided with two testable inputs for edge detection. µPD753017 has the following functions in the interrupt controller. (1) Interrupt function • Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (IEXXX) and interrupt master enable flag (IME). • Can set any interrupt start address. • Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS). • Test function of interrupt request flag (IRQXXX). An interrupt generated can be checked by software. • Release the standby mode. A release interrupt can be selected by the interrupt enable flag. (2) Test function • Test request flag (IRQXXX) generation can be checked by software. • Release the standby mode. The test source to be released can be selected by the test enable flag. 36 Figure 7-1. Interrupt Control Circuit Block Diagram Internal bus 2 1 4 IME IPS IM2 IM1 IST1 IST0 Interruput enable flag (IE×××) IM0 Decoder INTBT INT4/P00 INT0/P10 Note INT1/P11 KR0/P60 KR3/P63 Edge detector Rising edge detector VRQn IRQ4 IRQ0 IRQ1 INTCSI IRQCSI INTT0 IRQT0 INTT1 IRQT1 INTT2 IRQT2 INTW IRQW Selector IRQ2 Falling edge detector IM2 Note Noise eliminator (Standby release is disabled when noise eliminator is selected.) Priority control circuit Vector table address generator Standby release signal 37 µPD753012, 753016, 753017 INT2/TI1/TI2/P12 Selector Both edge detector Edge detector IRQBT µPD753012, 753016, 753017 8. STANDBY FUNCTION In order to save power consumption while a program is in a standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the µPD753017. Table 8-1. Operation Status in Standby Mode STOP Mode HALT Mode Set instruction STOP instruction HALT instruction System clock when set Settable only when the main system clock is used. Settable both by the main system clock and subsystem clock. Operation status Clock generator Only the main system clock stops oscillation. Only the CPU Φ halts (oscillation continues). Basic interval timer Operation stops Operation. Note 1 BT mode : Sets IRQBT at reference time intervals. WT mode: Generates reset signal when BT overflows. Serial interface Operable only when an external SCK input is selected as the serial clock. Operable Note 1 Operable only when a signal input to Operable Note 1 Timer/event counter the TI0-TI2 pins is specified as the count clock. Watch timer Operable when fXT is selected as the count clock. Operable LCD controller/driver Operable only when fXT is selected as the LCDCL. Operable External interrupt The INT1, 2, and 4 are operable. Only the INT0 is not operated.Note 2 CPU The operation stops. Release signal Notes 1. 2. Cannot operate only when the main system clock stops. Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode register(IM0). 38 Interrupt request signal sent from the operable hardware enabled by the interrupt enable flag or RESET signal input. µPD753012, 753016, 753017 9. RESET FUNCTION There are two reset inputs: external reset signal (RESET) and reset signal sent from the basic interval timer/ watchdog timer. When either one of the reset signals are input, an internal reset signal is generated. Figure 91 shows the circuit diagram of the above two inputs. Figure 9-1. Configuration of Reset Function RESET Internal reset signal Reset signal sent from the basic interval timer/watchdog timer WDTM Internal bus The µPD753017 is set by the RESET signal generated and each device is initialized as listed in Table 9-1. Figure 9-2 shows the timing chart of the reset operation. Figure 9-2. Reset Operation by RESET Signal Generation Wait Note RESET signal generated Operation mode or standby mode HALT mode Operation mode Internal reset operation Note The following two times can be selected by the mask option. 2 17/fX (21.8 ms : at 6.00 MHz operation, 31.3 ms : at 4.19 MHz operation) 2 15/fX (5.46 ms : at 6.00 MHz operation, 7.81 ms : at 4.19 MHz operation) 39 µPD753012, 753016, 753017 Table 9-1. Status of Each Device After Reset (1/2) RESET Signal Generation in Standby Mode RESET Signal Generation in Operation µPD753012, 753016 Sets the low-order 6 bits of program memory’s address 0000H to the PC13-PC8 and the contents of address 0001H to the PC7-PC0. Sets the low-order 6 bits of program memory’s address 0000H to the PC13-PC8 and the contents of address 0001H to the PC7-PC0. µPD753017 Sets the low-order 7 bits of program memory’s address 0000H to the PC14-PC8 and the contents of address 0001H to the PC7-PC0. Sets the low-order 7 bits of program memory’s address 0000H to the PC14-PC8 and the contents of address 0001H to the PC7-PC0. Held Undefined Skip flag (SK0-SK2) 0 0 Interrupt status flag (IST0) 0 0 Sets the bit 6 of program memory’s address 0000H to the RBE and bit 7 to the MBE. Sets the bit 6 of program memory’s address 0000H to the RBE and bit 7 to the MBE. Undefined Undefined 1000B 1000B Data memory (RAM) Held Undefined General-purpose register (X, A, H, L, D, E, B, C) Held Undefined Bank select register (MBS, RBS) 0, 0 0, 0 Undefined Undefined Hardware Program counter (PC) PSW Carry flag (CY) Bank enable flag (MBE, RBE) Stack pointer (SP) Stack bank select register (SBS) Basic interval/ Counter (BT) watchdog Mode register (BTM) 0 0 timer Watchdog timer enable flag (WDTM) 0 0 Timer/event Counter (T0) 0 0 counter (T0) Modulo register (TMOD0) FFH FFH 0 0 0, 0 0, 0 0 0 FFH FFH 0 0 0, 0 0, 0 0 0 Mode register (TM0) TOE0, TOUT F/F Timer/event Counter (T1) counter (T1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT F/F Timer/event Counter (T2) counter (T2) Modulo register (TMOD2) FFH FFH High level period setting modulo register (TMOD2H) FFH FFH 0 0 0, 0 0, 0 0, 0, 0 0, 0, 0 TGCE 0 0 Mode register (WM) 0 0 Mode register (TM2) TOE2, TOUT F/F REMC, NRZ, NRZB Watch timer 40 µPD753012, 753016, 753017 Table 9-1. Status of Each Device After Reset (2/2) Serial interface Hardware RESET Signal Generation in Standby Mode RESET Signal Generation in Operation Shift register (SIO) Held Undefined Operating mode register (CSIM) 0 0 SBI control register (SBIC) 0 0 Held Undefined Slave address register (SVA) Clock generator, Processor clock control register (PCC) 0 0 clock output System clock control register (SCC) 0 0 circuit Clock output mode register (CLOM) 0 0 Sub-oscillator control register (SOS) 0 0 LCD controller Display mode register (LCDM) 0 0 /driver Display control register (LCDC) 0 0 Interrupt Interrupt request flag (IRQXXX) Reset (0) Reset (0) function Interrupt enable flag (IEXXX) 0 0 Interrupt master enable flag (IME) 0 0 0, 0, 0 0, 0, 0 0 0 Output buffer Off Off Output latch Cleared (0) Cleared (0) I/O mode registers (PMGA, PMGB) 0 0 Pull-up resistor setting register (POGA) 0 0 Held Undefined INT0, 1, 2 mode registers (IM0, IM1, IM2) Priority selection register (IPS) Digital port Bit sequential buffer (BSB0-BSB3) 41 µPD753012, 753016, 753017 10. MASK OPTION The µPD753017 has the following mask options. • Mask option of P40 to P43 and P50 to P53 An on-chip pull-up resistor can be selected. <1> Specifies an on-chip pull-up resistor in bit units. <2> Does not specify an on-chip pull-up resistor. • Mask option of VLC0 to VLC2 and BIAS pins An on-chip split resistor for LDC driving can be selected. <1> Does not specify an on-chip divider resistor <2> Specifies four 10-kΩ (typ.) on-chip split resistors at the same time. <3> Specifies four 100-kΩ (typ.) on-chip split resistors at the same time. • Standby function mask option Wait time can be selected by RESET signai input. <1> 2 17/fX (21.8 ms: at fX = 6.0 MHz, 31.3 ms: at fX = 4.19 MHz) <2> 2 15/fX (5.46 ms: at fX = 6.0 MHz, 7.81 ms: at fX = 4.19 MHz) • Subsystem clock mask option Selectable an on-chip feedback resistor can be used/cannot be used <1> Make an on-chip feedback resistor usable (Switch on-chip feedback resistor ON/OFF in software) <2> Make an on-chip feedback resistor unusable (Disconnects on-chip feedback resistor in hardware) 42 µPD753012, 753016, 753017 11. INSTRUCTION SETS AND THEIR OPERATIONS (1) Operand identifiers and methods of use Operands are written in the operand column of each instruction in accordance with the method of use for the operand identifier of the instruction. For details, refer to RA75X Assembler Package User’s Manual— Language (U12385E). If there are several elements, one of them is selected. Capital letters and the + and – symbols are key words and are written as they are. For immediate data, appropriate numbers and labels are written. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be written. However, there are restrictions in the labels that can be written for fmem and pmem. For details, refer to User’s Manual. Identifier Format reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp rp1 rp2 rp' rp'1 XA, BC, BC, XA, BC, rpa rpa1 HL, HL+, HL–, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem bit 8-bit immediate data or label 2-bit immediate data or label fmem pmem FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label addr addr1 caddr faddr 0000H-2FFFH immediate data or label (µPD753012) 0000H-3FFFH immediate data or label (µPD753016, 753017) 0000H-5FFFH immediate data or label 12-bit immediate data or label 11-bit immediate data or label taddr 20H-7FH immediate data (where bit 0 = 0) or label PORTn IEXXX RBn MBn PORT0-PORT7 IEBT, IET0-IET2, IE0-IE2, IE4, IECSI, IEW RB0-RB3 MB0, MB1, MB2, MB3, MB15 BC, DE, DE BC, DE, DE, HL HL DE, HL, XA’, BC’, DE’, HL’ HL, XA’, BC’, DE’, HL’ Note Note mem can be only used even address in 8-bit data processing. 43 µPD753012, 753016, 753017 (2) Legend in explanation of operation 44 A : A register, 4-bit accumulator B : B register C : C register D : D register E : E register H : H register L : L register X : X register XA : XA register pair; 8-bit accumulator BC : BC register pair DE : DE register pair HL : HL register pair XA’ : XA’ expanded register pair BC’ : BC’ expanded register pair DE’ : DE’ expanded register pair HL’ : HL’ expanded register pair PC : Program counter SP : Stack pointer CY : Carry flag, bit accumulator PSW : Program status word MBE : Memory bank enable flag RBE : Register bank enable flag PORTn : Port n (n = 0-7) IME : Interrupt master enable flag IPS : Interrupt priority selection register IEXXX : Interrupt enable flag RBS : Register bank selection register MBS : Memory bank selection register PCC : Processor clock control register . : Separation between address and bit (XX) : The contents addressed by XX XXH : Hexadecimal data µPD753012, 753016, 753017 (3) Explanation of symbols under addressing area column *1 MB = MBE•MBS (MBS = 0-3, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (00H-7FH) MB = 15 (F80H-FFFH) MBE = 1 : MB = MBS (MBS = 0-3, 15) Data memory addressing *4 MB = 15, fmem = FB0H-FBFH, FF0H-FFFH *5 MB = 15, pmem = FC0H-FFFH *6 µPD753012 addr = 0000H-2FFFH µPD753016 753017 addr = 0000H-3FFFH µPD753012 753016 753017 (In Mk I mode) addr = (Current PC) – 15 to (Current PC) – 1 (Current PC) + 2 to (Current PC) + 16 µPD753017 (In Mk II mode) addr1 = (Current PC) – 15 to (Current PC) – 1 (Current PC) + 2 to (Current PC) + 16 µPD753012 caddr = 0000H-0FFFH(PC13, 12 = 00B) or 1000H-1FFFH(PC13, 12 = 01B) or 2000H-2FFFH(PC13, 12 = 10B) µPD753016 caddr = 0000H-0FFFH(PC 13, 12 1000H-1FFFH(PC13, 12 2000H-2FFFH(PC13, 12 3000H-3FFFH(PC13, 12 µPD753017 caddr = 0000H-0FFFH(PC 14, 13, 12 1000H-1FFFH(PC14, 13, 12 2000H-2FFFH(PC14, 13, 12 3000H-3FFFH(PC14, 13, 12 4000H-4FFFH(PC14, 13, 12 5000H-5FFFH(PC14, 13, 12 *7 *8 *9 faddr = 0000H-07FFH *10 taddr = 0020H-007FH *11 µPD753012 addr1 = 0000H-2FFFH µPD753016 addr1 = 0000H-3FFFH µPD753017 addr1 = 0000H-5FFFH Remarks 1. = = = = 00B) or 01B) or 10B) or 11B) = = = = = = 000B) 001B) 010B) 011B) 100B) 101B) Program memory addressing or or or or or MB indicates memory bank that can be accessed. 2. In *2, MB = 0 independently of how MBE and MBS are set. 3. In *4 and *5, MB = 15 independently of how MBE and MBS are set. 4. *6 to *11 indicate the areas that can be addressed. 45 µPD753012, 753016, 753017 (4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. • When no skip is made: S = 0 • When the skipped instruction is a 1- or 2-byte instruction: S = 1 • When the skipped instruction is a 3-byte instructionNote: S = 2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of CPU clock Φ (= tCY); time can be selected from among four types by setting PCC. 46 µPD753012, 753016, 753017 Instruction Group Transfer instruction Mnemonic MOV XCH Number of Bytes Number of Machine Cycles A, #n4 1 1 A ← n4 reg1, #n4 2 2 reg1 ← n4 XA, #n8 2 2 XA ← n8 String effect A HL, #n8 2 2 HL ← n8 String effect B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) *1 A, @HL+ 1 2+S A ← (HL), then L ← L+1 *1 L=0 A, @HL– 1 2+S A ← (HL), then L ← L–1 *1 L = FH A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A *1 @HL, XA 2 2 (HL) ← XA *1 A, mem 2 2 A ← (mem) *3 XA, mem 2 2 XA ← (mem) *3 mem, A 2 2 (mem) ← A *3 mem, XA 2 2 (mem) ← XA *3 A, reg 2 2 A ← reg XA, rp’ 2 2 XA ← rp’ reg1, A 2 2 reg1 ← A rp’1, XA 2 2 rp’1 ← XA A, @HL 1 1 A ↔ (HL) *1 A, @HL+ 1 2+S A ↔ (HL), then L ← L+1 *1 L=0 A, @HL– 1 2+S A ↔ (HL), then L ← L–1 *1 L = FH A, @rpa1 1 1 A ↔ (rpa1) *2 XA, @HL 2 2 XA ↔ (HL) *1 A, mem 2 2 A ↔ (mem) *3 XA, mem 2 2 XA ↔ (mem) *3 A, reg1 1 1 A ↔ reg1 XA, rp’ 2 2 XA ↔ rp’ Operand Operation Addressing Area Skip Condition String effect A 47 µPD753012, 753016, 753017 Instruction Group Mnemonic Table MOVTNote 1 Operand XA, @PCDE Number of Bytes Number of Machine Cycles 1 3 Operation Addressing Area Skip Condition XA ← (PC13–8+DE)ROM • µPD753017 XA ← (PC14–8+DE)ROM XA, @PCXA 1 3 XA ← (PC13–8+XA)ROM • µPD753017 XA ← (PC14–8+XA)ROM XA, @BCDENote 2 XA, @BCXANote 2 1 1 3 3 XA ← (B1,0+CDE)ROM *6 • µPD753017 XA ← (B2–0+CDE)ROM *11 XA ← (B1,0+CXA)ROM *6 µPD753017 XA ← (B2–0+CXA)ROM *11 • Bit transfer Operation MOV1 ADDS ADDC SUBS SUBC Notes 1. CY, fmem.bit 2 2 CY ← (fmem.bit) *4 CY, pmem.@L 2 2 CY ← (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← (H+mem3–0.bit) *1 fmem.bit, CY 2 2 (fmem.bit) ← CY *4 pmem.@L, CY 2 2 (pmem7–2+L3–2.bit(L1–0)) ← CY *5 @H+mem.bit, CY 2 2 (H+mem3–0.bit) ← CY *1 A, #n4 1 1+S A ← A+n4 carry XA, #n8 2 2+S XA ← XA+n8 carry A, @HL 1 1+S A ← A+(HL) XA, rp’ 2 2+S XA ← XA+rp’ carry rp’1, XA 2 2+S rp’1 ← rp’1+XA carry A, @HL 1 1 A, CY ← A+(HL)+CY XA, rp’ 2 2 XA, CY ← XA+rp’+CY rp’1, XA 2 2 rp’1, CY ← rp’1+XA+CY A, @HL 1 1+S A ← A–(HL) XA, rp’ 2 2+S XA ← XA–rp’ borrow rp’1, XA 2 2+S rp’1 ← rp’1–XA borrow A, @HL 1 1 A, CY ← A–(HL)–CY XA, rp’ 2 2 XA, CY ← XA–rp’–CY rp’1, XA 2 2 rp’1, CY ← rp’1–XA–CY Only the following bits are valid for the B register. µPD753012, 753016 : low-order 2 bits µPD753017 : low-order 3 bits Remark PC14 is fixed to 0 when the µPD753017 is set in the Mk I mode. 48 carry *1 *1 borrow *1 The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 2. *1 µPD753012, 753016, 753017 Instruction Group Operating instructions Number of Bytes Number of Machine Cycles A, #n4 2 2 A ← A ∧ n4 A, @HL 1 1 A ← A ∧ (HL) XA, rp’ 2 2 XA ← XA ∧ rp’ rp’1, XA 2 2 rp’1 ← rp’1 ∧ XA A, #n4 2 2 A ← A ∨ n4 A, @HL 1 1 A ← A ∨ (HL) XA, rp’ 2 2 XA ← XA ∨ rp’ rp’1, XA 2 2 rp’1 ← rp’1 ∨ XA A, #n4 2 2 A ← A ∨ n4 A, @HL 1 1 A ← A ∨ (HL) XA, rp’ 2 2 XA ← XA ∨ rp’ rp’1, XA 2 2 rp’1 ← rp’1 ∨ XA RORC A 1 1 CY ← A0, A3 ← CY, An–1 ← An NOT A 2 2 A←A INCS reg 1 1+S reg ← reg+1 reg=0 rp1 1 1+S rp1 ← rp1+1 rp1=00H @HL 2 2+S (HL) ← (HL)+1 *1 (HL)=0 mem 2 2+S (mem) ← (mem)+1 *3 (mem)=0 reg 1 1+S reg ← reg–1 reg=FH rp’ 2 2+S rp’ ← rp’–1 rp'=FFH reg, #n4 2 2+S Skip if reg = n4 reg=n4 @HL, #n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 1 1+S Skip if A = (HL) *1 A = (HL) XA, @HL 2 2+S Skip if XA = (HL) *1 XA = (HL) A, reg 2 2+S Skip if A = reg A=reg XA, rp’ 2 2+S Skip if XA = rp’ XA=rp’ SET1 CY 1 1 CY ← 1 CLR1 CY 1 1 CY ← 0 SKT CY 1 1+S NOT1 CY 1 1 Mnemonic AND OR XOR Accumulator manipulation instructions Increment and Decrement instructions DECS Comparison instruction Carry flag manipulation instruction SKE Operand Operation Skip if CY = 1 Addressing Area Skip Condition *1 *1 *1 CY=1 CY ← CY 49 µPD753012, 753016, 753017 Instruction Group Memory bit manipulation instructions Mnemonic SET1 CLR1 SKT SKF SKTCLR AND1 OR1 XOR1 50 Number of Bytes Number of Machine Cycles mem.bit 2 2 (mem.bit) ←1 *3 fmem.bit 2 2 (fmem.bit) ←1 *4 pmem.@L 2 2 (pmem7–2+L3–2.bit(L1–0)) ←1 *5 @H+mem.bit 2 2 (H+mem3–0.bit) ←1 *1 mem.bit 2 2 (mem.bit) ←0 *3 fmem.bit 2 2 (fmem.bit) ←0 *4 pmem.@L 2 2 (pmem7–2+L3–2.bit(L1–0)) ←0 *5 @H+mem.bit 2 2 (H+mem3–0.bit) ←0 *1 mem.bit 2 2+S Skip if (mem.bit)=1 *3 (mem.bit)=1 fmem.bit 2 2+S Skip if (fmem.bit)=1 *4 (fmem.bit)=1 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0))=1 *5 (pmem.@L)=1 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit)=1 *1 (@H+mem.bit)=1 mem.bit 2 2+S Skip if (mem.bit)=0 *3 (mem.bit)=0 fmem.bit 2 2+S Skip if (fmem.bit)=0 *4 (fmem.bit)=0 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0))=0 *5 (pmem.@L)=0 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit)=0 *1 (@H+mem.bit)=0 fmem.bit 2 2+S Skip if (fmem.bit)=1 and clear *4 (fmem.bit)=1 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0))=1 and clear *5 (pmem.@L)=1 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit)=1 and clear *1 (@H+mem.bit)=1 CY, fmem.bit 2 2 CY ← CY ∧ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ∧ (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY ∧ (H+mem3–0.bit) *1 CY, fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ∨ (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY ∨ (H+mem3–0.bit) *1 CY, fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ∨ (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY ∨ (H+mem3–0.bit) *1 Operand Operation Addressing Area Skip Condition µPD753012, 753016, 753017 Instruction Group Branch instructions Number of Bytes Number of Machine Cycles addr – – PC13–0 ← addr Select appropriate instruction from among BR !addr, BRCB !caddr, and BR $addr according to the assembler being used. BR !addr BRCB !caddr BR $addr *6 addr1 – – • µPD753017 PC14–0 ← addr1 Select appropriate instruction from among BR !addr, BRA !caddr1 BRCB !caddr, and BR $addr according to the assembler being used. BR !addr BRA !addr1 BRCB !caddr BR $addr *11 !addr 3 3 PC13–0 ← addr *6 Mnemonic BRNote 1 Operand Operation Addressing Area Skip Condition µPD753017 PC14 ← 0, PC13–0 ← addr • $addr 1 2 PC13–0 ← addr $addr1 1 2 • PCDE 2 3 PC13–0 ← PC13–8+DE *7 µPD753017 PC14–0 ← addr1 µPD753017 PC14–0 ← PC14–8+DE • PCXA 2 3 PC13–0 ← PC13–8+XA µPD753017 PC14–0 ← PC14–8+XA • BCDENote 2 2 3 PC13–0 ← B1,0+CDE *6 µPD753017 PC14–0 ← B2–0+CDE *11 PC13–0 ← B1,0+CXA *6 µPD753017 PC14–0 ← B2–0+CXA *11 µPD753012, 753016 PC13–0 ← addr *6 µPD753017 PC14–0 ← addr1 *11 • BCXANote2 2 3 • BRANote1 Notes 1. !addr 3 3 • !addr1 3 3 • The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 2. Only the following bits are valid for the B register. µPD753012, 753016 : low-order 2 bits µPD753017 : low-order 3 bits Remark PC14 is fixed to 0 when the µPD753017 is set in the Mk I mode. 51 µPD753012, 753016, 753017 Instruction Group Branch instructions Mnemonic BRCBNote Operand !caddr Number of Bytes Number of Machine Cycles 2 2 Operation PC13–0 ← PC13,12+caddr11-0 Addressing Area Skip Condition *8 µPD753017 PC14–0 ← PC14,13,12+caddr11–0 • Subroutine stack control instructions CALLANote CALLNote CALLFNote Note !addr 3 3 • µPD753012, 753016 (SP–5)(SP–6)(SP–3)(SP–4) ← 0, 0, PC13–0 (SP–2) ← ×, ×, MBE, RBE PC13–0 ← addr, SP ← SP–6 !addr1 3 3 • µPD753017 (SP–5)(SP–6)(SP–3)(SP–4) ← 0, PC14–0 (SP–2) ← ×, ×, MBE, RBE PC14–0 ← addr1, SP ← SP–6 *11 !addr 3 3 (SP–4)(SP–1)(SP–2) ← PC11–0 (SP–3) ← MBE, RBE, PC13, PC12 PC13–0 ← addr, SP ← SP–4 *6 4 • 4 • 2 (SP–4)(SP–1)(SP–2) ← PC11–0 (SP–3) ← MBE, RBE, PC13, PC12 PC13–0 ← 000+faddr, SP ← SP–4 3 • 3 • !faddr 2 µPD753012, 753016 (SP–5)(SP–6)(SP–3)(SP–4) ← 0, 0, PC13–0 (SP–2) ← ×, ×, MBE, RBE PC13–0 ← addr, SP ← SP–6 µPD753017 (SP–5)(SP–6)(SP–3)(SP–4) ← 0, PC14–0 (SP–2) ← ×, ×, MBE, RBE PC14 ← 0, PC13–0 ← addr, SP ← SP–6 *9 µPD753012, 753016 (SP–5)(SP–6)(SP–3)(SP–4) ← 0, 0, PC13–0 (SP–2) ← ×, ×, MBE, RBE PC13–0 ← 000+faddr, SP ← SP–6 µPD753017 (SP–5)(SP–6)(SP–3)(SP–4) ← 0, PC14–0 (SP–2) ← ×, ×, MBE, RBE PC14–0 ← 0000+faddr, SP ← SP–6 The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. Remark PC14 is fixed to 0 when the µPD753017 is set in the Mk I mode. 52 *6 µPD753012, 753016, 753017 Instruction Group Subroutine stack control instructions Mnemonic RETNote Operand Number of Bytes Number of Machine Cycles 1 3 Operation Addressing Area Skip Condition MBE, RBE, PC13, PC12 ← (SP+1) PC11–0 ← (SP)(SP+3)(SP+2), SP ← SP+4 µPD753012, 753016 ×, ×, MBE, RBE ← (SP+4) 0, 0, PC13, PC12 ← (SP+1) PC11–0 ← (SP)(SP+3)(SP+2), SP ← SP+6 • µPD753017 ×, ×, MBE, RBE ← (SP+4) 0, PC14, PC13, PC12 ← (SP+1) PC11–0 ← (SP)(SP+3)(SP+2), SP ← SP+6 • RETSNote 1 3+S MBE, RBE, PC13, PC12 ← (SP+1) PC11–0 ← (SP)(SP+3)(SP+2), SP ← SP+4 then skip unconditionally Unconditional µPD753012, 753016 ×, ×, MBE, RBE ← (SP+4) 0, 0, PC13, PC12 ← (SP+1) PC11–0 ← (SP)(SP+3)(SP+2), SP ← SP+6 then skip unconditionally • µPD753017 ×, ×, MBE, RBE ← (SP+4) 0, PC14, PC13, PC12 ← (SP+1) PC11–0 ← (SP)(SP+3)(SP+2), SP ← SP+6 then skip unconditionally • RETINote 1 3 MBE, RBE, PC13, PC12 ← (SP+1) PC11–0 ← (SP)(SP+3)(SP+2) PSW ← (SP+4)(SP+5), SP ← SP+6 µPD753012, 753016 0, 0, PC13, PC12 ← (SP+1) PC11–0 ← (SP)(SP+3)(SP+2) PSW ← (SP+4)(SP+5), SP ← SP+6 • µPD753017 0, PC14, PC13, PC12 ← (SP+1) PC11–0 ← (SP)(SP+3)(SP+2) PSW ← (SP+4)(SP+5), SP ← SP+6 • Note The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. Remark PC14 is fixed to 0 when the µPD753017 is set in the Mk I mode. 53 µPD753012, 753016, 753017 Instruction Group Subroutine stack control instructions Number of Bytes Number of Machine Cycles rp 1 1 (SP–1)(SP–2) ← rp, SP ← SP–2 BS 2 2 (SP–1) ← MBS, (SP–2) ← RBS, SP ← SP–2 rp 1 1 rp ← (SP+1)(SP), SP ← SP+2 BS 2 2 MBS ← (SP+1), RBS ← (SP), SP ← SP+2 2 2 IME(IPS.3) ← 1 2 2 IEXXX ← 1 2 2 IME(IPS.3) ← 0 IEXXX 2 2 IEXXX ← 0 A, PORTn 2 2 A ← PORTn (n = 0-7) XA, PORTn 2 2 XA ← PORTn+1, PORTn (n = 4, 6) PORTn, A 2 2 PORTn ← A (n = 2-7) PORTn, XA 2 2 PORTn+1, PORTn ← XA (n = 4, 6) HALT 2 2 Set HALT mode (PCC.2 ← 1) STOP 2 2 Set STOP mode (PCC.3 ← 1) NOP 1 1 No operation RBn 2 2 RBS ← n (n = 0-3) MBn 2 2 MBS ← n (n = 0-3, 15) taddr 1 3 • When TBR instruction PC13–0 ← (taddr)5–0+(taddr+1) Mnemonic PUSH POP Interrupt control instructions Operand EI IEXXX DI Input/output instructions INNote 1 OUTNote 1 CPU control instruction Special instruction SEL GETINotes 2, 3 Addressing Area Operation –––––––––––––––––––––––––––––––––– Skip Condition *10 –––––––––––– • When TCALL instruction (SP–4)(SP–1)(SP–2) ← PC11–0 (SP–3) ← MBE, RBE, PC13, PC12 PC13–0 ← (taddr)5–0+(taddr+1) SP ← SP–4 –––––––––––––––––––––––––––––––––– • When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed 1 3 Notes 1. –––––––––––– • When TCALL instruction (SP–5)(SP–6)(SP–3)(SP–4) ← 0, PC14–0 (SP–2) ← ×, ×, MBE, RBE PC13–0 ← (taddr)5–0+(taddr+1) SP ← SP–6, PC14 ← 0 –––––––––––––––––––––––––––––––––––––––––– 3 Depending on the reference instruction • µPD753017 • When TBR instruction PC13–0 ← (taddr)5–0+(taddr+1) PC14 ← 0 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –– – – – – 4 –––––––––––– • When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed ––––––––––––– Depending on the reference instruction While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1 and MBS must be set to 15. 2. The shaded area is applicable only to the Mk II mode. The other area is applicable only to Mk I mode. 3. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI instruction. Remark PC14 is fixed to 0 when the µPD753017 is set in the Mk I mode. 54 µPD753012, 753016, 753017 12. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 ˚C) Parameter Symbol Conditions Ratings Unit Supply voltage V DD –0.3 to +7.0 V Input voltage V I1 Other than ports 4 and 5 –0.3 to VDD +0.3 V V I2 Ports 4 Pull-up resistor provided –0.3 to V DD +0.3 V and 5 N-ch open drain –0.3 to +14 V Output voltage VO High-level output current IOH –0.3 to V DD +0.3 V Per pin –10 mA Low-level output current IOL Total of all pins –30 mA Per pin 30 mA Operating ambient temperature TA 200 mA –40 to +85 ˚C Storage temperature Tstg –65 to +150 ˚C Total of all pins Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the product(s). Be sure to use the product(s) within the ratings. Capacitance (TA = 25 ˚C, V DD = 0 V) Parameter Symbol Conditions Input capacitance CIN f = 1 MHz Output capacitance COUT Pins other than tested pins: 0 V I/O capacitance CIO MIN. TYP. MAX. Unit 15 pF 15 pF 15 pF 55 µPD753012, 753016, 753017 Main System Clock Oscillator Characteristics (TA = –40 to +85 ˚C) Recommended Constants Oscillator Ceramic oscillator X1 Parameter C2 Crystal oscillator Unit 6.0Note 2 MHz 4 ms 6.0Note 2 MHz ms VDD = 2.2 to 5.5 V Oscillation stabilization timeNote 3 After VDD has reached MIN. value of oscillation voltage range Oscillation frequency (f X) Note 1 VDD = 2.2 to 5.5 V C2 Oscillation stabilization timeNote 3 VDD = 4.5 to 5.5 V 10 VDD = 2.2 to 5.5 V 30 VDD Notes 1. 1.0 MAX. 1.0 X2 C1 X1 TYP. Oscillation frequency (f X) Note 1 VDD External clock MIN. X2 C1 X1 Conditions X2 X1 input frequency (f X) Note 1 VDD = 1.8 to 5.5 V 1.0 6.0Note 4 MHz X1 input high-, low-level widths (t XH, tXL) VDD = 1.8 to 5.5 V 83.3 500 ns The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillator only. For the instruction execution time, refer to AC Characteristics. 2. When the oscillation frequency is 4.7 MHz < fX ≤ 6.0 MHz at 2.2 V ≤ V DD < 2.7 V, assign a value other than 0011 to the processor clock control register (PCC). If 0011 is assigned to PCC, one machine cycle falls short of the rated value of 0.85 µs. 3. The oscillation stabilization time is the time required for oscillation to stabilize after VDD has been applied or STOP mode has been released. 4. When the X1 input frequency is 4.19 MHz < fX ≤ 6.0 MHz at 1.8 V ≤ VDD < 2.7 V, assign a value other than 0011 to the processor clock control register (PCC). If 0011 is assigned to PCC, one machine cycle falls short of the rated value of 0.95 µs. Caution When using the main system clock oscillator, wire the portion enclosed by the dotted line in the above figure as follows to prevent adverse influence from wiring capacitance: · Keep the wiring length as short as possible. · Do not cross the wiring with any other signal lines. · Do not route the wiring in the vicinity of a line through which a high alternating current flows. · Always keep the ground point of the capacitor of the oscillator at the same potential as VDD . · Do not ground to a power supply pattern through which a high current flows. · Do not extract any signal from the oscillator. 56 µPD753012, 753016, 753017 Subsystem Clock Oscillator Characteristics (TA = –40 to +85 ˚C) Recommended Constants Oscillator Crystal oscillator XT1 Parameter Conditions Oscillation frequency (f XT)Note 1 VDD = 2.2 to 5.5 V Oscillation stabilization timeNote 2 VDD = 4.5 to 5.5 V MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.0 2 s XT2 R C3 C4 VDD = 2.2 to 5.5 V VDD External clock Notes 1. XT1 XT2 10 XT1 input frequency (f XT)Note 1 VDD = 1.8 to 5.5 V 32 100 kHz XT1 input high-, low-level widths (t XTH, t XTL) VDD = 1.8 to 5.5 V 5 15 µs The oscillation frequency shown above indicate characteristics of the oscillator only. For the instruction execution time, refer to AC Characteristics. 2. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied. Caution When using the subsystem clock oscillator, wire the portion enclosed by the dotted line in the above figure as follows to prevent adverse influence from to wiring capacitance: · Keep the wiring length as short as possible. · Do not cross the wiring with any other signal lines. · Do not route the wiring in the vicinity of a line through which a high alternating current flows. · Always keep the ground point of the capacitor of the oscillator at the same potential as VDD . · Do not ground to a power supply pattern through which a high current flows. · Do not extract any signal from the oscillator. The subsystem clock oscillator has a low amplification factor to reduce current dissipation and is more susceptible to noise than the main system clock oscillator. Therefore, exercise utmost care in wiring the subsystem clock oscillator. 57 µPD753012, 753016, 753017 Recommended Oscillator Constants Ceramic oscillator (TA = –40 to +85 ˚C) Manufacturer Murata Mfg. Co., Ltd. Part Number Frequency (MHz) Oscillation Voltage Range (V DD) C1 C2 MIN. MAX. CSB1000JNote 1.0 100 100 2.7 5.5 CSA2.00MG040 2.0 100 100 – – CST2.00MG040 CSA4.19MG 30 30 CST4.19MGW – – CSA4.19MGU 30 30 CST4.19MGWU – – CSA6.00MG Kyocera Corp. Recommended Circuit Constant (pF) 4.19 30 30 CST6.00MGW 6.0 – – CSA6.00MGU 30 30 CST6.00MGWU – – Remark Rd = 5.6 kΩ Capacitor-contained model 2.5 5.5 Capacitor-contained model 2.2 5.5 Capacitor-contained model 2.7 5.5 Capacitor-contained model 2.5 5.5 Capacitor-contained model KBR-1000F/Y 1.0 220 220 2.9 5.5 KBR-2.0MS 2.0 82 82 3.1 5.5 KBR-4.19MSA 4.19 33 33 2.7 5.5 –20 to +85 ˚C KBR-4.19MKS PBRC 4.19A – – Capacitor-contained model PBRC 4.19B – – –20 to +85 ˚C 33 33 KBR-6.0MSA 6.0 2.8 5.5 –20 to +85 ˚C KBR-6.0MKS TDK Corp. Note PBRC 6.00A – – Capacitor-contained model PBRC 6.00B – – –20 to +85 ˚C 30 30 FCR2.0MC3 2.0 2.0 5.5 FCR4.19MC5 4.19 2.5 5.5 FCR6.0MC5 6.0 2.7 5.5 When using the CSB1000J (1.00 MHz) by Murata Mfg. Co., Ltd. as a ceramic oscillator, a limiting resistor (Rd = 5.6 kΩ) is necessary (refer to the figure below). The resistor is not necessary when using the other recommended oscillators. Example of recommended main system clock oscillator (when using CSB1000J by Murata Mfg. Co., Ltd.) X1 X2 CSB1000J C1 C2 VDD 58 Rd µPD753012, 753016, 753017 DC Characteristics (TA = –40 to +85 ˚C, VDD = 2.2 to 5.5 V) Parameter Low-level output Symbol IOL current High-level input VIH1 Conditions MAX. Unit Per pin 15 mA Total of all pins 120 mA Ports 2, 3 voltage VIH2 VIH3 2.7 V ≤ V DD ≤ 5.5 V 0.7 V DD VDD V 2.2 V ≤ VDD < 2.7 V 0.9 VDD VDD V 2.7 V ≤ V DD ≤ 5.5 V 0.8 V DD VDD V 0.9 VDD VDD V Pull-up resistor 2.7 V ≤ V DD ≤ 5.5 V 0.7 V DD VDD V provided 2.2 V ≤ VDD < 2.7 V 0.9 VDD VDD V 2.7 V ≤ V DD ≤ 5.5 V 0.7 V DD 13 V 2.2 V ≤ VDD < 2.7 V 0.9 VDD 13 V VDD – 0.1 VDD V 0 0.3 V DD V N-ch open drain VIH4 X1, XT1 VIL1 Ports 2, 3, 4, 5 VIL2 Ports 0, 1, 6, 7, RESET VIL3 X1, XT1 High-level output voltage VOH SCK, SO, ports 0, 2, 3, 6, 7, BP0 to 7 IOH = –1 mA Low-level output VOL1 SCK, SO, ports 0, 2, 3, 4, IOL = 15 mA 5, 6, 7, BP0 to 7 VDD = 4.5 to 5.5 V Low-level input voltage voltage TYP. 2.2 V ≤ VDD < 2.7 V Ports 0, 1, 6, 7, RESET Ports 4, 5 MIN. 2.7 V ≤ V DD ≤ 5.5 V 2.2 V ≤ VDD < 2.7 V 0 0.1 VDD V 2.7 V ≤ V DD ≤ 5.5 V 0 0.2 V DD V 2.2 V ≤ VDD < 2.7 V 0 0.1 VDD V 0 0.1 V VDD – 0.5 V 0.2 IOL = 1.6 mA VOL2 SB0, 1 ILIH1 VIN = V DD 2.0 V 0.4 V 0.2 VDD V Pins other than X1, XT1 3 µA X1, XT1 20 µA Ports 4, 5 (N-ch open drain) 20 µA N-ch open drain Pull-up resistor ≥ 1 kΩ High-level input leakage current ILIH2 ILIH3 VIN = 13 V Low-level input ILIL1 VIN = 0 V leakage current ILIL2 X1, XT1 ILIL3 Ports 4, 5 (N-ch open drain) Pins other than X1, XT1, ports 4 and 5 –3 µA –20 µA –3 µA When input instruction is not executed Ports 4, 5 (N-ch open drain) When input instruction is executed –30 µA VDD = 5 V –10 –27 µA VDD = 3 V –3 –8 µA 3 µA High-level output ILOH1 VOUT = VDD SCK, SO/SB0, SB1, ports 2, 3, 6, 7, ports 4, 5 (with on-chip pull-up resistor), BP0 to 7 leakage current ILOH2 VOUT = 13 V Ports 4, 5 (N-ch open drain) 20 µA Low-level output ILOL VOUT = 0 V –3 µA Internal pull-up RL1 VIN = 0 V resistor R L2 leakage current Ports 0, 1, 2, 3, 6, 7 (except P00 pin) 50 100 200 kΩ Ports 4, 5 (mask option) 15 30 60 kΩ 59 µPD753012, 753016, 753017 DC Characteristics (TA = –40 to +85 ˚C, VDD = 2.2 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. VDD V 200 kΩ LCD drive voltage VLCD 2.2 LCD divider RLCD1 50 100 resistorNote 1 RLCD2 5 10 LCD output voltage VODC IO = ±5µA VLCD0 = VLCD deviationNote 2 VLCD1 = VLCD × 2/3 (common) VLCD2 = VLCD × 1/3 LCD output voltage VODS IO = ±1µA 2.2 V ≤ VLCD ≤ VDD Unit 20 kΩ 0 ±0.2 V 0 ±0.2 V 6.0 mA deviationNote 2 (segment) Supply currentNote 3 IDD1 IDD2 IDD1 IDD2 IDD3 6.00 MHzNote 4 crystal oscillation C1 = C2 = 22 pF 4.19 MHzNote 4 crystal oscillation C1 = C2 = 22 pF VDD = 5.0 V ± 10 %Note 5 VDD = 3.0 V ± 10 0.4 1.3 mA HALT VDD = 5.0 V ± 10 % 0.72 2.1 mA mode VDD = 3.0 V ± 10 % 0.27 0.8 mA VDD = 5.0 V ± 10 %Note 5 1.5 4.0 mA VDD = 3.0 V ± 10 %Note 6 0.25 0.75 mA HALT VDD = 5.0 V ± 10 % 0.7 2.0 mA mode VDD = 3.0 V ± 10 % 0.23 0.7 mA 32.768 Low- VDD = 3.0 V ± 10 % 12 35 µA kHz Note 7 voltage VDD = 2.5 V ± 10 % 4.5 12 µA crystal modeNote 8 VDD = 3.0 V, TA = 25 ˚C 12 24 µA VDD = 3.0 V ± 10 % 6 18 µA VDD = 3.0 V, TA = 25 ˚C 6 12 µA oscillation IDD4 Low current dissipation mode Note 9 HALT Low- VDD = 3.0 V ± 10 % 8.5 25 µA mode voltage VDD = 2.5 V ± 10 % 3 9 µA modeNote 8 V DD = 3.0 V, TA = 25 ˚C 8.5 17 µA VDD = 3.0 V ± 10 % 3.5 12 µA Low power dissipation mode Note 9 IDD5 XT1 = 0 V VDD = 5.0 V ± 10 % STOP VDD = 3.0 V ± 10 % modeNote 10 Notes 1. 2. 1.9 %Note 6 V DD = 3.0 V, TA = 25 ˚C TA = 25 ˚C 3.5 7 µA 0.05 10 µA 0.02 5 µA 0.02 3 µA Either RLCD1 or RLCD2 can be selected by mask option. Voltage deviation is the difference between the ideal values (VLCDn; n = 0, 1, 2) of the segment and common outputs and the output voltage. 3. The current flowing through the internal pull-up resistor and the LCD split resistor is not included. 4. Including the case when the subsystem clock oscillates. 5. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011. 6. When the device operates in low-speed mode with PCC set to 0000. 7. When the device operates on the subsystem clock, with the system clock control register (SCC) set to 1001 and oscillation of the main system clock stopped. 8. When 0000 is assigned to the sub-oscillator control register (SOS). 9. When 0010 is assigned to the SOS. 10. When the sub-oscillator feedback resistor is not used with the SOS set to 00X1 (X: don’t care). 60 µPD753012, 753016, 753017 AC Characteristics (TA = –40 to +85 ˚C, VDD = 2.2 to 5.5 V) Parameter CPU clock cycle timeNote 1 Symbol tCY (minimum instruction execution time = 1 machine cycle) Conditions When using VDD = 2.7 to 5.5 V Operates ceramic or with main crystal When using VDD = 2.7 to 5.5 V system external clock VDD = 1.8 to 5.5 V clock MIN. TYP. MAX. Unit 0.67 64 µs 0.85 64 µs 0.67 64 µs 0.95 64 µs 125 µs TI0, TI1, TI2 input frequency fTI VDD = 2.7 to 5.5 V 0 1 MHz 0 275 kHz TI0, TI1, TI2 high-, low-level tTIH, t TIL VDD = 2.7 to 5.5 V 0.48 µs tINTH, t INTL INT0 Operates with subsystem clock widths Interrupt input high-, IM02 = 0 Notes 1. 122 1.8 µs Note 2 µs 10 µs INT1, 2, 4 10 µs KR0-7 10 µs 10 µs low-level widths RESET low-level width 114 IM02 = 1 tRSL The cycle time of the CPU clock (Φ) is tCY vs VDD determined by the oscillation frequency (with main system clock) of the connected oscillator (and exter- 70 nal clock), the system clock control 64 60 register (SCC), and processor clock control register (PCC). The figure on the right shows the sup- 6 ply voltage VDD vs. cycle time tCY char- 5 acteristics when the device operates 4 2. 2t CY or 128/fX depending on the setting of the interrupt mode register (IM0). Cycle time tCY [ µ s] with the main system clock. Operation guaranteed range 3 2 1 0.95 0.85 0.67 0.5 0 1 2 3 1.8 2.2 2.7 4 5 5.5 6 Supply voltage VDD [V] Remark The shaded portion is guaranteed only when using the external clock. 61 µPD753012, 753016, 753017 Serial transfer operation 2-wire and 3-wire serial I/O modes (SCK ··· internal clock output): (TA = –40 to +85 ˚C, VDD = 2.2 to 5.5 V) Parameter SCK cycle time SCK high-, low-level widths Symbol tKCY1 tKL1, Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tKH1 SI Note 1 setup time (vs. SCK ↑) SI Note 1hold time (vs. SCK ↑) SCK ↓ → SO Note 1 output tSIK1 tKSI1 tKSO1 delay time Notes 1. VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V RL = 1 kΩNote 2 VDD = 2.7 to 5.5 V CL = 100 pF MIN. TYP. MAX. Unit 1300 ns 3800 ns tKCY1/2–50 ns tKCY1/2–150 ns 150 ns 500 ns 400 ns 600 ns 0 250 ns 0 1000 ns Replace the parameter with SB0 or SB1 in the 2-wire serial I/O mode. RL and C L respectively indicate the load resistance and load capacitance of the SO output line. 2. 2-wire and 3-wire serial I/O modes (SCK ··· external clock input): (TA = –40 to +85 ˚C, VDD = 2.2 to 5.5 V) Parameter SCK cycle time SCK high-, low-level widths Symbol tKCY2 tKL2, Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tKH2 SI Note 1 setup time (vs. SCK ↑) SI Note 1 hold time (vs. SCK ↑) SCK ↓ → SO Note 1 output delay time Notes 1. 2. 62 tSIK2 tKSI2 tKSO2 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V RL = 1 kΩNote 2 CL = 100 pF VDD = 2.7 to 5.5 V MIN. TYP. MAX. Unit 800 ns 3200 ns 400 ns 1600 ns 100 ns 150 ns 400 ns 600 ns 0 300 ns 0 1000 ns Replace the parameter with SB0 or SB1 in the 2-wire serial I/O mode. RL and C L respectively indicate the load resistance and load capacitance of the SO output line. µPD753012, 753016, 753017 SBI mode (SCK ··· internal clock output (master)): (TA = –40 to +85 ˚C, VDD = 2.2 to 5.5 V) Parameter SCK cycle time SCK high-, low-level widths Symbol tKCY3 tKL3, Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tKH3 SB0, 1 setup time tSIK3 VDD = 2.7 to 5.5 V (vs. SCK ↑) SB0, 1 hold time (vs. SCK ↑) tKSI3 SCK ↓ → SB0, 1 output tKSO3 delay time MIN. TYP. MAX. 1300 ns 3800 ns tKCY3/2–50 ns tKCY3/2–150 ns 150 ns 500 ns t KCY3/2 RL = 1 kΩNote VDD = 2.7 to 5.5 V CL = 100 pF Unit ns 0 250 0 1000 ns ns SCK ↑ → SB0, 1 ↓ tKSB tKCY3 ns SB0, 1 ↓ → SCK ↓ tSBK tKCY3 ns SB0, 1 low-level width tSBL tKCY3 ns SB0, 1 high-level width tSBH tKCY3 ns Note RL and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines. SBI mode (SCK ··· external clock input (slave)): (TA = –40 to +85 ˚C, VDD = 2.2 to 5.5 V) Parameter SCK cycle time SCK high-, low-level widths Symbol tKCY4 tKL4, Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tKH4 SB0, 1 setup time tSIK4 VDD = 2.7 to 5.5 V (vs. SCK ↑) SB0, 1 hold time (vs. SCK ↑) tKSI4 SCK ↓ → SB0, 1 output tKSO4 delay time MIN. TYP. MAX. 800 ns 3200 ns 400 ns 1600 ns 100 ns 150 ns t KCY4/2 RL = 1 kΩNote CL = 100 pF VDD = 2.7 to 5.5 V Unit ns 0 300 0 1000 ns ns SCK ↑ → SB0, 1 ↓ tKSB tKCY4 ns SB0, 1 ↓ → SCK ↓ tSBK tKCY4 ns SB0, 1 low-level width tSBL tKCY4 ns SB0, 1 high-level width tSBH tKCY4 ns Note RL and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines. 63 µPD753012, 753016, 753017 AC timing test points (except X1 and XT1 inputs) VIH (MIN.) VIH (MIN.) VIL (MAX.) VIL (MAX.) VOH (MIN.) VOH (MIN.) VOL (MAX.) VOL (MAX.) Clock timing 1/fX tXL tXH VDD – 0.1 V X1 input 0.1 V 1/fXT tXTL tXTH VDD – 0.1 V XT1 input 0.1 V TI0, TI1, TI2 timing 1/fTI tTIL TI0, TI1, TI2 64 tTIH µPD753012, 753016, 753017 Serial transfer timing 3-wire serial I/O mode tKCY1 tKL1 tKH1 SCK tSIK1 tKSI1 Input data SI tKSO1 Output data SO 2-wire serial I/O mode tKCY2 tKL2 tKH2 SCK tSIK2 tKSI2 SB0, 1 tKSO2 65 µPD753012, 753016, 753017 Serial transfer timing Bus release signal transfer tKCY3, 4 tKL3, 4 tKH3, 4 SCK tKSB tSBL tSBH tSIK3, 4 tSBK SB0, 1 tKSO3, 4 Command signal transfer tKCY3, 4 tKL3, 4 tKH3, 4 SCK tKSB tSIK3, 4 tSBK SB0, 1 tKSO3, 4 Interrupt input timing tINTL tINTH INT0, 1, 2, 4 KR0-7 RESET input timing tRSL RESET 66 tKSI3, 4 tKSI3, 4 µPD753012, 753016, 753017 Data retention characteristics of data memory in STOP mode and at low supply voltage (TA = –40 to +85 ˚C) Parameter Symbol Release signal setup time tSREL Oscillation stabilization tWAIT Conditions TYP. MAX. Unit µs 0 wait time Note 1 Notes 1. MIN. Released by RESET Note 2 ms Released by interrupt request Note 3 ms The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable operation when oscillation is started. 2. Either 217/fX or 2 15/fX can be selected by mask option. 3. Set by the basic interval timer mode register (BTM). (Refer to the table below.) BTM3 BTM2 BTM1 Wait Time BTM0 fx = 4.19 MHz f x = 6.0 MHz – 0 0 0 220/f x 2 20/f x – 0 1 1 217/f x (approx. 31.3 ms) 2 17/f x (approx. 21.8 ms) – 1 0 1 215/f x (approx. 7.82 ms) 2 15/f x (approx. 5.46 ms) – 1 1 1 213/f x (approx. 1.95 ms) 2 13/f x (approx. 1.37 ms) (approx. 250 ms) (approx. 175 ms) Data retention timing (when STOP mode released by RESET) Internal reset operation Oscillation stabilization wait time STOP mode Operation mode Data retention mode VDD tSREL STOP instruction execution RESET tWAIT Data retention timing (standby release signal: when STOP mode released by interrupt signal) Oscillation stabilization wait time STOP mode Operation mode Data retention mode VDDDR VDD tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 67 µPD753012, 753016, 753017 13 . PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14x14) A B 60 61 41 40 detail of lead end C D S R Q 21 20 80 1 F J G I H M K P M N L NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 17.2±0.4 0.677±0.016 B 14.0±0.2 0.551 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 17.2±0.4 0.677±0.016 F 0.825 0.032 G 0.825 0.032 H 0.30±0.10 0.012 +0.004 –0.005 I 0.13 0.005 J 0.65 (T.P.) 0.026 (T.P.) K 1.6±0.2 L 0.8±0.2 M 0.15 +0.10 –0.05 0.063±0.008 0.031 +0.009 –0.008 0.006 +0.004 –0.003 N 0.10 0.004 P 2.7±0.1 0.106 +0.005 –0.004 Q 0.1±0.1 0.004±0.004 R 5°±5° 5°±5° S 3.0 MAX. 0.119 MAX. S80GC-65-3B9-5 68 µPD753012, 753016, 753017 80 PIN PLASTIC TQFP (FINE PITCH) (12×12) A B 60 41 61 40 detail of lead end C D S Q R 21 80 1 20 F G H I M J K P M N NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. L ITEM MILLIMETERS INCHES A 14.00±0.20 0.551±0.008 B 12.00±0.20 0.472 +0.009 –0.008 C 12.00±0.20 0.472 +0.009 –0.008 D F 14.00±0.20 1.25 0.551±0.008 0.049 G 1.25 0.049 H 0.22 +0.05 –0.04 0.009±0.002 I 0.10 0.004 J 0.50 (T.P.) 0.020 (T.P.) K 1.00±0.20 0.039 +0.009 –0.008 L 0.50±0.20 0.020 +0.008 –0.009 M 0.145 +0.055 –0.045 0.006±0.002 N 0.10 0.004 P 1.05 0.041 Q 0.10±0.05 0.004±0.002 R 5°±5° 5°±5° S 1.27 MAX. 0.050 MAX. P80GK-50-BE9-5 69 µPD753012, 753016, 753017 14. RECOMMENDED SOLDERING CONDITIONS Solder the µPD753017 under the following recommended conditions. For the details on the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For the soldering methods and conditions other than those recommended, consult NEC. Table 14-1. Soldering Conditions of Surface Mount Type (1) µPD753012GC-XXX-3B9: 80-pin plastic QFP (14 × 14 mm) µPD753016GC-XXX-3B9: 80-pin plastic QFP (14 × 14 mm) µPD753017GC-XXX-3B9: 80-pin plastic QFP (14 × 14 mm) Soldering Method Soldering Conditions Symbol of Recommended Condition Infrared reflow Package peak temperature: 235 ˚C, Time: 30 seconds max. (210 ˚C min.), Number of times: 3 max. IR35-00-3 VPS Package peak temperature: 215 ˚C, Time: 40 seconds max. (200 ˚C min.), Number of times: 3 max. VP15-00-3 Wave soldering Solder bath temperature: 260 ˚C max., Time: 10 seconds max., Number of times: 1 Preheating temperature: 120 ˚C max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300 ˚C max., Time: 3 seconds max. (per side of device) – Caution Do not use two or more soldering methods in combination (except partial heating). 70 µPD753012, 753016, 753017 (2) µPD753012GK-XXX-BE9: 80-pin plastic TQFP (fine pitch) (12 × 12 mm) µPD753016GK-XXX-BE9: 80-pin plastic TQFP (fine pitch) (12 × 12 mm) µPD753017GK-XXX-BE9: 80-pin plastic TQFP (fine pitch) (12 × 12 mm) Soldering Method Infrared reflow Symbol of Recommended Condition Soldering Conditions Package peak temperature: 235 ˚C, Time: 30 seconds max. (210 ˚C min.), Number of times: 2 max., Number of days: 7Note (After that, prebaking is necessary at 125 ˚C for 10 hours.) IR35-107-2 <Precaution> Products other than those packed in heat-resistant trays (such as those packed in a magazine, taping, or non-heat-resistant tray) cannot be baked while they are in their packaging. VPS Package peak temperature: 215 ˚C, Time: 40 seconds max. (200 ˚C min.), Number of times: 2 max., Number of days: 7Note (After that, prebaking is necessary at 125 ˚C for 10 hours.) VP15-107-2 <Precaution> Products other than those packed in heat-resistant trays (such as those packed in a magazine, taping, or non-heat-resistant tray) cannot be baked while they are in their packaging. Pin partial heating Note Pin temperature: 300 ˚C max., Time: 3 seconds max. (per side of device) The number of days for storage after the dry pack has been opened. – The storing conditions are 25 ˚C, 65% RH max. Caution Do not use two or more soldering methods in combination (except partial heating). 71 µPD753012, 753016, 753017 APPENDIX A µPD75316B, 753017 AND 75P3018 FUNCTION LIST Parameter Program memory µPD75316B µPD753017 µPD75P3018 Mask ROM 0000H-3F7FH (16256 × 8 bits) Mask ROM 0000H-5FFFH (24576 × 8 bits) One-time PROM 0000H-7FFFH (32768 × 8 bits) Data memory 000H-3FFH (1024 × 4 bits) CPU Instruction execution time Pin connection Stack Instruction Standard CPU 75XL CPU When main system clock is selected 0.95, 1.91, 15.3 µs (at 4.19 MHz operation) • 0.95, 1.91, 3.81, 15.3 µs (at 4.19 MHz operation) • 0.67, 1.33, 2.67, 10.7 µs (at 6.0 MHz operation) When subsystem clock is selected 122 µs (32.768 kHz operation) 44 P12/INT2 P12/INT2/TI1/TI2 47 P21 P21/PTO1 48 P22/PCL P22/PCL/PTO2 50-53 P30-P33 P30/MD0-P33/MD3 57 IC VPP SBS register None SBS.3 = 1: Mk I mode selection SBS.3 = 0: Mk II mode selection Stack area 000H-0FFH n00H-nFFH (n = 0-3) Subroutine call instruction stack operation 2-byte stack Mk I mode: 2-byte stack Mk II mode: 3-byte stack BRA !addr1 CALLA !addr1 Unavailable Mk I mode: unavailable Mk II mode: available MOVT XA, @BCDE MOVT XA, @BCXA BR BCDE BR BCXA Timer 72 Available CALL !addr 3 machine cycles Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles CALLF !faddr 2 machine cycles Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles 3 channels • Basic interval timer: 1 channel • 8-bit timer/event counter: 1 channel • Watch timer: 1 channel 5 channels • Basic interval timer/watchdog timer: 1 channel • 8-bit timer/event counter: 3 channels (can be used as 16-bit timer/event counter, carrier generator, or timer with gate) • Watch timer: 1 channel µPD753012, 753016, 753017 µPD75316B Parameter µPD753017 µPD75P3018 Clock output (PCL) Φ, 524, 262, 65.5 kHz (Main system clock: at 4.19 MHz operation) • Φ, 524, 262, 65.5 kHz (Main system clock: at 4.19 MHz operation) • Φ, 750, 375, 93.8 kHz (Main system clock: at 6.0 MHz operation) BUZ output 2 kHz (Main system clock: at 4.19 MHz operation) • 2, 4, 32 kHz (Main system clock: at 4.19 MHz operation or subsystem clock: at 32.768 kHz operation) • 2.93, 5.86, 46.9 kHz (Main system clock: at 6.0 MHz operation) Serial interface 3 modes are available • 3-wire serial I/O mode ... MSB/LSB can be selected for transfer top bit • 2-wire serial I/O mode • SBI mode SOS register Feedback resistor cut flag (SOS.0) None Provided Sub-oscillator current cut flag (SOS.1) None Provided Register bank selection register (RBS) None Yes Standby release by INT0 No Yes Vectored interrupt External: 3, internal: 3 External: 3, internal: 5 Supply voltage VDD = 2.0 to 6.0 V VDD = 2.2 to 5.5 V Operation ambient temperature TA = –40 to +85˚C Package • 80-pin plastic TQFP (fine pitch) (12 × 12 mm) • 80-pin plastic QFP (14 × 14 mm) 73 µPD753012, 753016, 753017 APPENDIX B DEVELOPMENT TOOLS The following development tools are provided for system development using the µPD753017. The 75XL series uses a common relocatable assembler, in combination with a device file matching each machine. Language processor RA75X relocatable assembler OS PC-9800 series IBM PC/ATTM and compatible machines Distribution media MS-DOSTM 3.5-inch 2HD µS5A13RA75X Ver. 3.30 to 5-inch 2HD µS5A10RA75X Refer to 3.5-inch 2HC µS7B13RA75X OS for IBM PC 5-inch 2HC µS7B10RA75X Ver. 6.2 Device file Note PC-9800 series IBM PC/AT and compatible machines Distribution media MS-DOSTM 3.5-inch 2HD µS5A13DF753017 Ver. 3.30 to 5-inch 2HD µS5A10DF753017 Refer to 3.5-inch 2HC µS7B13DF753017 OS for IBM PC 5-inch 2HC µS7B10DF753017 Ver. 6.2 Note Ver. 5.00 and later have the task swap function, but cannot be used for this software. Remark The operation of the assembler and device file is guaranteed only on the above host machines and OSs. 74 Part Number (product name) Host Machine OS Note Part Number (product name) Host Machine µPD753012, 753016, 753017 PROM write tools Hardware PG-1500 PA-75P316BGC PG-1500 is a PROM programmer which enables you to program single chip microcomputers containing PROM by stand-alone or host machine operation by connecting an attached board and optional programmer adapter to PG-1500. It also enables you to program typical PROM devices of 256K bits to 4M bits. PROM programmer adapter for µPD75P3018GC. Connect the programmer adapter to PG1500 for use. Software PA-75P316BGK PROM programmer adapter for µPD75P3018GK. Connect the programmer adapter to PG1500 for use. PG-1500 controller PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500 is controlled on the host machine. Host machine OS PC-9800 series Distribution media Part number (product name) 3.5-inch 2HD µS5A13PG1500 5-inch 2HD µS5A10PG1500 Refer to 3.5-inch 2HC µS7B13PG1500 OS for IBM PC 5-inch 2HC µS7B10PG1500 MS-DOS Ver. 3.30 to Ver. 6.2Note IBM PC/AT and compatible machines Note Ver.5.00 and later have the task swap function, but it cannot be used for this software. Remark The operation of the PG-1500 controller is guaranteed only on the above host machines and OSs. 75 µPD753012, 753016, 753017 Debugging tool The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the µPD753017. The system configurations are described as follows. Hardware IE-75000-RNote1 In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X series and 75XL series. When developing a µPD753017 subseries, the emulation board IE-75300-R-EM and emulation probe that are sold separately must be used with the IE-75000-R. By connecting with the host machine and the PROM programmer, efficient debugging can be made. It contains the emulation board IE-75000-R-EM which is connected. IE-75001-R In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X series and 75XL series. When developing a µPD753017 sub-series, the emulation board IE-75300-R-EM and emulation probe which are sold separately must be used with the IE-75001-R. It can debug the system efficiently by connecting the host machine and PROM programmer. IE-75300-R-EM Emulation board for evaluating the application systems that use the µPD753017 subseries. It must be used with the IE-75000-R or IE-75001-R. EP-753017GC-R Emulation probe for the µPD753017GC. It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the 80-pin conversion socket EV-9200GC-80 which facilitates connection to a target system. EV-9200GC-80 EP-753017GK-R TGK-080SDWNote 2 Software IE control program Emulation probe for the µPD753017GK. It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the 80-pin conversion adapter TGK-080SDW which facilitates connection to a target system. Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix I/F and controls the above hardware on a host machine. Host machine OS PC-9800 series Distribution media Part number (product name) 3.5-inch 2HD µS5A13IE75X 5-inch 2HD µS5A10IE75X Refer to 3.5-inch 2HC µS7B13IE75X OS for IBM PC 5-inch 2HC µS7B10IE75X MS-DOS Ver. 3.30 to Ver. 6.2Note 3 IBM PC/AT and its compatible machines Notes 1. 2. Maintenance parts This is a product of Tokyo Eletech Corp. (Tokyo 03-5295-1661) When purchasing this product, consult your NEC distributor. 3. Ver.5.00 and later have the task swap function, but it cannot be used for this software. Remark The operation of the IE control program is guaranteed only on the above host machines and OSs. 76 µPD753012, 753016, 753017 OS for IBM PC The following IBM PC OS’s are supported. OS Version PC DOS TM Ver. 3.1 to Ver. 6.3 J6.1/V Note to J6.3/V Note MS-DOS Ver. 5.0 to Ver. 6.22 5.0/V Note to 6.2/V Note IBM DOS TM J5.02/V Note Note Only English version is supported. Caution Ver. 5.0 and later have the task swap function, but it cannot be used for this software. 77 µPD753012, 753016, 753017 APPENDIX C RELATED DOCUMENTS Some of the following related documents are preliminary. Device Related Documents Document No. Document Name Japanese English µPD753012, 753016, 753017 Data Sheet U10140J U10140E (This manual) µPD75P3018 Data Sheet U10956J U10956E µPD753017 User’s Manual U11282J U11282E µPD753017 Instruction IEM-5598 – 75XL Series Selection Guide U10453J U10453E Development Tool Related Documents Document No. Document Name IE-75000 R/IE-75001-R User’s Manual Hardware English EEU-846 EEU-1416 IE-75300-R-EM User’s Manual U11354J U11354E EP-753017GC/GK-R User’s Manual EEU-967 EEU-1494 PG-1500 User’s Manual Software Japanese U11940J U11940E U12622J EEU-1346 Language U12385J EEU-1363 PC-9800 Series (MS-DOS) Base EEU-704 EEU-1291 IBM PC Series (PC DOS) Base EEU-5008 U10540E RA75X Assembler Package Operation User’s Manual PG-1500 Controller User’s Manual Other Documents Document No. Document Name Japanese IC Package Manual English C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892J C11892E Semiconductor Devices Quality Guarantee Guide C11893J MEI-1202 Guide for Products Related to Microcomputer : Other Companies U11416J – Caution The above related documents are subject to change without notice. For design purpose, etc., be sure to use the latest documents. 78 µPD753012, 753016, 753017 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 79 µPD753012, 753016, 753017 MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT and PC DOS are trademarks of IBM Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 2