NEC UPD75068GB

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75064, 75066, 75068,
75064(A), 75066(A), 75068(A)
4-BIT SINGLE-CHIP MICROCOMPUTER
The µPD75068 is a member of the 75X series of 4-bit single-chip microcomputers.
The minimum instruction execution time of the µPD75068's CPU is 0.95 µs. In addition to this high-speed
capability, the chip contains an A /D converter and furnishes high-performance functions such as the serial
bus interface (SBI) function compliant with the NEC standard format, providing powerful features and high
cost performance. The µ PD75068(A) is a high-reliability version of the µPD75068.
NEC also provides PROM versions suitable for small-scale production or evaluation samples in system
development. The µPD75P068 is the PROM version for the µPD75064, 75066, 75068, and the µPD75P068(A)
is that for the µPD75064(A), 75066(A), 75068(A).
The detailed function descriptions are described in the document below. Please make sure to read this
document before starting design.
µPD75068 User's Manual: IEU-1366
FEATURES
• Variable instruction execution time advantageous to high-speed operation and power-saving:
•
0.95 µs, 1.91 µs, or 15.3 µs (at 4.19 MHz with the main system clock selected)
•
122 µ s (at 32.768 kHz with the subsystem clock selected)
• A /D converter (8-bit resolution, successive approximation): 8 channels
•
•
•
•
•
•
Capable of low-voltage operation: VDD = 2.7 to 6.0 V
Timer function: 3 channels
On-chip NEC standard serial bus interface (SBI)
Very low-power watch operation enabled (5 µA TYP. at 3 V)
Pull-up resistor option allowed for 27 I/O lines
The µPD75P068 and 75P068(A) (PROM versions) available: Capable of low-voltage operation (VDD = 2.7 to
6.0 V)
APPLICATIONS
•
µPD75064, 75066, 75068
Home electronic appliances, air conditioners, cameras, and electronic measuring instruments
•
µPD75064(A), 75066(A), 75068(A)
★
Automotive electronics
The information in this document is subject to change without notice.
Document No. IC-3140B
( O.D. No. IC-8629B)
Date Published December 1994 P
Printed in Japan
The mark ★ shows revised points.
NEC CORPORATION 1993
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
The µPD75064, 75066, 75068 and µPD75064(A), 75066(A), 75068(A) differ only in their quality grade.
Unless otherwise specified, this data sheet describes the µPD75068 as the representative product.
For products with the suffix (A) attached, please make the following substitutions when reading:
µPD75064 —> µ PD75064(A)
µPD75066 —> µ PD75066(A)
µPD75068 —> µ PD75068(A)
ORDERING INFORMATION
Part number
Package
µPD75064CU-xxx
µPD75064GB-xxx-3B4
µPD75066CU-xxx
µPD75066GB-xxx-3B4
µPD75068CU-xxx
µPD75068GB-xxx-3B4
µPD75064CU(A)-xxx
µPD75064GB(A)-xxx-3B4
µPD75066CU(A)-xxx
µPD75066GB(A)-xxx-3B4
µPD75068CU(A)-xxx
µPD75068GB(A)-xxx-3B4
★
★
★
★
★
★
42-pin
44-pin
42-pin
44-pin
42-pin
44-pin
42-pin
44-pin
42-pin
44-pin
42-pin
44-pin
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
shrink DIP (600 mil)
QFP (10x10 mm)
shrink DIP (600 mil)
QFP (10x10 mm)
shrink DIP (600 mil)
QFP (10x10 mm)
shrink DIP (600 mil)
QFP (10x10 mm)
shrink DIP (600 mil)
QFP (10x10 mm)
shrink DIP (600 mil)
QFP (10x10 mm)
Quality Grade
Standard
Standard
Standard
Standard
Standard
Standard
Special
Special
Special
Special
Special
Special
Remark xxx : ROM code suffix
Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published
by NEC Corporation to know the specification of quality grade on the devices and its recommended
applications.
DIFFERENCE BETWEEN µPD7506x SUBSERIES AND µPD7506x(A) SUBSERIES
★
µPD75064
µPD75064(A)
µPD75066
µPD75066(A)
Parameter
µPD75068
µPD75068(A)
Quality grade
Standard
Special
Part number
2
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
FUNCTION OVERVIEW
Item
Function
Instruction execution time
• Main system clock : 0.95 µs, 1.91 µs, 15.3 µs (at 4.19 MHz)
• Subsystem clock : 122 µs (at 32.768 kHz)
Internal memory
ROM
• µ PD75064 : 4096 × 8 bits
• µ PD75066 : 6016 × 8 bits
• µ PD75068 : 8064 × 8 bits
RAM
512 × 4 bits
General register
I/O port
• When operating in 4 bits:
• When operating in 8 bits:
32
12
8
4
CMOS input
Of these, seven with software-specifiable on-chip
pull-up resistors
12
CMOS I/O
Software-specifiable on-chip pull-up resistors
Four pins can directly drive LEDs.
8
N-ch open-drain I/O
Breakdown voltage: 10 V
Mask-option-specifiable on-chip pull-up resistors
Can directly drive LEDs.
• Timer/event counter
• Basic interval timer : Applicable to watchdog timer
• Watch timer : Capable of buzzer output
Timer
3 chs.
Serial interface
• 3-wire serial I/O mode
• 2-wire serial I/O mode
• SBI mode
Bit sequencial buffer
16 bits
Clock output function
Φ , fx /23, f x /24, f x/2 6 (Main system clock: at 4.19 MHz operation)
A/D converter
• 8-bit resolution x 8 channels
• Low-power operation possible : VDD = 2.7 to 6.0 V
Vectored interrupt
External : 3 , Internal : 3
Test input
External : 1,
System clock oscillator
• Ceramic/crystal oscillator for main system clock
• Crystal oscillator for subsystem clock
Standby function
STOP / HALT mode
Operating ambient
–40 to +85 °C
Internal : 1
temperature
Operating supply
2.7 to 6.0 V
voltage
Package
• 42-pin plastic shrink DIP (600 mil)
• 44-pin plastic QFP (10 x 10 mm)
3
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ··························································································
5
2. BLOCK DIAGRAM ························································································································
7
3. PIN FUNCTIONS ··························································································································
8
3.1
Port Pins ···············································································································································
8
3.2
Non-Port Pins ·······································································································································
9
3.3
Pin Input/Output Circuits···················································································································
10
3.4
Mask Option Selection ························································································································
12
3.5
Handling Unused Pins ·························································································································
13
4. MEMORY CONFIGURATION ·····································································································
14
5. PERIPHERAL HARDWARE FUNCTIONS ··················································································· 18
5.1
Ports ······················································································································································
18
5.2
Clock Generator ···································································································································
19
5.3
Clock Output Circuit ····························································································································
20
5.4
Basic Interval Timer ·····························································································································
21
5.5
Watch Timer ·········································································································································
22
5.6
Timer/Event Counter ···························································································································
23
5.7
Serial Interface ·····································································································································
24
5.8
A/D Converter ······································································································································
25
5.9
Bit Sequential Buffer ···························································································································
26
6. INTERRUPT FUNCTIONS ···········································································································
27
7. STANDBY FUNCTION ················································································································
29
8. RESET OPERATION ····················································································································
30
9. INSTRUCTION SET ····················································································································
32
10. ELECTRICAL SPECIFICATIONS ·································································································
40
11. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) ··························································· 54
12. PACKAGE DRAWINGS ···············································································································
60
13. RECOMMENDED SOLDERING CONDITIONS ··········································································· 62
APPENDIX A.
DEVELOPMENT TOOLS ························································································
64
APPENDIX B.
RELATED DOCUMENTS ························································································
65
4
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
1. PIN CONFIGURATION (TOP VIEW)
• 42-pin plastic shrink DIP
1
42
VSS
XT2
2
41
P40
RESET
3
40
P41
X1
4
39
P42
X2
5
38
P43
P33
6
37
P50
P32
7
36
P51
P31
8
35
P52
P30
9
34
P53
AVSS
10
33
P00/INT4
AN7/KR3/P63
11
32
P01/SCK
AN6/KR2/P62
12
31
P02/SO/SB0
AN5/KR1/P61
13
30
P03/SI/SB1
AN4/KR0/P60
14
29
P10/INT0
AN3/P113
15
28
P11/INT1
AN2/P112
16
27
P12/INT2
AN1/P111
17
26
P13/TI0
AN0/P110
18
25
P20/PTO0
AVREF
19
24
P21
IC
20
23
P22/PCL
VDD
21
22
P23/BUZ
µ PD75064CU-×××
µ PD75066CU-×××
µ PD75068CU-×××
XT1
NC
P111/AN1
P110/AN0
AVREF
IC
VDD
P23/BUZ
P22/PCL
P21
P20/PTO0
P13/TI0
• 44-pin plastic QFP
44 43 42 41 40 39 38 37 36 35 34
1
33
P112/AN2
INT1/P11
2
32
P113/AN3
INT0/P10
3
31
P60/KR0/AN4
SB1/SI/P03
4
30
P61/KR1/AN5
SB0/SO/P02
5
29
P62/KR2/AN6
SCK /P01
6
28
P63/KR3/AN7
INT4/P00
7
27
AVSS
P53
8
26
P30
P52
9
25
P31
P51
10
24
P32
P50
11
12 13 14 15 16 17 18 19 20 21 22
23
P33
X1
RESET
XT2
XT1
VSS
P40
P41
P42
NC
P43
µ PD75064GB-×××-3B4
µ PD75066GB-×××-3B4
µ PD75068GB-×××-3B4
X2
INT2/P12
IC : Internally Connected (This pin should be directly connected to VDD)
5
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
PIN IDENTIFICATIONS
6
P00 - 03
:
Port 0
P10 - 13
:
Port 1
P20 - 23
:
Port 2
P30 - 33
:
Port 3
P40 - 43
:
Port 4
P50 - 53
:
Port 5
P60 - 63
:
Port 6
P110 - 113 :
Port 11
KR0 - 3
Key Return
:
SCK
:
Serial Clock
SI
:
Serial Input
SO
:
Serial Output
SB0, 1
:
Serial Bus 0, 1
RESET
:
Reset Input
TI0
:
Timer Input 0
PTO0
:
Programmable Timer Output 0
BUZ
:
Buzzer Clock
PCL
:
Programmable Clock
INT0, 1, 4 :
External Vectored Interrupt 0, 1, 4
INT2
:
External Test Input 2
X1, 2
:
Main System Clock Oscillation 1, 2
XT1, 2
:
Subsystem Clock Oscillation 1, 2
AN0 - 7
:
Analog Input 0 - 7
AV REF
:
Analog Reference
AV SS
:
Analog V SS
VDD
:
Positive Power Supply
VSS
:
Ground
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
2.
BLOCK DIAGRAM
BIT SEQ.
BUFFER
BASIC
INTERVAL
TIMER
INTBT
TIMER/
COUNTER
#0
INTT0
TI0/P13
PTO0/P20
PROGRAM Note
COUNTER
PORT 0
4
P00 - P03
PORT 1
4
P10 - P13
PORT 2
4
P20 - P23
PORT 3
4
P30 - P33
PORT 4
4
P40 - P43
PORT 5
4
P50 - P53
PORT 6
4
P60 - P63
PORT 11
4
P110 - P113
SP
CY
ALU
BANK
SI/SB1/P03
SO/SB0/P02
SCK/P01
SERIAL
INTERFACE
INTCSI
INT0/P10
INT1/P11
INT2/P12
INT4/P00
KR0 - KR3
/ P60 - P63
INTERRUPT
CONTROL
4
GENERAL
REGISTER
ROM
PROGRAM
MEMORY
4096 × 8 BITS
( µ PD75064)
6016 × 8 BITS
( µ PD75066)
8064 × 8 BITS
( µ PD75068)
DECODE
AND
CONTROL
RAM
DATA
MEMORY
512 × 4 BITS
WATCH
TIMER
BUZ/P23
INTW
AVREF
AVSS
AN0 - AN3
/ P110 - P113
AN4 - AN7
/ P60 - P63
A/D
CONVERTER
fX /2N
8
CPU CLOCK
Φ
CLOCK
OUTPUT
CONTROL
CLOCK
DIVIDER
PCL/P22
CLOCK GENERATOR
SUB
MAIN
XT1 XT2
X1 X2
STAND BY
CONTROL
VDD VSS RESET
Note
The µ PD75064 uses the program counter of a 12-bit configuration, the µPD75066 and µPD75068
use that of a 13-bit configuration.
7
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
3.
PIN FUNCTIONS
3.1
Port Pins
Pin name
Input/
output
Shared
with
P00
Input
INT4
P01
I/O
SCK
P02
I/O
SO/SB0
F -B
P03
I/O
SI/SB1
M -C
P10
Input
INT0
With noise elimination function
P11
INT1
P12
INT2
4-bit input port (PORT1).
Pull-up resistors can be provided by software in units of 4 bits.
P13
TI0
P20
I/O
PTO0
P21
–
P22
PCL
P23
BUZ
P30Note 2
I/O
–
P31Note 2
–
P32Note 2
–
P33Note 2
–
Function
4-bit input port (PORT0).
For P01 to P03, pull-up resistors can be
provided by software in units of 3 bits.
4-bit I/O port (PORT2).
Pull-up resistors can be provided by software in units of 4 bits.
Programmable 4-bit I/O port (PORT3).
I/O can be specified bit by bit. Pull-up
resistors can be provided by software in
units of 4 bits.
When reset
I/O circuit
type Note 1
×
Input
B
F -A
×
Input
B -C
×
Input
E-B
×
Input
E-B
P43Note 2
I/O
–
N-ch open-drain 4-bit I/O port (PORT4).
A pull-up resistor can be provided for
each bit (mask option). Breakdown voltage is 10 V in open-drain mode.
High level
(when pullup resistors
are provided)
or high
impedance
M
P50 - P53Note 2
I/O
–
N-ch open-drain 4-bit I/O port (PORT5).
A pull-up resistor can be provided for
each bit (mask option). Breakdown voltage is 10 V in open-drain mode.
High level
(when pullup resistors
are provided)
or high
impedance
M
P60
I/O
KR0/AN4
Programmable 4-bit I/O port (PORT6).
I/O can be specified bit by bit. Pull-up
resistors can be provided by software in
units of 4 bits.
Input
Y -D
Input
Y-A
P40 -
P61
KR1/AN5
P62
KR2/AN6
P63
KR3/AN7
P110
Input
AN0
P111
AN1
P112
AN2
P113
AN3
4-bit input port (PORT11).
Notes 1. The circle (
) indicates the Schmitt trigger input.
2. Can directly drive LEDs.
8
8-bit
I/O
×
×
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
3.2
Non-Port Pins
Pin name
Input/
output
Shared
with
TI0
Input
PTO0
Function
When reset
I/O circuit
typeNote 1
P13
Input for receiving external event pulse signal for
timer/event counter
–
B -C
I/O
P20
Timer/event counter output
Input
E-B
PCL
I/O
P22
Clock output
Input
E-B
BUZ
I/O
P23
Output frequency selectable
(for buzzer output or system clock trimming)
Input
E-B
SCK
I/O
P01
Serial clock I/O
Input
F -A
SO/SB0
I/O
P02
Serial data output
Serial bus I/O
Input
F -B
SI/SB1
I/O
P03
Serial data input
Serial bus I/O
Input
M -C
INT4
Input
P00
Edge-detective vectored interrupt input
(both rising and falling edges enabled)
–
B
INT0
Input
P10
Edge-detective vectored interrupt input
(detection edge selectable)
–
B -C
–
B -C
Input
Y -D
Input
Y-A
P11
INT1
Edge-detective testable input
(rising edge detection)
Note 2
Note 3
INT2
Input
KR0 - KR3
I/O
AN0 - AN3
Input
AN4 - AN7
I/O
P60 - P63/
KR0 - KR3
AVREF
Input
–
Reference voltage input
–
Z
AV SS
–
–
GND potential
–
Z
X1, X2
Input
–
Crystal/ceramic connection for main system clock
generation. When external clock signal is used,
the signal should be applied to X1, and its reverse
phase signal to X2.
–
–
XT1, XT2
Input
–
Crystal connection for subsystem clock generation. When external clock signal is used, the
signal should be applied to XT1, and its reverse
phase signal to XT2. XT1 can be used as a 1-bit
input (test).
–
–
RESET
Input
–
System reset input
–
B
IC
–
–
Internally connected.
–
–
P12
Note 3
P60 - P63/ Parallel falling edge detection testable input
AN4 - AN7
P110 - P113 For A /D converter only
8-bit analog input
Y -D
(Connect this pin directly to VDD)
VDD
–
–
Positive power supply
–
–
VSS
–
–
GND potential
–
–
Notes 1. The circle (
) indicates the Schmitt trigger input.
2. Clock synchronous
3. Asynchronous
9
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
3.3
Pin Input/Output Circuits
The input/output circuit of each µPD75068 pin is shown below in a simplified manner.
(1/3)
Type A (For type E-B)
Type D (For type E-B, F-A)
VDD
VDD
Data
P-ch
P-ch
OUT
IN
N-ch
CMOS input buffer
Type B
Output
disable
N-ch
Push-pull output which can be set to high impedance output
(off for both P-ch and N-ch)
Type E-B
VDD
P.U.R.
P.U.R.
enable
IN
P-ch
Data
IN/OUT
Type D
Output
disable
Type A
Schmitt trigger input with hysteresis
Type B-C
VDD
P.U.R.
P-ch
P.U.R.
enable
IN
P.U.R.: Pull-Up Resistor
10
P.U.R.: Pull-Up Resistor
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
(2/3)
Type F-A
Type M-C
VDD
VDD
P.U.R.
P.U.R.
P.U.R.
enable
P.U.R.
enable
P-ch
P-ch
IN/OUT
Data
IN/OUT
Type D
Data
Output
disable
N-ch
Output
disable
Type B
P.U.R.: Pull-Up Resistor
P.U.R.: Pull-Up Resistor
Type F-B
Type Y (For type Y-A , Y-D)
VDD
P.U.R.
VDD
P.U.R.
enable
Output
disable
(P)
P-ch
IN
VDD
P-ch
N-ch
+
Sampling C
VDD
P-ch
–
IN/OUT
Data
AVSS
Output
disable
AVSS
N-ch
Output
disable
(N)
Reference voltage
(from voltage tap of
serial resistor string)
Input
enable
P.U.R.: Pull-Up Resistor
Type M
Type Y-A
VDD
P.U.R.
enable
(Mask option)
Data
Output
disable
IN instruction
IN/OUT
N-ch
(Can
withstand
+10 V)
Type A
Input buffer
IN
Type Y
Middle-voltage input buffer
(Can withstand +10 V)
P.U.R.: Pull-Up Resistor
11
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
(3/3)
Type Y-D
Type Z
VDD
P.U.R.
P.U.R.
enable
AVREF
P-ch
Data
IN/OUT
Type D
Output
disable
Reference voltage
Type B
Type Y
AVSS
P.U.R.: Pull-Up Resistor
3.4
Mask Option Selection
The following mask options are available for selection for each pin.
Pin name
12
Mask option
P40 - P43,
P50 - P53
1
Pull-up resistor enabled
(specifiable bit by bit)
2
Pull-up resistor disabled
(specifiable bit by bit)
XT1, XT2
1
Feedback resistor enabled
(if a subsystem clock is used)
2
Feedback resistor disabled
(if a subsystem clock is not used)
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
3.5
Handling Unused Pins
Table 3-1. Handling Unused Pins
Pin
Recommended connection
P00/INT4
Connect to VSS.
P01/SCK
Connect to VSS or VDD.
P02/SO/SB0
P03/SI/SB1
P10/INT0-P12/INT2
Connect to VSS.
P13/TI0
P20/PTO0
Input state: Connect to VSS or VDD.
P21
Output state: Open
P22/PCL
P23/BUZ
P30-P33
P40-P43
P50-53
P60/KR0/AN4-P63/KR3/AN7
P110/AN0-P113/AN3
Connect to VSS or VDD.
AVREF
Connect to VSS.
AVSS
XT1
Connect to VSS or VDD.
XT2
Open
IC
Directly connect to VDD.
13
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
4.
MEMORY CONFIGURATION
• Program memory (ROM) ..... 4096 × 8 bits (0000H to 0FFFH) : µPD75064
..... 6016 × 8 bits (0000H to 177FH) : µPD75066
..... 8064 × 8 bits (0000H to 1F7FH) : µPD75068
• 0000H to 0001H : Vector table in which the program start address by reset is stored
• 0002H to 000BH : Vector table in which the program start address by interrupt is stored
• 0020H to 007FH : Table area to be referenced by GETI instruction
• Data memory
..... 512 × 4 bits (000H to 1FFH)
• Data area
• Peripheral hardware area ..... 128 × 4 bits (F80H to FFFH)
Figure 4-1. Program Memory Map
(a) µPD75064
Address
0000H
7
6
5
4
MBE
0
0
0
0
Internal reset start address (high-order 4 bits)
Internal reset start address (low-order 8 bits)
0002H
0004H
0006H
0008H
000AH
MBE
MBE
MBE
MBE
MBE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
INTBT/INT4 start address
(high-order 4 bits)
INTBT/INT4 start address
(low-order 8 bits)
INT0 start address
(high-order 4 bits)
INT0 start address
(low-order 8 bits)
INT1 start address
(high-order 4 bits)
INT1 start address
(low-order 8 bits)
INTCSI start address
(high-order 4 bits)
INTCSI start address
(low-order 8 bits)
INTT0 start address
(high-order 4 bits)
INTT0 start address
(low-order 8 bits)
0020H
GETI instruction reference table
007FH
0080H
07FFH
0800H
0FFFH
14
CALLF
! faddr
instruction
entry
address
CALL ! addr
instruction
subroutine entry
address
BR $addr
instruction
relative branch
address
(–15 to –1,
+2 to +16)
BRCB
! caddr
instruction
branch
address
Branch destination
address specified
by GETI instruction,
Subroutine entry
address
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
(b) µPD75066
Address
0000H
0002H
0004H
0006H
0008H
000AH
7
6
5
MBE
0
0
MBE
MBE
MBE
MBE
MBE
0
0
0
0
0
0
0
0
0
0
0
Internal reset start address
(high-order 5 bits)
Internal reset start address
(low-order 8 bits)
INTBT/INT4 start address
(high-order 5 bits)
INTBT/INT4 start address
(low-order 8 bits)
INT0 start address
(high-order 5 bits)
INT0 start address
(low-order 8 bits)
INT1 start address
(high-order 5 bits)
INT1 start address
(low-order 8 bits)
INTCSI start address
(high-order 5 bits)
INTCSI start address
(low-order 8 bits)
INTT0 start address
(high-order 5 bits)
INTT0 start address
(low-order 8 bits)
0020H
GETI instruction reference table
007FH
0080H
CALLF
! faddr
instruction
entry
address
CALL ! addr
instruction
subroutine entry
address
BR ! addr
instruction brach
address
BR $addr
instruction
relative branch
address
(–15 to –1,
+2 to +16)
BRCB
! caddr
instruction
branch
address
Branch destination
address specified
by GETI instruction,
Subroutine entry
address
07FFH
0800H
0FFFH
1000H
BRCB
! caddr
instruction
branch
address
177FH
15
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
(c) µPD75068
Address
0000H
0002H
0004H
0006H
0008H
000AH
7
6
5
MBE
0
0
MBE
MBE
MBE
MBE
MBE
0
0
0
0
0
0
0
0
0
0
0
Internal reset start address
(high-order 5 bits)
Internal reset start address
(low-order 8 bits)
INTBT/INT4 start address
(high-order 5 bits)
INTBT/INT4 start address
(low-order 8 bits)
INT0 start address
(high-order 5 bits)
INT0 start address
(low-order 8 bits)
INT1 start address
(high-order 5 bits)
INT1 start address
(low-order 8 bits)
INTCSI start address
(high-order 5 bits)
INTCSI start address
(low-order 8 bits)
INTT0 start address
(high-order 5 bits)
INTT0 start address
(low-order 8 bits)
0020H
GETI instruction reference table
007FH
0080H
CALLF
! faddr
instruction
entry
address
BR ! addr
instruction brach
address
BR $addr
instruction
relative branch
address
(–15 to –1,
+2 to +16)
BRCB
! caddr
instruction
branch
address
Branch destination
address specified
by GETI instruction,
Subroutine entry
address
07FFH
0800H
0FFFH
1000H
BRCB
! caddr
instruction
branch
address
1F7FH
16
CALL ! addr
instruction
subroutine entry
address
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Figure 4-2. Data Memory Map
Data memory
General 000H
register
area
007H
(8 × 4)
008H
256 × 4
Stack
area
Bank 0
Static RAM
(512 × 4)
0FFH
100H
256 × 4
Bank 1
1FFH
Not contained
F80H
Peripheral
hardware area
128 × 4
Bank 15
FFFH
17
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 Ports
The following three types of I/O port are provided:
• CMOS input ports (PORT0, 1, 11)
: 12
• CMOS input/output ports (PORT2, 3, 6)
: 12
• N-ch open-drain input/output ports (PORT4, 5) :
Total
8
32
Table 5-1. Functions of Port
Port (Symbol)
Function
Operation/features
Remarks
PORT0
PORT1
4-bit input
Can be read or tested regardless of the operation mode of
the dual function pin.
Shared with the SO/SB0, SI/SB1, SCK,
INT0-2, 4, and TI0 pins.
PORT3Note
PORT6
4-bit I/O
Can be specified for input/
output in bit units.
Port 6 is shared with pins KR0 to KR3 and
pins AN4 to AN7.
Can be specified for input/
output in 4-bit units.
Port 2 is shared with PTO0, PCL, and BUZ
pins.
PORT2
PORT4Note
PORT5Note
4-bit I/O
(N-ch open-drain,
can withstand 10 V)
Can be specified for input/
output in 4-bit units.
Ports 4 and 5 can be paired to
input/output data in 8-bit units.
Whether or not the internal pull-up
resistor is provided can be specified for
each bit by mask option.
PORT11
4-bit input
4-bit port dedicated to input
Port 11 is shared with pins AN0 to AN3.
Note
18
Can directly drive LEDs.
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
5.2
Clock Generator
The clock generator operates according to the statuses of the processor clock control register (PCC) and
the system clock control register (SCC). Two types of clock are provided: main system clock and subsystem
clock, and the instruction execution time can be changed.
• 0.95 µs / 1.91 µs / 15.3 µs (operated with main system clock at 4.19 MHz)
• 122 µs (operated with subsystem clock at 32.768 kHz)
Figure 5-1. Clock Generator Block Diagram









XT1
XT2
Subsystem
clock generator
fXT
Main system
clock generator
fX
Watch timer
• Basic interval timer (BT)
• Timer/event counter
• Serial interface
• Watch timer
• A /D converter
(successive approximation type)
• INT0 noise eliminator
• Clock output circuit
X1
X2
1/2 to 1/4096
Frequency divider
1/2 1/16
WM.3
SCC
Selector
Oscillator
disable
signal
Frequency
divider
SCC3
Selector
Internal bus
Φ
1/4
 • CPU
 • INT0 noise
 eliminator
 • Clock output
 circuit
SCC0
PCC
PCC0
PCC1
4
HALT
HALT F/F
Note
STOP Note
PCC2
S
PCC3
R
PCC2, PCC3
clear signal
STOP F/F
Q
Q
Wait release signal from BT
S
RESET signal
R
Standby release signal from
interrupt control circuit
Note Instruction execution
Remarks
1.
2.
3.
4.
5.
6.
fX = Main system clock frequency
fXT = Subsystem clock frequency
Φ = CPU clock
PCC: Processor clock control register
SCC: System clock control register
One clock cycle (tCY) at Φ is equal to one machine cycle of an instruction.
For tCY, refer to AC Characteristics in 10. ELECTRICAL SPECIFICATIONS.
19
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
5.3
Clock Output Circuit
The clock output circuit outputs clock pulses from the P22/PCL pin, and is used to supply clock pulses to
remote unit controller and peripheral LSIs.
• Clock output (PCL):
Φ,
524 kHz, 262 kHz, 65.5 kHz (fX = at 4.19 MHz)
Figure 5-2. Clock Output Circuit Configuration
From the clock
generator
Φ
Output
buffer
f X / 23
Selector
fX / 2
4
fX / 2
6
P22/PCL
PORT2.2
CLOM3
0
CLOM1 CLOM0 CLOM
P22 output
latch
Bit 2 of PMGB
Port 2 input/
output mode
specification bit
4
Internal bus
Remark Measures are taken to prevent outputting a narrow pulse when selecting clock output
enable/disable.
20
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
5.4
Basic Interval Timer
The basic interval timer has these functions:
• Interval timer operation which generates a reference timer interrupt
• Watchdog timer application which detects a program runaway
• Selection of wait time for releasing the standby mode and counting the wait time
• Reading out the count value
Figure 5-3. Basic Interval Timer Configuration
From the clock
generator
Clear signal
Clear signal
fX/25
Set
signal
7
fX/2
Basic interval timer
(8-bit frequency divider circuit)
MPX
9
BT interrupt
request flag
fX/2
12
BT
fX/2
3
BTM3
SET1 Note
BTM2
BTM1
IRQBT
Vectored
interrupt
request
signal
Wait release
signal for standby
release
BTM0
4
BTM
8
Internal bus
Note Instruction execution
21
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
5.5
Watch Timer
The µPD75068 has an on-chip 1-ch watch timer. The watch timer has the following functions:
• Sets the test flag (IRQW) with a 0.5-sec interval. The standby mode can be released by IRQW.
• The 0.5-second interval can be generated from either the main system clock or subsystem clock.
• The time interval can be made 128 times faster (3.91 ms) by selecting the fast mode. This is convenient
for program debugging, testing, etc.
• Any of the frequencies 2.048 kHz, 4.096 kHz, and 32.768 kHz can be output to the P23/BUZ pin. This
can be used for beep and system clock frequency trimming.
• The frequency divider circuit can be cleared so that a zero-second start of the watch can be made.
Figure 5-4. Watch Timer Block Diagram
fw
27

From the 
clock

generator


fX
128
(32.768 kHz)
(256 Hz: 3.91 ms)
fw
fW
(32.768 kHz)
214
Selector
INTW
IRQW
set signal
Selector
Frequency divider
fXT
(32.768 kHz)
2 Hz
0.5 sec
(4 kHz)(2 kHz)
fw
fw
23
24
Clear signal
Selector
Output buffer
P23/BUZ
WM
WM7
PORT2.3
0
WM5 WM4 WM3 WM2 WM1 WM0
8
Bit test instruction
Internal bus
Remark ( ) is for fX = 4.194304 MHz, fXT = 32.768 kHz.
22
P23 output
latch
Bit 2 of PMGB
Port 2 input/
output mode
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
5.6
Timer/Event Counter
The µPD75068 has an on-chip 1-ch timer/event counter. The timer/event counter has the following
functions:
• Programmable interval timer operation
• Outputs square-wave signal of a user-selectable frequency to the PTO0 pin
• Event counter operation
• Divides the TI0 pin input by N and outputs to the PTO0 pin (frequency divider operation)
• Supplies serial shift clock to the serial interface circuit
• Count condition read-out function.
Figure 5-5. Block Diagram of Timer / Event Counter
Internal bus
8
SET1 Note
TM0
8
8
TOE0
TMOD0
TM07 TM06 TM05 TM04 TM03 TM02 TM01 TM00
TO
enable
flag
Modulo register (8)
PORT2.0
P20
output
latch
signal
Bit 2 of PGMB
Port 2
input/
output
mode
To serial
interface
8
PORT1.3
Match
Comparator (8)
8
Input buffer
TOUT
F/F
P20/PTO0
Reset
Output
buffer
T0
P13/
TI0
INTT0
From the
clock
generator





Count register (8)
MPX
(Refer to Fig. 5-1.)
CP
Clear
signal
IRQT0
set signal
Timer operation start signal
RESET
IRQT0 clear
signal
Note Instruction execution
23
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
5.7
Serial Interface
(1) Serial interface function
The µPD75068 contains a clock synchronous 8-bit serial interface, which has four modes.
• Operation halt mode
• 3-wire serial I/O mode
• 2-wire serial I/O mode
• SBI (serial bus interface mode)
Figure 5-6. Block Diagram of Serial Interface
Internal bus
8
8
8
Slave address
register (SVA)
Address comparator
(8)
SBIC
Match
signal
CMDT
(8)
SO
SET CLR latch
D
Q
ACKT
Selector
RELT
(8)
P03/SI/SB1
Shift register (SIO)
Bit
test
Bit manipulation
BSYE
CSIM
Bit
test
ACKE
8/4
Selector
P02/SO/SB0
Busy/
acknowledge
output circuit
Bus release/
command/
acknowledge
detection circuit
RELD
CMDD
ACKD
INTCSI
P01/SCK
Serial clock
counter
P01
output
latch
Serial clock
control circuit
INTCSI
control circuit
IRQCSI
set signal
Serial clock
selector
fx/23
fx/24
fx/26
TOUT F/F
(from timer/
event counter)
External SCK
24
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
5.8
A/D Converter
The µPD75068 contains an 8-bit analog/digital (A / D) converter that has eight analog input channels
(AN0 - AN7).
The A /D converter employs the successive-approximation method.
Figure 5-7. Block Diagram of A/D Converter
Internal bus
8
0
ADM6 ADM5 ADM4
SOC
EOC
ADM1
0
ADM
8
AN0/P110
Control circuit
AN1/P111
Sample and hold circuit
AN2/P112
+
AN3/P113
Multiplexer
SA register (8)
–
AN4/KR0/P60
Comparator
AN5/KR1/P61
AN6/KR2/P62
8
AN7/KR3/P63
Tap decoder
AVREF
R/2
R
R
Series resistor string
R
R/2
AVSS
25
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
5.9
Bit Sequential Buffer: 16 Bits
The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer,
addresses and bit specifications can be sequentially updated by bit manipulation operation. Therefore, this
buffer is very useful for processing long data in bit units.
Figure 5-8. Bit Sequential Buffer Format
FC3H
Address
Bit
3
1
0
3
2
BSB3
Symbol
L register
2
FC2H
L=F
1
FC1H
0
3
BSB2
L=C L=B
2
FC0H
1
0
3
BSB1
L=8 L=7
2
1
0
BSB0
L=4 L=3
L=0
DECS L
INCS L
Remark For "pmem.@L" addressing, the specification bit is shifted according to the L register.
26
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
6.
INTERRUPT FUNCTIONS
The µPD75068 has six different interrupt sources. In addition, multiple interrupts with priority control are
possible. Two types of test sources are provided. Of these test sources, INT2 has two types of edge detection
testable inputs.
Table 6-1. Interruption Source Types
Interruption Source
INTBT
(Reference time interval signal from
basic interval timer)
INT4
(Detection of both rising edge and
falling edge is valid.)
INT0
(Selection of rising edge detection or
falling edge detection)
INT1
Interruption
OrderNote1
Vectored Interrupt Request Signal
(Vector table address)
1
VRQ1 (0002H)
OUT
2
VRQ2 (0004H)
OUT
3
VRQ3 (0006H)
IN/OUT
IN
OUT
INTCSI
(Serial data transmission completion
signal)
IN
4
VRQ4 (0008H)
INTT0
(Coincidence signal of programmable
timer/counter count register and modulo
register)
IN
5
VRQ5 (000AH)
INT2Note2
(Detection of rising edge of input to
INT2 pin or detection of falling edge of
any input to KR0 to KR3)
INTWNote2
(Signal from watch timer)
OUT
Test input signal (Set IRQ and IRQW)
IN
Notes 1. The interruption order shows the priority order of the pins when several interruption requests occur
at the same time.
2. Test source. Like the interruption source, it is influenced by the interruption enable flag. However,
vectored interrupt will not occur.
The interrupt control circuit of the µPD75068 has the following functions:
• Hardware controlled vectored interrupt function which can control whether or not to acknowledge an
interrupt based on the interrupt flag (IE×××) and interrupt master enable flag (IME)
• The interrupt start address can be set arbitrarily.
• Interrupt request flag (IRQ×××) test function (an interrupt generation can be confirmed by software)
• Standby mode release (interrupts to be released can be selected by the interrupt enable flag)
27
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Figure 6-1. Block Diagram of Interrupt Control Circuit
Internal bus
1
3
IM1
IM0
Interrupt enable flag (IExxx)
INT
BT
Both-edge
detection
circuit
INT4
/P00
INT0
/P10
Note
INT1
/P11
INT2
/P12
Edge
detection
circuit
Decoder
IRQBT
VRQn
IRQ4
IRQ1
INTCSI
IRQCSI
INTT0
IRQT0
INTW
IRQW
Selector
Priority
control
circuit
Vector
table
address
generator
IRQ2
Standby
release
signal
AN4/KR0/P60
Falling edge
detection
circuit
AN7/KR3/P63
IM2
Note Noise eliminator
28
IST0
IRQ0
Edge
detection
circuit
Rising edge
detection
circuit
IME
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
7.
STANDBY FUNCTION
The µPD75068 has two different standby modes (STOP mode and HALT mode) to reduce power dissipation
while waiting for program execution.
Table 7-1. Standby Mode Statuses
STOP mode
HALT mode
Instruction for setting
STOP instruction
HALT instruction
System clock for setting
Can be set only when operating on the
main system clock.
Can be set either with the main system
clock or the subsystem clock.
Operation
status
Clock oscillator
Only the main system clock stops its
operation.
Only the CPU clock Φ stops its operation
(oscillation continues).
Basic interval
timer
Does not operate.
Can operate only at main system clock
oscillation (IRQBT is set at reference
time intervals.).
Serial interface
Can operate only when the external SCK
input is selected for the serial clock.
Can operate only when external SCK
input is selected as the serial clock or at
main system clock oscillation.
Timer/event
counter
Can operate only when the TI0 pin input
is selected for the count clock.
Can operate only when TI0 pin input is
specified as the count clock or at main
system clock oscillation.
Watch timer
Can operate when fXT is selected as the
count clock.
Can operate.
A/D converter
Does not operate.
Can operate.Note
External
interrupt
INT1, INT2, and INT4 can operate.
Only INT0 cannot operate.
CPU
Does not operate.
Release signal
An interrupt request signal from hardware whose operation is enabled by the
interrupt enable flag or the RESET signal
input
An interrupt request signal from hardware whose operation is enabled by the
interrupt enable flag or the RESET signal
input
Note A/D converter's operation in HALT mode is possible only when the main system clock operates.
29
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
8.
RESET OPERATION
When the RESET signal is input, the µPD75068 is reset and all hardware is initialized as indicated in Table
8-1.
Figure 8-1 shows the reset operation timing.
Figure 8-1. Reset Operation by RESET Input
Wait
(Approx. 31.3 ms/4.19 MHz)
RESET input
Operation mode or
standby mode
HALT mode
Operation mode
Internal reset operation
Table 8-1. Status of All Hardware after Reset (1/2)
RESET input in standby mode
RESET input during operation
µPD75064
Contents of lower 4 bits of address 0000H
in program memory are set to PC11 - 8,
and that of 0001H are set to PC7 - 0.
Same operation as that in
standby state
µPD75066
µPD75068
Contents of lower 5 bits of address 0000H
in program memory are set to PC12 - 8,
and that of 0001H are set to PC7 - 0.
Same operation as that in
standby state
Retained
Undefined
Skip flag (SK0-2)
0
0
Interrupt status flag (IST0)
0
0
The contents of bit 7 of address 0000H
of the program memory is set to MBE.
Same operation as that in
standby state
Undefined
Undefined
RetainedNote
Undefined
Retained
Undefined
0
0
Undefined
Undefined
Hardware
Program counter (PC)
PSW
Carry flag (CY)
Bank enable flag (MBE)
Stack pointer (SP)
Data memory (RAM)
General purpose register
(X, A, H, L, D, E, B, C)
Bank selection register (MBS)
Basic interval
timer
Counter (BT)
Mode register (BTM)
0
0
Timer/event
counter
Counter (T0)
0
0
FFH
FFH
0
0
0, 0
0, 0
0
0
Modulo register (TMOD0)
Mode register (TM0)
TOE0, TOUT F/F
Watch timer
Mode register (WM)
Note Data of address 0F8H to 0FDH of the data memory becomes undefined when the RESET signal is input.
30
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Table 8-1. Status of All Hardware after Reset (2/2)
RESET input in standby mode
RESET input during operation
Retained
Undefined
Operation mode register (CSIM)
0
0
SBI control register (SBIC)
0
0
Retained
Undefined
Processor clock control register
(PCC)
0
0
System clock control register
(SCC)
0
0
Clock output mode register
(CLOM)
0
0
IRQ1, IRQ2,
and IRQ4
Undefined
Undefined
Other than above
0
0
Interrupt enable flag (IE×××)
0
0
Interrupt master enable flag
(IME)
0
0
0, 0, 0
0, 0, 0
Output buffer
Off
Off
Output latch
Clear (0)
Clear (0)
Input/output mode register
(PMGA, PMGB)
0
0
Pull-up resistor specification
register (POGA)
0
0
04H
04H
Undefined
Undefined
Retained
Undefined
Hardware
Serial
interface
Shift register (SIO)
Slave address register (SVA)
Clock generator, Clock
output circuit
Interrupt
function
Interrupt
request flag
( IRQxxx )
INT0, 1, 2, mode register
(IM0, IM1, IM2)
Digital port
A/D converter
Mode register (ADM)
SA register (SA)
Bit sequential buffer (BSB0-BSB3)
31
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
9.
INSTRUCTION SET
(1) Operand identifier and its descriptive method
The operands are described in the operand column of each instruction according to the descriptive method
for the operand format of the appropriate instructions. Details should be followed by "RA75X Assembler
Package User's Manual, Language." For descriptions in which alternatives exist, one element should be
selected. Capital letters and plus and minus signs are keywords; therefore, they should be described as
they are.
For immediate data, the appropriate numerical values or labels should be described.
Description
Identifier
reg
reg1
X, A, B, C, D, E, H, L
X, B, C, D, E, H, L
rp
rp1
rp2
XA, BC, DE, HL
BC, DE, HL
BC, DE
rpa
rpa1
HL, DE, DL
DE, DL
n4
n8
4-bit immediate data or label
8-bit immediate data or label
memNote
bit
8-bit immediate data or label
2-bit immediate data or label
fmem
pmem
FB0H - FBFH, FF0H - FFFH immediate data or label
FC0H - FFFH immediate data or label
addr
µPD75064
0000H - 0FFFH immediate data or label
µPD75066
0000H - 177FH immediate data or label
µPD75068
0000H - 1F7FH immediate data or label
caddr
12-bit immediate data or label
faddr
11-bit immediate data or label
taddr
20H - 7FH immediate data (however, bit 0 = 0) or label
PORTn
PORT0 - PORT6, PORT11
IEBT, IECSI, IET0, IE0, IE1, IE2, IE4, IEW
MB0, MB1, MB15
IExxx
MBn
Note
Only even address can be specified for mem when processing 8-bit data.
(2) Symbol definitions in operation description
32
A
: A register; 4-bit accumulator
B
: B register
C
: C register
D
: D register
E
: E register
H
: H register
L
: L register
X
: X register
XA
: Pair register (XA); 8-bit accumulator
BC
: Pair register (BC)
DE
: Pair register (DE)
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
HL
: Pair register (HL)
PC
: Program counter
SP
: Stack pointer
CY
: Carry flag; Bit accumulator
PSW
: Program status word
MBE
: Memory bank enable flag
PORTn : Port n (n = 0 to 6, 11)
IME
: Interrupt master enable flag
IE×××
: Interrupt enable flag
MBS
: Memory bank selection register
PCC
: Processor clock control register
.
: Address bit delimiter
(××)
: Contents addressed by ××
××H
: Hexadecimal data
(3) Symbols used for the addressing area column
*1
MB = MBE · MBS
(MBS = 0, 1, 15)
*2
MB = 0
*3
MBE = 0: MB = 0 (00H - 7FH)
MB = 15 (80H - FFH)
MBE = 1: MB = MBS (MBS = 0, 1, 15)
*4
MB = 15, fmem = FB0H - FBFH,
FF0H - FFFH
*5
MB = 15, pmem = FC0H - FFFH
*6
µ PD75064
addr = 0000H - 0FFFH
µ PD75066
addr = 0000H - 177FH
µ PD75068
addr = 0000H - 1F7FH
*7
addr = (Current PC) – 15 to (Current PC) – 1
(Current PC) + 2 to (Current PC) + 16
*8
µ PD75064
caddr = 0000H - 0FFFH
µ PD75066
caddr = 0000H - 0FFFH (PC 12 = 0) or
= 1000H - 177FH (PC12 = 1)
µ PD75068
caddr = 0000H - 0FFFH (PC 12 = 0) or
= 1000H - 1F7FH (PC12 = 1)
*9
faddr = 0000H - 07FFH
*10
taddr = 0020H - 007FH
Data memory
addressing
Program memory
addressing
Remarks 1. MB indicates the memory bank that can be accessed.
2. For *2, MB = 0 regardless of MBE and MBS settings.
3. For *4 and *5, MB = 15 regardless of MBE and MBS.
4. For *6 to *10, each addressable area is indicated.
33
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
(4) Description of machine cycle column
S indicates the number of machine cycles necessary for skipping any skip instruction. The value of S
changes as follows:
• When no skip is performed ············································································································ S = 0
• When a 1-byte or 2-byte instruction is skipped ············································································S = 1
• When a 3-byte instruction (BR !addr
Note
Note
, CALL !addr instruction) is skipped ······················· S = 2
BR !addr instruction is not provided in the µPD75064.
Caution The GETI instruction is skipped in one machine cycle.
One machine cycle is equivalent to one CPU clock Φ cycle. Therefore, the length of the machine cycle
can be selected from three different lengths by the PCC setting.
★
(5) Representative products listed in operation column
The products listed in the operation column (µPD75064, 75066, 75068) stand for the products listed below.
34
µPD75064
µPD75064, µPD75064(A)
µPD75066
µPD75066, µPD75066(A)
µPD75068
µPD75068, µPD75068(A)
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Group
Transfer
Mnemonic
MOV
XCH
Table
reference
MOVT
Operand
MaBytes chine
cycle
Operation
Addressing area
Skip
condition
A, #n4
1
1
A ← n4
reg1, #n4
2
2
reg1 ← n4
XA, #n8
2
2
XA ← n8
String A
HL, #n8
2
2
HL ← n8
String B
rp2, #n8
2
2
rp2 ← n8
A, @HL
1
1
A ← (HL)
*1
A, @rpa1
1
1
A ← (rpa1)
*2
XA, @HL
2
2
XA ← (HL)
*1
@HL, A
1
1
(HL) ← A
*1
@HL, XA
2
2
(HL) ← XA
*1
A, mem
2
2
A ← (mem)
*3
XA, mem
2
2
XA ← (mem)
*3
mem, A
2
2
(mem) ← A
*3
mem, XA
2
2
(mem) ← XA
*3
A, reg
2
2
A ← reg
XA, rp
2
2
XA ← rp
reg1, A
2
2
reg1 ← A
rp1, XA
2
2
rp1 ← XA
A, @HL
1
1
A ↔ (HL)
*1
A, @rpa1
1
1
A ↔ (rpa1)
*2
XA, @HL
2
2
XA ↔ (HL)
*1
A, mem
2
2
A ↔ (mem)
*3
XA, mem
2
2
XA ↔ (mem)
*3
A, reg1
1
1
A ↔ reg1
XA, rp
2
2
XA ↔ rp
XA, @PCDE
1
3
• µPD75064
String A
XA ← (PC11-8 + DE)ROM
• µPD75066, 75068
XA ← (PC12-8 + DE)ROM
XA, @PCXA
1
3
• µPD75064
XA ← (PC11-8 + XA)ROM
• µPD75066, 75068
XA ← (PC12-8 + XA)ROM
Arithmetic
A, #n4
1
1+S
A ← A + n4
A, @HL
1
1+S
A ← A + (HL)
*1
ADDC
A, @HL
1
1
A, CY ← A + (HL) + CY
*1
SUBS
A, @HL
1
1+S
A ← A – (HL)
*1
SUBC
A, @HL
1
1
A, CY ← A – (HL) – CY
*1
ADDS
carry
carry
borrow
35
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Group
Arithmetic
Mnemonic
AND
OR
XOR
Operand
MaBytes chine
cycle
Address- Skip
ing area condition
Operation
A, #n4
2
2
A, @HL
1
1
A, #n4
2
2
A, @HL
1
1
A, #n4
2
2
A, @HL
1
1
∧ n4
A ← A ∧ (HL)
A ← A ∨ n4
A ← A ∨ (HL)
A ← A ∨ n4
A ← A ∨ (HL)
A←A
*1
*1
Accumulator
RORC
A
1
1
CY ← A0 ,
manipulation
NOT
A
2
2
A ← A
Increment/
decrement
INCS
reg
1
1+S
reg ← reg + 1
@HL
2
2+S
(HL) ← (HL) + 1
*1
(HL) = 0
mem
2
2+S
(mem) ← (mem) + 1
*3
(mem) = 0
DECS
reg
1
1+S
reg ← reg – 1
reg = FH
SKE
reg, #n4
2
2+S
Skip if reg = n4
reg = n4
@HL, #n4
2
2+S
Skip if (HL) = n4
*1
(HL) = n4
A, @HL
1
1+S
Skip if A = (HL)
*1
A = (HL)
A, reg
2
2+S
Skip if A = reg
SET1
CY
1
1
CY ← 1
CLR1
CY
1
1
CY ← 0
SKT
CY
1
1+S
NOT1
CY
1
1
CY ← CY
SET1
mem.bit
2
2
(mem.bit) ← 1
*3
fmem.bit
2
2
(fmem.bit) ← 1
*4
pmem. @L
2
2
(pmem7-2 + L3-2.bit(L1-0)) ← 1
*5
@H+mem.bit
2
2
(H + mem3-0.bit) ← 1
*1
mem.bit
2
2
(mem.bit) ← 0
*3
fmem.bit
2
2
(fmem.bit) ← 0
*4
pmem. @L
2
2
(pmem7-2 + L3-2.bit(L1-0)) ← 0
*5
@H+mem.bit
2
2
(H + mem3-0.bit) ← 0
*1
mem.bit
2
2+S
Skip if (mem.bit) = 1
*3
(mem.bit) = 1
fmem.bit
2
2+S
Skip if (fmem.bit) = 1
*4
(fmem.bit) = 1
pmem. @L
2
2+S
Skip if (pmem7-2 + L 3-2.bit(L1-0)) = 1
*5
(pmem.@L) = 1
@H+mem.bit
2
2+S
Skip if (H + mem3-0.bit) = 1
*1
(@H + mem.bit) = 1
mem.bit
2
2+S
Skip if (mem.bit) = 0
*3
(mem.bit) = 0
fmem.bit
2
2+S
Skip if (fmem.bit) = 0
*4
(fmem.bit) = 0
pmem. @L
2
2+S
Skip if (pmem7-2 + L 3-2.bit(L1-0)) = 0
*5
(pmem.@L) = 0
@H+mem.bit
2
2+S
Skip if (H + mem3-0.bit) = 0
*1
(@H + mem.bit) = 0
fmem.bit
2
2+S
Skip if (fmem.bit) = 1 and clear
*4
(fmem.bit) = 1
pmem. @L
2
2+S
Skip if (pmem7-2 + L3-2.bit(L1-0)) = 1 and clear
*5
(pmem.@L) = 1
@H+mem.bit
2
2+S
Skip if (H + mem3-0.bit) = 1 and clear
*1
(@H + mem.bit) = 1
Comparison
Carry
flag
manipulation
Memory
bit
manipulation
CLR1
SKT
SKF
SKTCLR
36
A3 ← CY,
*1
An–1 ← An
reg = 0
A = reg
CY = 1
Skip if CY = 1
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Group
Memory
bit manipulation
Mnemonic
AND1
OR1
XOR1
Branch
BR
Operand
MaBytes chine
cycle
Operation
CY, fmem.bit
2
2
CY, pmem. @L
2
2
CY, @H+mem.bit
2
2
CY, fmem.bit
2
2
CY, pmem. @L
2
2
CY, @H+mem.bit
2
2
CY, fmem.bit
2
2
CY, pmem.@L
2
2
∧ (fmem.bit)
CY ← CY ∧ (pmem7-2 + L 3-2.bit(L1-0))
CY ← CY ∧ (H + mem3-0.bit)
CY ← CY ∨ (fmem.bit)
CY ← CY ∨ (pmem7-2 + L 3-2.bit(L1-0))
CY ← CY ∨ (H + mem3-0.bit)
CY ← CY ∨ (fmem.bit)
CY ← CY ∨ (pmem7-2 + L3-2.bit(L 1-0))
CY, @H+mem.bit
2
2
CY ← CY
addr
–
–
• µPD75064
PC11-0 ← addr
(Appropriate instructions are
selected from BRCB !caddr, and
CY ← CY
∨ (H + mem3-0.bit)
Addressing area
Skip
condition
*4
*5
*1
*4
*5
*1
*4
*5
*1
*6
BR $addr by the assembler.)
• µPD75066, 75068
PC12-0 ← addr
(Appropriate instructions are
selected from BR !addr, BRCB
!caddr, and BR $addr by the
assembler.)
!addr
Note
$addr
3
3
1
2
• µPD75066, 75068
PC12-0 ← addr
*6
• µPD75064
PC11-0 ← addr
*7
• µPD75066, 75068
PC12-0 ← addr
BRCB
!caddr
2
2
• µPD75064
PC11-0 ← caddr 11-0
*8
• µPD75066, 75068
PC12-0 ← PC12 + caddr11-0
Subroutine
stack
control
CALL
!addr
3
3
• µPD75064
(SP – 4)(SP – 1)(SP – 2) ← PC11-0
(SP – 3) ← MBE, 0, 0, 0
PC11-0 ← addr, SP ← SP – 4
*6
• µPD75066, 75068
(SP – 4)(SP – 1)(SP – 2) ← PC11-0
(SP–3) ← MBE, 0, 0, PC12
PC12-0 ← addr, SP ← SP – 4
Note
BR !addr instruction is not provided in the µPD75064.
37
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Group
Subroutine
stack
control
Mnemonic
CALLF
Operand
!faddr
MaBytes chine
cycle
2
2
Operation
• µPD75064
(SP – 4)(SP – 1)(SP – 2) ← PC11-0
(SP–3) ← MBE, 0, 0, 0
PC11-0 ← 00, faddr, SP ← SP – 4
Addressing area
Skip
condition
*9
• µPD75066, 75068
(SP – 4)(SP – 1)(SP – 2) ← PC11-0
(SP–3) ← MBE, 0, 0, PC12
PC12-0 ← 00, faddr, SP ← SP – 4
1
RET
3
• µPD75064
MBE, 0, 0, 0 ← (SP + 1)
PC11-0 ← (SP)(SP + 3)(SP + 2)
SP ← SP + 4
• µPD75066, 75068
MBE, 0, 0, PC12 ← (SP + 1)
PC11-0 ← (SP)(SP + 3)(SP + 2)
SP ← SP + 4
1
RETS
3+S
• µPD75064
MBE, 0, 0, 0 ← (SP + 1)
PC11-0 ← (SP)(SP + 3)(SP + 2)
SP ← SP + 4, then skip unconditionally
• µPD75066, 75068
MBE, 0, 0, PC12 ← (SP + 1)
PC11-0 ← (SP)(SP + 3)(SP + 2)
SP ← SP + 4, then skip unconditionally
1
RETI
3
• µPD75064
MBE, 0, 0, 0 ← (SP + 1)
PC11-0 ← (SP)(SP + 3)(SP + 2)
PSW ← (SP + 4)(SP + 5), SP ← SP + 6
• µPD75066, 75068
MBE, 0, 0, PC12 ← (SP + 1)
PC11-0 ← (SP)(SP + 3)(SP + 2)
PSW ← (SP + 4)(SP + 5), SP ← SP + 6
PUSH
POP
38
rp
1
1
(SP – 1)(SP – 2) ← rp, SP ← SP – 2
BS
2
2
(SP – 1) ← MBS, (SP – 2) ← 0, SP ← SP – 2
rp
1
1
rp ← (SP + 1)(SP), SP ← SP + 2
BS
2
2
MBS ← (SP + 1), SP ← SP + 2
Unconditional
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Group
Interrupt
control
Mnemonic
Operand
2
IME ← 1
2
2
IExxx ← 1
2
2
IME ← 0
IExxx
2
2
IExxx ← 0
A, PORTn
2
2
A ← PORTn
XA, PORTn
2
2
XA ← PORTn+1,PORTn
(n = 4, 6)
PORTn, A
2
2
PORTn ← A
(n = 2 - 6)
PORTn, XA
2
2
PORTn+1, PORTn ← XA (n = 4, 6)
HALT
2
2
Set HALT Mode
(PCC.2 ← 1)
STOP
2
2
Set STOP Mode
(PCC.3 ← 1)
NOP
1
1
No Operation
IExxx
IN
OUT
CPU
control
Special
Addressing area
Operation
2
EI
DI
Input/
output
MaBytes chine
cycle
(n = 0 - 6, 11)
SEL
MBn
2
2
MBS ← n (n = 0, 1, 15)
GETI
taddr
1
3
• µPD75064
• For the TBR instruction
PC11-0 ← (taddr)3-0 + (taddr + 1)
---------------------------------------------•
For the TCALL instruction
(SP – 4)(SP – 1)(SP – 2) ← PC11-0
(SP – 3) ← MBE, 0, 0, 0
PC11-0 ← (taddr)3-0 + (taddr + 1)
SP ← SP – 4
---------------------------------------------•
For other than the TBR and
TCALL instruction
(taddr) (taddr + 1) is executed.
• µPD75066, 75068
• For the TBR instruction
PC12-0 ← (taddr)4-0 + (taddr + 1)
---------------------------------------------•
For the TCALL instruction
(SP – 4)(SP – 1)(SP – 2) ← PC11-0
(SP – 3) ← MBE, 0, 0, PC12
PC12-0 ← (taddr)4-0 + (taddr + 1)
SP ← SP – 4
---------------------------------------------•
Skip
condition
For other than the TBR and
TCALL instruction
(taddr) (taddr + 1) is executed.
*10
-----------------
----------------Depends on
the reference
instruction.
-----------------
----------------Depends on
the reference
instruction.
Caution When executing the IN/OUT instruction, MBE must be set to 0, or MBE and MBS must be set to
1 and 15, respectively.
39
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (Ta = 25 °C)
Parameter
Power supply
voltage
Symbol
Conditions
Ratings
VDD
–0.3 to +7.0
V
–0.3 to VDD+0.3
V
–0.3 to VDD+0.3
V
–0.3 to +11
V
–0.3 to VDD+0.3
V
Per pin
–10
mA
All output pins
–30
mA
Peak value
30
mA
rms value
15
mA
Peak value
20
mA
rms value
5
mA
Peak value
160
mA
rms value
120
mA
Peak value
30
mA
rms value
20
mA
VI1
Except ports 4 and 5
VI2
Ports 4 and 5
Input voltage
On-chip pull-up resistor
N-ch open–drain
Output voltage
VO
High level output
current
IOH
Low level output
current
Unit
One pin of ports 0, 3, 4, and 5
IOLNote
One pin of ports 2 and 6
Total of ports 0, 3, 4 and 5
Total of ports 2 and 6
Operating ambient
temperature
Topt
–40 to +85
°C
Storage
temperature
Tstg
–65 to +150
°C
Note Rms value is calculated using the following expression: [rms value] = [peak value] × √duty ratio
Caution If any of the items exceeds the absolute maximum ratings, even momentarily, this may damage product
quality. The absolute maximum ratings are values that may physically damage products. Be sure to use
the products within the ratings.
40
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Main System Clock Oscillator Characteristics (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Recommended
Constant
Resonator
VSS
X1
Parameter
Oscillation
frequency (fx)Note1
X2
Ceramic
resonator
C1
VSS
Crystal
resonator
C2
X1
Conditions
VDD = Oscillation voltage
range
TYP.
1.0
MAX.
5.0
Oscillation
stabilization
timeNote2
1.0
4.19
5.0
VDD = 4.5
to 6.0 V
C1
X1
C2
X2
External
clock
µ PD74HCU04
Note3
4
Oscillation
frequency (fx)Note1
X2
MIN.
Oscillation
stabilization
timeNote2
X1 input
frequency (fx)Note1
1.0
X1 input
high-/low-level
width (tXH, tXL)
100
Note3
Unit
MHz
ms
MHz
10
ms
30
ms
5.0
Note3
500
MHz
ns
Notes 1. The oscillation frequency indicates characteristics of the oscillator only. For the instruction execution time,
refer to the AC characteristics.
2. The oscillation stabilization time is the required time for oscillation to stabilize after the voltage level of
VDD reaches the MIN. value of the oscillation voltage range or releasing the STOP mode.
3. When the oscillation frequency is “4.19 MHz < fX ≤ 5.0 MHz”, selection of “PCC = 0011” with 1 machine
cycle of less than 0.95 µs for instruction execution time is not possible.
Caution If the main system clock oscillator is used, the wiring in the area indicated with broken lines in the
recommended constant illustration should be routed observing the points described below to avoid
influence of wiring capacitance, etc.
• Route as short as possible.
• Do not cross the wires.
• Route the wires away from lines where changing high current flows.
• Make the connecting point of the capacitors in the oscillation circuit to have always the same potential
as VSS. Do not route the connecting point to another ground pattern on the board where high current
flows.
• Do not use the oscillator as a signal source of other circuits.
41
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Subsystem Clock Oscillator Characteristics (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Recommended
Constant
Resonator
Parameter
Conditions
Oscillation
frequency (fXT)Note1
VSS
XT1
Crystal
resonator
C3
MAX.
Unit
32
32.768
50
kHz
1.0
2
s
10
s
32
100
kHz
5
15
µs
VDD = 4.5
to 6.0 V
C4
Oscillation
stabilization
timeNote2
XT1 input
frequency (fXT)Note1
External
clock
TYP.
XT2
R
XT1
MIN.
XT2
XT1 input high-/
low-level width
(tXTH,tXTL)
Notes 1. The oscillation frequency indicates characteristics of the oscillator only. For the instruction execution
time, refer to the AC characteristics.
2. The oscillation stabilization time is the required time for oscillation to stabilize after the voltage level
of VDD reaches the MIN. value of the oscillation voltage range.
Caution If the subsystem clock oscillator is used, the wiring in the area indicated with broken lines in the
recommended constant illustration should be routed observing the points described below to avoid
influence of wiring capacitance, etc.
•
•
•
•
Route as short as possible.
Do not cross the wires.
Route the wires away from lines where changing high current flows.
Make the connecting point of the capacitors in the oscillation circuit to have always the same potential
as VSS. Do not route the connecting point to another ground pattern on the board where high current
flows.
• Do not use the oscillator as a signal source of other circuits.
Especially when using the subsystem clock, be sure to design wiring so as to minimize noise. The
subsystem clock oscillator uses a low-amplification circuit to minimize power dissipation. As a result,
malfunctions due to noise are more liable to occur than with the main system clock oscillator.
42
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Recommended Oscillator Constant
Main system clock: Ceramic (Ta = –40 to +85°C)
Manufacturer
Part number
Frequency
(MHz)
KBR-2.0 MS
Recommended
circuit constant
C1 (pF)
Oscillation
voltage range
C2 (pF)
2.00
47
47
4.19
33
33
Remarks
MAX. (V)
MIN. (V)
2.5
PBRC 2.00A
KYOCERA
KBR-4.19 MSA
6.0
PBRC 4.19A
2.7
KBR-4.19 MKS
4.19
Internal
Internal
1.00
100
100
2.7
100
100
2.8
Internal
Internal
15
15
30
30
Internal
Internal
KBR-4.19 MWS
CSB1000JNote
CSA2.0MG040
MURATA
Manufacturing
CST2.0MGW093
2.00
CSAC2.0MGCME
CSA4.19MGU
Rd = 5.6 kΩ
6.0
Chip product
2.7
4.19
CST4.19MGUW
Note When the Murata's CSB1000J ceramic resonator (1.00 MHz) is used, the limiting resistor (Rd = 5.6 kΩ) is
required (see figure below). When using other recommended resonators, the limiting resistor is not required.
Example of Recommended Main System Clock Circuit (when using CSB1000J of Murata)
X1
X2
CSB1000J
C1
Rd
C2
Main System Clock: XTAL
Manufacturer
Part number
Frequency
(MHz)
Recommended
circuit constant
C1 (pF)
C2 (pF)
2.00
DAISINKU
HC-49/U
4.19
Oscillation
voltage range
MIN. (V)
Remarks
MAX. (V)
2.8
8
8
22
22
2.7
6.0
(T a = –40 to +85°C)
6.0
(T a = –20 to +70°C)
5.00
2.00
KINSEKI
HC-49/U
4.19
3.1
3.2
43
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
DC Characteristics (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Parameter
High-level input
voltage
Low-level input
voltage
High-level output
voltage
Low-level output
voltage
Symbol
Conditions
VDD
V
VIH2
Ports 0,1,6, RESET
0.8 VDD
VDD
V
On-chip pull-up resistor
0.7 VDD
VDD
V
VIH3
Ports 4 and 5
N-ch open-drain
0.7 VDD
10
V
VDD –0.5
VDD
V
VIH4
X1, X2, XT1, XT2
VIL1
Ports 2 through 5 and 11
0
0.3 VDD
V
VIL2
Ports 0, 1, 6, RESET
0
0.2 VDD
V
VIL3
X1, X2, XT1, XT2
0
0.4
V
VOH
VDD = 4.5 to 6.0 V , IOH = –1 mA
VDD –1.0
V
IOH = –100 µA
VDD –0.5
V
VOL
Ports 4 and 5
VDD = 4.5 to 6.0 V
IOL = 15 mA
0.7
2.0
V
Port 3
VDD = 4.5 to 6.0 V
IOL = 15 mA
0.3
2.0
V
VDD = 4.5 to 6.0 V , IOL = 1.6 mA
0.4
V
IOL = 400 µA
0.5
V
N-ch open-drain
pull-up resistor ≥ 1 kΩ
0.2 VDD
V
Other than pins below
3
µA
X1, X2, XT1, XT2
20
µA
Ports 4 and 5
(N-ch open-drain)
20
µA
Other than pins below
–3
µA
X1, X2, XT1, XT2
–20
µA
3
µA
20
µA
–3
µA
80
kΩ
300
kΩ
70
kΩ
60
kΩ
ILIH1
VI = VDD
VI = 10 V
ILIL1
VI = 0 V
ILIL2
Low-level output
leakage current
On-chip pull-up
resistor
Unit
0.7 VDD
ILIH3
High-level output
leakage current
MAX.
Ports 2, 3, and 11
ILIH2
Low-level input
leakage current
TYP.
VIH1
SB0, SB1
High-level input
leakage current
MIN.
ILOH1
VO = VDD
ILOH2
VO = 10 V
ILOL
VO = 0 V
RU1
P01, 02, 03,
Ports 1, 2, 3 and 6
VI = 0 V
RU2
Ports 4 and 5
VO = VDD – 2.0 V
Ports 4 and 5
(N-ch open-drain)
VDD = 5.0 V ±10 %
15
VDD = 3.0 V ±10 %
30
VDD = 5.0 V ±10 %
15
VDD = 3.0 V ±10 %
10
40
40
(Cont.)
44
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
DC Characteristics (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Parameter
Supply current
Symbol
Conditions
Note1
MIN.
TYP.
MAX.
Unit
VDD = 5.0 V ±10 %
Note3
2.0
6.0
mA
VDD = 3.0 V ±10 %
Note4
0.2
0.6
mA
IDDI
4.19 MHz Note2
crystal oscillation
C1 = C2 = 22 pF
HALT
VDD = 5.0 V ±10 %
400
1200
µA
mode
VDD = 3.0 V ±10 %
120
400
µA
10
30
µA
5
15
µA
VDD = 5.0 V ±10 %
0.5
20
µA
VDD =
3.0 V ±10 %
0.1
10
µA
0.1
5
µA
IDD2
VDD = 3.0 V ±10 %
IDD3
IDD4
IDD5
32.768 kHz Note5
crystal oscillation
XT1 = 0 V
STOP mode
HALT
mode
VDD = 3.0 V ±10 %
Ta = 25 °C
Notes 1. Current which flows in the on-chip pull-up resistor is not included.
2. Including oscillation of the subsystem clock.
3. When the processor clock control register (PCC) is set to 0011 and the device is operated in the highspeed mode.
4. When PCC is set to 0000 and the device is operated in the low-speed mode.
5. When the system clock control register (SCC) is set to 1001 and the device is operated on the subsystem clock, with main system clock oscillation stopped.
45
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Capacitance (Ta = 25 °C, VDD = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
15
pF
Input capacitance
CI
f = 1 MHz
Unmeasured pins returned to 0 V.
Output capacitance
CO
15
pF
I/O capacitance
CIO
15
pF
MAX.
Unit
0.95
64
µs
3.8
64
µs
125
µs
0
1
MHz
0
275
kHz
AC Characteristics (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Parameter
CPU clock
cycle time Note1
( minimum
instruction
execution time =
1 machine cycle )
TI0 input
frequency
Symbol
Conditions
Operating on main
system clock
MIN.
VDD = 4.5 to 6.0 V
tCY
Operating on subsystem clock
TYP.
114
VDD = 4.5 to 6.0 V
122
fTI
TI0 input high and
low level width
Interrupt input high
and low level width
RESET low level
width
tTIH,
tTIL
0.48
µs
1.8
µs
Note2
µs
INT1, INT2, INT4
10
µs
KR0 to KR3
10
µs
10
µs
VDD = 4.5 to 6.0 V
INT0
tINTH,
tINTL
tRSL
tCY vs VDD
(Operating on Main System Clock)
Notes 1. The cycle time (minimum instruction
execution time) of the CPU clock (Φ) is
determined by the oscillation frequency of
supply voltage VDD characteristic with the
main system clock operating.
2. 2tCY or 128/fX is set by setting the interrupt
mode register (IM0).
64
60
6
Operation
guarantee range
5
4
Cycle Time tCY [ µ s]
the connected resonator, the system clock
control register (SCC), and the processor
clock control register (PCC). The figure at
the right indicates the cycle time tCY versus
70
3
2
1
0.5
0
1
2
3
4
5
Supply Voltage VDD [V]
46
6
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Serial Transfer Operation
2-Wire and 3-Wire Serial I/O Modes (SCK ... Internal clock output)
Parameter
Symbol
SCK cycle time
Conditions
VDD = 4.5 to 6.0 V
MIN.
TYP.
MAX.
Unit
1600
ns
3800
ns
tKCY1/2-50
ns
tKCY1/2-150
ns
tKCY1
SCK high- and lowlevel width
tKL1
tKH1
VDD = 4.5 to 6.0 V
SI setup time
(to SCK↑)
tSIK1
150
ns
SI hold time
(from SCK↑)
tKSI1
400
ns
SO output
delay time
from SCK↓
tKSO1
RL = 1 kΩ,
CL = 100 pF
VDD = 4.5 to 6.0 V
0
250
ns
0
1000
ns
MAX.
Unit
Note
2-Wire and 3-Wire Serial I/O Modes (SCK ... External clock input)
Parameter
Symbol
SCK cycle time
Conditions
VDD = 4.5 to 6.0 V
MIN.
TYP.
800
ns
3200
ns
400
ns
1600
ns
tKCY2
SCK high- and lowlevel width
tKL2
tKH2
VDD = 4.5 to 6.0 V
SI setup time
(to SCK↑)
tSIK2
100
ns
SI hold time
(from SCK ↑)
tKSI2
400
ns
SO output
delay time
from SCK↓
tKSO2
RL = 1 kΩ,
CL = 100 pF
VDD = 4.5 to 6.0 V
0
300
ns
0
1000
ns
Note
Note RL and CL are load resistance and load capacitance of the SO output line, respectively.
47
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
SBI Mode (SCK ... Internal clock output (Master))
Parameter
Symbol
SCK cycle time
Conditions
VDD = 4.5 to 6.0 V
MIN.
TYP.
MAX.
Unit
1600
ns
3800
ns
tKCY3/2-50
ns
tKCY3/2-150
ns
tKCY3
SCK high- and low-level
width
tKL3
tKH3
VDD = 4.5 to 6.0 V
SB0, 1 setup time
(to SCK ↑)
tSIK3
150
ns
SB0, 1 hold time
(from SCK ↑)
tKSI3
tKCY3/2
ns
SB0, 1 output
delay time from
SCK ↓
tKSO3
SB0, 1 ↓ from SCK ↑
tKSB
tKCY3
ns
SCK ↓ from SB0, 1 ↓
tSBK
tKCY3
ns
SB0, 1 low-level width
tSBL
tKCY3
ns
SB0, 1 high-level width
tSBH
tKCY3
ns
RL = 1 kΩ,
CL = 100 pF
VDD = 4.5 to 6.0 V
0
250
ns
0
1000
ns
Note
SBI Mode (SCK ... External clock input (Slave))
Parameter
Symbol
SCK cycle time
Conditions
VDD = 4.5 to 6.0 V
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
tKCY4
SCK high- and low-level
width
tKL4
tKH4
VDD = 4.5 to 6.0 V
SB0, 1 setup time
(to SCK ↑)
tSIK4
100
ns
SB0, 1 hold time
(from SCK ↑)
tKSI4
tKCY4/2
ns
SB0, 1 output
delay time from
SCK ↓
tKSO4
SB0, 1 ↓ from SCK ↑
tKSB
tKCY4
ns
SCK ↓ from SB0, 1 ↑
tSBK
tKCY4
ns
SB0, 1 low-level width
tSBL
tKCY4
ns
SB0, 1 high-level width
tSBH
tKCY4
ns
RL = 1 kΩ,
CL = 100 pF
VDD = 4.5 to 6.0 V
0
300
ns
0
1000
ns
Note
Note RL and CL are load resistance and load capacitance, respectively, for the SB0 and SB1 output lines.
48
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
A/D Converter (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
8
bit
–10 ≤ Ta ≤ +85 °C
±1.5
LSB
–40 ≤ Ta < –10 °C
±2.0
LSB
tCONV
168/fx
µs
Sampling time
tSAMP
44/fX
µs
Reference
input voltage
AVREF
2.5
VDD
V
Analog input voltage
VIAN
AVSS
AVREF
V
Analog input
impedance
RAN
1000
AVREF current
AIREF
0.7
Resolution
8
Absolute
accuracy Note1
2.5 V ≤ AVREF ≤ V DDNote2
Conversion timeNote3
Note4
TYP.
8
MΩ
2.0
mA
Notes 1. Absolute accuracy excluding quantization error (±1/2 LSB)
2. ADM1 should be set according to the A/D converter reference voltage (AVREF) as follows:
When the AVREF is between 0.6VDD and 0.65VDD, either 1 or 0 can be set.
2.5 V
0.6 VDD
0.65 VDD
VDD (2.7 to 6.0 V)
AVREF
ADM1 = 0
ADM1 = 1
3. The time from conversion start instruction execution to conversion end (EOC=1) (40.1 µs : at fX = 4.19
MHz)
4. The time from conversion start instruction execution to sampling end (10.5 µs : at fX = 4.19 MHz)
49
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
AC Timing Test Points (excluding X1 and XT1 inputs):
0.8 VDD
0.8 VDD
Test Points
0.2 VDD
0.2 VDD
Clock Timings:
1/fX
tXL
tXH
VDD –0.5 V
0.4 V
X1 Input
1/fXT
tXTL
tXTH
VDD –0.5 V
0.4 V
XT1 Input
TI0 Timings:
1/fTI
tTIL
TI0
50
tTIH
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Serial Transfer Timing
3-wire serial I/O mode:
tKCY1
tKL1
tKH1
SCK
tKSI1
tSIK1
Input Data
SI
tKSO1
SO
Output Data
2-wire serial I/O mode:
tKCY2
tKL2
tKH2
SCK
tSIK2
tKSI2
SB0,1
tKSO2
51
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Serial Transfer Timing
Bus release signal transfer:
tKL3,4
tKCY3,4
tKH3,4
SCK
tKSB
tSBL
tSBH
tSIK3,4
tSBK
SB0,1
tKSO3,4
Command signal transfer:
tKL3,4
tKCY3,4
tKH3,4
SCK
tKSB
tSIK3,4
tSBK
SB0,1
tKSO3,4
Interrupt Input Timing
tINTL
INT0,1,2,4
KR0-3
RESET Input Timing
tRSL
RESET
52
tINTH
tKSI3,4
tKSI3,4
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (Ta = –40 to +85 °C)
Parameter
Symbol
Data retention supply voltage
Data retention supply current
Conditions
MIN.
2.0
VDDDR
Note 1
Release signal setting time
Oscillation stabilization
wait time Note2
IDDDR
TYP.
VDDDR = 2.0 V
0.1
tSREL
MAX.
Unit
6.0
V
10
µA
µs
0
Release by RESET
217/fx
ms
Release by interrupt request
Note3
ms
tWAIT
Notes 1. Current which flows in the on-chip pull-up resistor is not included.
2. The oscillation stabilization wait time is the time during which the CPU operation is stopped to
prevent unstable operation at the oscillation start.
3. Depends on the basic interval timer mode register (BTM) settings (See the table below).
BTM3
BTM2
BTM1
BTM0
Wait Time
(Figures in parentheses are for operation at fx = 4.19 MHz)
—
0
0
0
220/fx (approx. 250 ms)
—
0
1
1
217/fx (approx. 31.3 ms)
—
1
0
1
215/fx (approx. 7.82 ms)
—
1
1
1
213/fx (approx. 1.95 ms)
Data Retention Timing (STOP mode release by RESET)
Internal Reset Operation
HALT Mode
STOP Mode
Operating
Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
RESET
tWAIT
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
HALT Mode
STOP Mode
Operating
Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
53
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
11.
CHARACTERISTIC CURVES (FOR REFERENCE ONLY)
I DD vs VDD (Main system clock: 4.19-MHz crystal resonator)
(Ta=25 °C)
X1
5.0
X2
Crystal
resonator
4.19 MHz
XT1
XT2
Crystal
resonator
32.768 kHz
330 kΩ
18 pF
18 pF
3.0
PCC=0011
22 pF
22 pF
PCC=0010
1.0
PCC=0000
Main system clock
HALT mode + 32 kHz
oscillation
Supply Current IDD [mA]
0.5
0.1
0.05
Subsystem clock
operation mode
Main system clock
STOP mode + 32 kHz
oscillation
and
subsystem clock
HALT mode
0.01
0.005
0.001
0
2
4
Supply Voltage VDD [V]
54
6
8
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
IDD vs VDD (Main system clock: 2.0-MHz crystal resonator)
(Ta=25 °C)
X2
X1
5.0
Crystal
resonator
2.0 MHz
XT2
XT1
Crystal
resonator
32.768 kHz
330 kΩ
18 pF
18 pF
3.0
22 pF
22 pF
Supply Current IDD [mA]
PCC=0011
1.0
PCC=0010
0.5
PCC=0000
Main system clock
HALT mode + 32 kHz
oscillation
0.1
0.05
Subsystem clock
operation mode
Main system clock
STOP mode + 32 kHz
oscillation
and
subsystem clock
HALT mode
0.01
0.005
0.001
0
2
4
Supply Voltage VDD [V]
6
8
55
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
IDD vs VDD (Main system clock: 4.19-MHz ceramic resonator)
(Ta=25 °C)
X1
5.0
X2
Ceramic
resonator
4.19 MHz
XT1
XT2
Crystal
resonator
32.768 kHz
330 kΩ
18 pF
18 pF
3.0
PCC=0011
30 pF
30 pF
PCC=0010
1.0
PCC=0000
Main system clock
HALT mode + 32 kHz
oscillation
Supply Current IDD [mA]
0.5
0.1
0.05
Subsystem clock
operation mode
Main system clock
STOP mode + 32 kHz
oscillation
and
subsystem clock
HALT mode
0.01
0.005
0.001
0
56
2
4
Supply Voltage VDD [V]
6
8
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
IDD vs V DD (Main system clock: 2.0-MHz ceramic resonator)
(Ta=25 °C)
X1
5.0
X2
Ceramic
resonator
2.0 MHz
XT1
XT2
Crystal
resonator
32.768 kHz
330 kΩ
18 pF
18 pF
3.0
30 pF
30 pF
PCC=0011
PCC=0010
1.0
PCC=0000
Main system clock
HALT mode + 32 kHz
oscillation
Supply Current IDD [mA]
0.5
0.1
0.05
Subsystem clock
operation mode
Main system clock
STOP mode + 32 kHz
oscillation
and
subsystem clock
HALT mode
0.01
0.005
0.001
0
2
4
Supply Voltage VDD [V]
6
8
57
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
I DD vs fX
IDD vs fX
(VDD = 5 V, Ta=25 °C)
2.0
X1
(VDD = 3 V, Ta=25 °C)
0.5
X2
X1
X2
PCC=0011
0.4
1.5
PCC=0010
PCC=0011
0.3
IDD [mA]
IDD [mA]
PCC=0010
1.0
0.2
PCC=0000
0.5
0.1
PCC=0000
0
0
1
3
2
4
Main system
clock
HALT mode
Main system
clock
HALT mode
5
6
0
0
1
4
3
2
5
6
fx [MHz]
fx [MHz]
IOL vs VOL (Port 0)
IOL vs VOL (Ports 2, 6)
(Ta=25 °C)
40
(Ta=25 °C)
30
25
VDD=5 V
30 VDD=6 V
VDD=4 V
VDD=5 V VDD=4 V
VDD=3 V
20 VDD=6 V
IOL [mA]
IOL [mA]
VDD=3 V
VDD=2.7 V
20
VDD=2.7 V
15
10
10
5
0
0
1
3
2
VOL [V]
58
4
5
0
0
1
2
VOL [V]
3
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
IOL vs VOL (Port 3)
IOL vs VOL (Ports 4, 5)
(Ta=25 °C)
40
VDD=6 V VDD=5 V
30
30
VDD=3 V
VDD=4 V
(Ta=25 °C)
40
VDD=5 V
VDD=4 V
VDD=6 V
VDD=3 V
IOL [mA]
IOL [mA]
VDD=2.7 V
20
10
10
0
VDD=2.7 V
20
0
2
1
3
4
5
VOL [V]
0
0
1
2
3
4
5
VOL [V]
IOH vs VOH
(Ta=25 °C)
15
10
VDD=6 V VDD=5 V
VDD=4 V VDD=3 V
IOH [mA]
VDD=2.7 V
5
0
0
1
2
3
4
VDD - VOH [V]
59
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
12.
PACKAGE DRAWINGS
42PIN PLASTIC SHRINK DIP (600 mil)
42
22
1
21
A
K
H
G
J
I
L
F
B
D
N
R
M
C
M
NOTES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
2) Item "K" to center of leads when formed parallel.
ITEM MILLIMETERS
INCHES
A
39.13 MAX.
1.541 MAX.
B
1.78 MAX.
0.070 MAX.
C
1.778 (T.P.)
0.070 (T.P.)
D
0.50±0.10
0.020 +0.004
–0.005
F
0.9 MIN.
0.035 MIN.
G
3.2±0.3
0.126±0.012
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
J
5.08 MAX.
0.200 MAX.
K
L
15.24 (T.P.)
13.2
0.600 (T.P.)
0.520
M
0.25 +0.10
–0.05
N
0.17
0.007
R
0~15°
0~15°
0.010 +0.004
–0.003
P42C-70-600A-1
★
Remark The outline dimensions and materials of ES versions are the same as for mass-produced versions.
60
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
44 PIN PLASTIC QFP (
10)
A
B
12
11
D
F
Q
5°±5°
44
1
detail of lead end
S
23
22
C
33
34
G
H
I M
J
M
P
K
N
L
P44GB-80-3B4-2
NOTE
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
13.6 ± 0.4
0.535+0.017
–0.016
B
10.0 ± 0.2
0.394+0.008
–0.009
C
10.0 ± 0.2
0.394+0.008
–0.009
D
13.6 ± 0.4
0.535+0.017
–0.016
F
1.0
0.039
G
1.0
0.039
H
0.35 ± 0.10
0.014+0.004
–0.005
0.006
I
0.15
J
0.8 (T.P.)
0.031 (T.P.)
K
1.8 ± 0.2
0.071+0.008
–0.009
L
0.8 ± 0.2
0.031+0.009
–0.008
M
0.15+0.10
–0.05
0.006+0.004
–0.003
N
0.12
0.005
P
2.7
0.106
Q
0.1 ± 0.1
0.004 ± 0.004
S
3.0 MAX.
0.119 MAX.
Remark The outline dimensions and materials of ES versions are the same as for mass-produced versions.
61
★
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
★
13.
RECOMMENDED SOLDERING CONDITIONS
Solder the µPD75064, 75066, 75068 under the soldering conditions indicated below.
For further information on the recommended soldering conditions, refer to information document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (IEI-1207)".
For soldering methods and conditions other than those of recommended, consult NEC.
Table 13-1. Soldering Conditions for Surface Mounting Devices
µPD75064GB-×××-3B4 : 44-pin plastic QFP (10 x 10 mm)
µPD75066GB-×××-3B4 : 44-pin plastic QFP (10 x 10 mm)
µPD75068GB-×××-3B4 : 44-pin plastic QFP (10 x 10 mm)
µPD75064GB(A)-×××-3B4 : 44-pin plastic QFP (10 x 10 mm)
µPD75066GB(A)-×××-3B4 : 44-pin plastic QFP (10 x 10 mm)
µPD75068GB(A)-×××-3B4 : 44-pin plastic QFP (10 x 10 mm)
Soldering conditions
Soldering method
Infrared ray reflow
Symbol
Peak temperature of package surface : 235 °C, Time : 30 seconds IR35-00-2
max. (210 °C min.), Number of reflow processes : 2 or less
<Note>
(1) Start second reflow after the device temperature, which rose
because of the first reflow, has dropped to the normal level.
(2) Do not clean the flux with water after the first reflow.
VPS
Peak temperature of package surface : 215 °C, Time : 40 seconds VP15-00-2
max. (200 °C min.), Number of reflow processes : 2 or less
<Note>
(1) Start second reflow after the device temperature, which rose
because of the first reflow, has dropped to the normal level.
(2) Do not clean the flux with water after the first reflow.
Wave soldering
Solder temperature : 260 °C max., Time : 10 seconds max., Number
WS60-00-1
of reflow processes : 1
Preheating temperature : 120 °C max. (package surface temperature)
Partial heating
Pin temperature : 300 °C max., Time : 3 seconds max., (per one side
—
of device)
Caution Do not apply two or more soldering methods (except partial heating method) to the same device.
62
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Table 13-2. Soldering Conditions for Through-Hole Type Devices
µPD75064CU-××× : 42-pin plastic shrink DIP (600 mil)
µPD75066CU-××× : 42-pin plastic shrink DIP (600 mil)
µPD75068CU-××× : 42-pin plastic shrink DIP (600 mil)
µPD75064CU(A)-××× : 42-pin plastic shrink DIP (600 mil)
µPD75066CU(A)-××× : 42-pin plastic shrink DIP (600 mil)
µPD75068CU(A)-××× : 42-pin plastic shrink DIP (600 mil)
Soldering conditions
Soldering method
Wave soldering
(Only leads)
Partial heating
Soldering bath temperature : 260 °C max., Time : 10 seconds max.
Pin temperature : 300 °C max., Time : 3 seconds max. (per pin)
Caution Solder only the leads by means of wave soldering , and exercise care that the jetted solder does
not come in contact with the package.
63
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
APPENDIX A.
DEVELOPMENT TOOLS
The following development tools are provided for the development of a system which employs the
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A).
Hardware
IE-75000-R
Note1
In-circuit emulator for 75X series
IE-75001-R
IE-75000-R-EM
Software
Note2
Emulation board for IE-75000-R or IE-75001-R
EP-75068CU-R
Emulation probe for all shrink DIP versions of this series
EP-75068GB-R
EV-9200G-44
Emulation probe for all QFP versions of this series. A 44-pin conversion
socket EV-9200G-44 is contained in this product.
PG-1500
PROM programming equipment
PA-75P008CU
An adapter for connecting the PG-1500 to the µPD75P068CU/GB.
IE control program
Host machines:
PG-1500 controller
PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00A
RA75X relocatable assembler
TM
IBM PC/AT
Note3
)
(refer to OS for IBM PC)
Notes 1. Available for maintenance only
2. The IE-75000-R-EM is not installed in the IE-75001-R.
3. Ver. 5.00/5.00A has the task swap function, but it cannot be used with this software.
★
OS for IBM PC
The following products are supported as OS for IBM PCs.
OS
Version
PC DOSTM
Ver. 5.02 to Ver. 6.1
MS-DOS
Ver. 3.30 to Ver. 5.00
IBM DOSTM
J5.02/V
Note1
, 5.0/V
Note2
Note2
Notes 1. Ver. 5.0 and later have the task swap function, but it cannot be used with this software.
2. Only the English mode is supported.
Remark
For development tools supplied by third-party manufacturers, refer to 75X Series Selection Guide
(IF-1027).
64
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
APPENDIX B.
RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However,
preliminary versions are not marked as such.
Documents related to device
Document
Doc. No.
User's Manual
IEU-1366
Instruction Quick Reference
—
Application Note
IEA-1296
75X Series Selection Guide
IF-1027
Documents related to development tool
Document
Hardware
Software
Doc. No.
IE-75000-R/IE-75001-R User's Manual
EEU-1416
IE-75000-R-EM User's Manual
EEU-1294
EP-75068CU-R User's Manual
EEU-1429
EP-75068GB-R User's Manual
EEU-1428
PG-1500 User's Manual
EEU-1335
RA75X Assembler Package User's Manual
PG-1500 Controller User's Manual
Operation
EEU-1346
Language
EEU-1363
EEU-1291
Other related documents
Document
Doc. No.
Package Manual
IEI-1231
Semiconductor Device Mounting Technology Manual
IEI-1207
Quality Grades on NEC Semiconductor Devices
IEI-1209
NEC Semiconductor Device Reliability/Quality Control System
—
Electrostatic Discharge (ESD) Test
—
Guide to Quality Assurance for Semiconductor Devices
Microcomputer-Related Product Guide - Third Party Products
MEI-1202
—
Caution The contents of the documents listed above are subject to change without prior notice to users.
Make sure to use the latest edition when starting design.
65
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
[MEMO]
66
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop generation of static electricity as much as possible,
and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must
not be touched with bare hands. Similar precautions need to be taken for
PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction.
CMOS devices behave differently than Bipolar or NMOS devices. Input
levels of CMOS devices must be fixed high or low by using a pull-up or pulldown circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the
device. Immediately after the power source is turned ON, the devices
with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device
is not initialized until the reset signal is received. Reset operation must be
executed immediately after power-on for devices having reset function.
67
µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime
systems, etc.
M4
MS-DOS is a trademark of Microsoft Corporation.
IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.
92.6