NEC UPD780033AYGC

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD780031AY, 780032AY, 780033AY, 780034AY
8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD780031AY, 780032AY, 780033AY, and 780034AY are members of the µPD780034AY Subseries of the
78K/0 Series. This is a µPD780034A Subseries product with an added multimaster-supporting I2C bus interface, and
is suitable for AV equipment applications.
A flash memory version, the µPD78F0034AY, that can operate in the same power supply voltage range as the mask
ROM version, and various development tools, are available.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD780024A, 780034A, 780024AY, 780034AY
Subseries User's Manual:
U14046E
78K/0 Series User’s Manual Instructions:
U12326E
FEATURES
• Internal ROM and RAM
Item
Program Memory
(Internal ROM)
Data Memory
(Internal High-Speed RAM)
µPD780031AY
8 Kbytes
512 bytes
µPD780032AY
16 Kbytes
µPD780033AY
24 Kbytes
µPD780034AY
32 Kbytes
Part Number
Package
• 64-pin plastic shrink DIP (750 mils)
• 64-pin plastic QFP (14 × 14 mm)
1024 bytes
• 64-pin plastic LQFP (12 × 12 mm)
• External memory expansion space: 64 Kbytes
• Minimum instruction execution time: 0.24 µs (@ fX = 8.38-MHz operation)
• I/O ports: 51 (5-V-tolerant N-ch open-drain: 4)
• 10-bit resolution A/D converter: 8 channels (AVDD = 1.8 to 5.5 V)
• Serial interface: 3 channels (multimaster-supporting I2C bus mode, UART mode, 3-wire serial I/O mode)
• Timer: 5 channels
• Power supply voltage: VDD = 1.8 to 5.5 V
APPLICATIONS
Telephones, home electric appliances, pagers, AV equipment, car audios, office automation equipment, etc.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14045EJ1V0DS00 (1st edition)
Date Published August 1999 N CP(K)
Printed in Japan
©
1999
µPD780031AY, 780032AY, 780033AY, 780034AY
ORDERING INFORMATION
Part Number
µPD780031AYCW-×××
Package
64-pin plastic shrink DIP (750 mils)
µPD780031AYGC-×××-AB8
64-pin plastic QFP (14 × 14 mm)
µPD780031AYGK-×××-8A8
64-pin plastic LQFP (12 × 12 mm)
µPD780032AYCW-×××
64-pin plastic shrink DIP (750 mils)
µPD780032AYGC-×××-AB8
64-pin plastic QFP (14 × 14 mm)
µPD780032AYGK-×××-8A8
64-pin plastic LQFP (12 × 12 mm)
µPD780033AYCW-×××
64-pin plastic shrink DIP (750 mils)
µPD780033AYGC-×××-AB8
64-pin plastic QFP (14 × 14 mm)
µPD780033AYGK-×××-8A8
64-pin plastic LQFP (12 × 12 mm)
µPD780034AYCW-×××
64-pin plastic shrink DIP (750 mils)
µPD780034AYGC-×××-AB8
64-pin plastic QFP (14 × 14 mm)
µPD780034AYGK-×××-8A8
64-pin plastic LQFP (12 × 12 mm)
Remark ××× indicates ROM code suffix.
2
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
Control
100-pin
100-pin
100-pin
µ PD78075B
µ PD78078
µ PD78070A
100-pin
80-pin
µ PD780058
µ PD78058F
EMI-noise reduced version of the µ PD78078
µPD78078Y
µPD78054 with added timer and enhanced external interface
µ PD78070AY
ROM-less version of the µPD78078
µPD78078Y with enhanced serial I/O and limited functions
µ PD780018AY
µ PD780058Y
µ PD78054 with enhanced serial I/O
µ PD78058FY
EMI-noise reduced version of the µ PD78054
µPD78054
µPD780065
µ PD78054Y
µPD78018F with added UART and D/A converter and enhanced I/O
µ PD780078
µ PD780034A
µ PD780024A
µPD78014H
µ PD780078Y
µ PD780034AY
µ PD78018FY
42/44-pin
µPD78018F
µ PD78083
64-pin
µPD780988
80-pin
80-pin
80-pin
64-pin
64-pin
64-pin
64-pin
64-pin
µPD780024A with increased RAM capacity
µ PD780024AY
A µPD780034A with added timer and enhanced serial I/O
µ PD780024A with enhanced A/D converter
µPD78018F with enhanced serial I/O
EMI-noise reduced version of the µPD78018F
Basic subseries for control
On-chip UART, capable of operating at low voltage (1.8 V)
Inverter control
On-chip inverter control circuit and UART. EMI-noise reduced.
FIPTM drive
µ PD780208
µ PD780228
µPD78044F with enhanced I/O and FIP C/D. Display output total: 53
µPD78044H with enhanced I/O and FIP C/D. Display output total: 48
µ PD780232
µPD78044H
For panel control. On-chip FIP C/D. Display output total: 53
80-pin
80-pin
µPD78044F
Basic subseries for driving FIP. Display output total: 34
100-pin
78K/0
Series
100-pin
80-pin
µPD78044F with added N-ch open drain I/O. Display output total: 34
LCD drive
100-pin
µ PD780308
100-pin
µPD78064B
µPD78064
100-pin
µ PD780308Y
µPD78064 with enhanced SIO, and increased ROM, RAM capacity.
EMI-noise reduced version of the µ PD78064
µ PD78064Y
Basic subseries for driving LCDs, on-chip UART
Call ID supported
80-pin
µ PD780841
On-chip Call ID and simple DTMF. EMI-noise reduced.
Bus interface supported
100-pin
µ PD780948
80-pin
µ PD78098B
On-chip D-CAN controller
µ PD78054 with IEBusTM controller added. EMI-noise reduced.
80-pin
µ PD780701Y
On-chip D-CAN/IEBus controller
80-pin
µ PD780833Y
On-chip controller compliant with J1850 (Class 2)
Meter control
100-pin
80-pin
80-pin
80-pin
µPD780958
µPD780955
For industrial meter control
Ultra low-power consumption. On-chip UART.
µPD780973
µPD780824
For automobile meter. On-chip D-CAN controller.
On-chip automobile meter controller/driver
Data Sheet U14045EJ1V0DS00
3
µPD780031AY, 780032AY, 780033AY, 780034AY
The major functional differences among the Y subseries are shown below.
Function ROM Capacity
Configuration of Serial Interface
I/O VDD MIN.
Value
Subseries Name
Control
µPD78078Y
48 K to 60 K
88
1.8 V
61
2.7 V
µPD78070AY
—
µPD780018AY
48 K to 60 K
3-wire with automatic transmit/receive function: 1 ch
Time-division 3-wire:
1 ch
I2C bus (multimaster supported):
1 ch
88
µPD780058Y
24 K to 60 K
3-wire/2-wire/I2C:
1 ch
3-wire with automatic transmit/receive function: 1 ch
3-wire/time-division UART:
1 ch
68
1.8 V
µPD78058FY
48 K to 60 K
69
2.7 V
µPD78054Y
16 K to 60 K
3-wire/2-wire/I2C:
1 ch
3-wire with automatic transmit/receive function: 1 ch
3-wire/UART:
1 ch
µPD780078Y
48 K to 60 K
3-wire:
UART:
3-wire/UART:
I2C bus (multimaster supported):
1
1
1
1
ch
ch
ch
ch
52
1.8 V
µPD780034AY
8 K to 32 K
UART:
3-wire:
I2C bus (multimaster supported):
1 ch
1 ch
1 ch
51
1.8 V
µPD78018FY
8 K to 60 K
3-wire/2-wire/I2C:
1 ch
3-wire with automatic transmit/receive function: 1 ch
53
µPD780308Y
48 K to 60 K
3-wire/2-wire/I2C:
3-wire/time-division UART:
3-wire:
1 ch
1 ch
1 ch
57
µPD78064Y
16 K to 32 K
3-wire/2-wire/I2C:
3-wire/UART:
1 ch
1 ch
µPD780024AY
LCD
3-wire/2-wire/I2C:
1 ch
3-wire with automatic transmit/receive function: 1 ch
3-wire/UART:
1 ch
drive
Remark Functions other than the serial interface are common to the non-Y subseries.
4
Data Sheet U14045EJ1V0DS00
2.0 V
2.0 V
µPD780031AY, 780032AY, 780033AY, 780034AY
OVERVIEW OF FUNCTIONS
µPD780031AY
Part Number
µPD780032AY
µPD780033AY
µPD780034AY
Item
Internal
ROM
8 Kbytes
memory
High-speed RAM
512 bytes
16 Kbytes
24 Kbytes
1024 bytes
Memory space
64 Kbytes
General-purpose registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution
On-chip minimum instruction execution time cycle variable function
time
32 Kbytes
When main system 0.24 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs (@ 8.38-MHz operation)
clock selected
When subsystem
clock selected
122 µs (@ 32.768-kHz operation)
Instruction set
•
•
•
•
16-bit operation
Multiply/divide (8 bits × 8 bits,16 bits ÷ 8 bits)
Bit manipulation (set, reset, test, Boolean operation)
BCD adjust, etc.
I/O ports
Total:
51
• CMOS input:
8
• CMOS I/O:
39
• 5-V-tolerant N-ch open-drain I/O: 4
A/D converter
• 10-bit resolution x 8 channels
• Low-voltage operation available: AVDD = 1.8 to 5.5 V
Serial interface
• 3-wire serial I/O mode:
• UART mode:
• I2C bus mode (multimaster supported):
Timer
•
•
•
•
Timer output
3 (8-bit PWM output capable: 2)
Clock output
• 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz
(@ 8.38-MHz operation with main system clock )
• 32.768 kHz (@ 32.768-kHz operation with subsystem clock)
Buzzer output
1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (@ 8.38-MHz operation with main system clock)
16-bit timer/event counter:
8-bit timer/event counter:
Watch timer:
Watchdog timer:
Vectored
Maskable
Internal: 13, external: 5
interrupt
Non-maskable
Internal: 1
sources
Software
1
Power supply voltage
VDD = 1.8 to 5.5 V
Operating ambient temperature
TA = –40 to +85°C
Package
• 64-pin plastic shrink DIP (750 mils)
• 64-pin plastic QFP (14 × 14 mm)
• 64-pin plastic LQFP (12 × 12 mm)
1
2
1
1
Data Sheet U14045EJ1V0DS00
1 channel
1 channel
1 channel
channel
channels
channel
channel
5
µPD780031AY, 780032AY, 780033AY, 780034AY
CONTENTS
1. PIN CONFIGURATION (Top View) ..................................................................................................... 7
2. BLOCK DIAGRAM .............................................................................................................................10
3. PIN FUNCTIONS ................................................................................................................................ 11
3.1
Port Pins .................................................................................................................................................... 11
3.2
Non-Port Pins ............................................................................................................................................ 12
3.3
Pin I/O Circuits and Recommended Connection of Unused Pins ..................................................... 14
4. MEMORY SPACE ...............................................................................................................................16
5. PERIPHERAL HARDWARE FUNCTION FEATURES .......................................................................17
5.1
Ports ........................................................................................................................................................... 17
5.2
Clock Generator ........................................................................................................................................ 18
5.3
Timer/Counter ........................................................................................................................................... 19
5.4
Clock Output/Buzzer Output Control Circuit ....................................................................................... 23
5.5
A/D Converter ........................................................................................................................................... 24
5.6
Serial Interface .......................................................................................................................................... 25
6. INTERRUPT FUNCTION ....................................................................................................................28
7. EXTERNAL DEVICE EXPANSION FUNCTION ...............................................................................31
8. STANDBY FUNCTION .......................................................................................................................31
9. RESET FUNCTION ............................................................................................................................31
10. MASK OPTION ...................................................................................................................................31
11. INSTRUCTION SET ...........................................................................................................................32
12. ELECTRICAL SPECIFICATIONS ......................................................................................................34
13. PACKAGE DRAWINGS .....................................................................................................................57
14. RECOMMENDED SOLDERING CONDITIONS ................................................................................60
APPENDIX A. DEVELOPMENT TOOLS ................................................................................................62
APPENDIX B. RELATED DOCUMENTS ...............................................................................................65
6
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
1. PIN CONFIGURATION (Top View)
• 64-pin plastic shrink DIP (750 mils)
µPD780031AYCW-×××, 780032AYCW-×××, 780033AYCW-×××, 780034AYCW-×××
P40/AD0
1
64
P67/ASTB
P41/AD1
2
63
P66/WAIT
P42/AD2
3
62
P65/WR
P43/AD3
4
61
P64/RD
P44/AD4
5
60
P75/BUZ
P45/AD5
6
59
P74/PCL
P46/AD6
7
58
P73/TI51/TO51
P47/AD7
8
57
P72/TI50/TO50
P50/A8
9
56
P71/TI01
P51/A9
10
55
P70/TI00/TO0
P52/A10
11
54
P03/INTP3/ADTRG
P53/A11
12
53
P02/INTP2
P54/A12
13
52
P01/INTP1
P55/A13
14
51
P00/INTP0
P56/A14
15
50
VSS1
P57/A15
16
49
X1
VSS0
17
48
X2
VDD0
18
47
IC
P30
19
46
XT1
P31
P32/SDA0
20
21
45
44
XT2
RESET
P33/SCL0
22
43
AVDD
P34
23
42
AVREF
P35
24
41
P10/ANI0
P36
25
40
P11/ANI1
P20/SI30
26
39
P12/ANI2
P21/SO30
27
38
P13/ANI3
P22/SCK30
28
37
P14/ANI4
P23/RxD0
29
36
P15/ANI5
P24/TxD0
30
35
P16/ANI6
P25/ASCK0
31
34
P17/ANI7
VDD1
32
33
AVSS
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.
2. Connect the AVSS pin to VSS0.
Remark When the µPD780031AY, 780032AY, 780033AY, and 780034AY are used in applications where the
noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction
measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to
different ground lines, is recommended.
Data Sheet U14045EJ1V0DS00
7
µPD780031AY, 780032AY, 780033AY, 780034AY
• 64-pin plastic QFP (14 × 14 mm)
µPD780031AYGC-×××-AB8, 780032AYGC-×××-AB8, 780033AYGC-×××-AB8, 780034AYGC-×××-AB8
• 64-pin plastic LQFP (12 × 12 mm)
P72/TI50/TO50
P73/TI51/TO51
P74/PCL
P75/BUZ
P64/RD
P65/WR
P66/WAIT
P67/ASTB
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
µPD780031AYGK-×××-8A8, 780032AYGK-×××-8A8, 780033AYGK-×××-8A8, 780034AYGK-×××-8A8
P01/INTP1
P55/A13
6
43
P00/INTP0
P56/A14
7
42
VSS1
P57/A15
8
41
X1
VSS0
9
40
X2
VDD0
10
39
IC
P30
11
38
XT1
P31
12
37
XT2
P32/SDA0
13
36
RESET
P33/SCL0
14
35
AVDD
P34
15
34
AVREF
P35
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P71/TI01
P10/ANI0
P11/ANI1
P12/ANI2
44
P13/ANI3
5
P14/ANI4
P54/A12
P15/ANI5
P02/INTP2
P16/ANI6
P03/INTP3/ADTRG
45
P17/ANI7
46
4
AVSS
3
P53/A11
VDD1
P52/A10
P25/ASCK0
P70/TI00/TO0
P24/TxD0
47
P23/RxD0
2
P22/SCK30
P51/A9
P21/SO30
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
P20/SI30
1
P36
P50/A8
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.
2. Connect the AVSS pin to VSS0.
Remark When the µPD780031AY, 780032AY, 780033AY, and 780034AY are used in applications where the
noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction
measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to
different ground lines, is recommended.
8
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
A8 to A15:
Address Bus
P70 to P75:
AD0 to AD7:
Address/Data Bus
PCL:
Programmable Clock
ADTRG:
AD Trigger Input
RD:
Read Strobe
ANI0 to ANI7:
Analog Input
RESET:
Reset
ASCK0:
Asynchronous Serial Clock
RxD0:
Receive Data
ASTB:
Address Strobe
SCK30, SCL0:
Serial Clock
AVDD:
Analog Power Supply
SDA0:
Serial Data
AVREF:
Analog Reference Voltage
SI30:
Serial Input
AVSS:
Analog Ground
SO30:
Serial Output
BUZ:
Buzzer Clock
TI00, TI01, TI50, TI51: Timer Input
IC:
Internally Connected
TO0, TO50, TO51:
INTP0 to INTP3:
External Interrupt Input
TxD0:
Transmit Data
P00 to P03:
Port 0
VDD0, V DD1:
Power Supply
P10 to P17:
Port 1
VSS0, VSS1:
Ground
P20 to P25:
Port 2
WAIT:
Wait
P30 to P36:
Port 3
WR:
Write Strobe
P40 to P47:
Port 4
X1, X2:
Crystal (Main System Clock)
P50 to P57:
Port 5
XT1, XT2:
Crystal (Subsystem Clock)
P64 to P67:
Port 6
Data Sheet U14045EJ1V0DS00
Port 7
Timer Output
9
µPD780031AY, 780032AY, 780033AY, 780034AY
2. BLOCK DIAGRAM
TI00/TO0/P70
16-BIT TIMER/
EVENT COUNTER
PORT 0
P00 to P03
TI50/TO50/P72
8-BIT TIMER/
EVENT COUNTER 50
PORT 1
P10 to P17
TI51/TO51/P73
8-BIT TIMER/
EVENT COUNTER 51
PORT 2
P20 to P25
WATCHDOG TIMER
PORT 3
P30 to P36
PORT 4
P40 to P47
PORT 5
P50 to P57
PORT 6
P64 to P67
PORT 7
P70 to P75
TI01/P71
WATCH TIMER
SI30/P20
SO30/P21
SCK30/P22
RxD0/P23
TxD0/P24
ASCK0/P25
78K/0
CPU CORE
ROM
SERIAL
INTERFACE 30
UART0
RAM
SDA0/P32
AD0/P40 to
AD7/P47
A8/P50 to
A15/P57
2
SCL0/P33
ANI0/P10 to
ANI7/P17
AVDD
AVSS
AVREF
INTP0/P00 to
INTP3/P03
I C BUS
EXTERNAL
ACCESS
A/D CONVERTER
INTERRUPT
CONTROL
BUZ/P75
BUZZER OUTPUT
PCL/P74
CLOCK OUTPUT
CONTROL
SYSTEM
CONTROL
VDD0 VDD1 VSS0 VSS1
IC
Remark The internal ROM and RAM capacities differ depending on the product.
10
RD/P64
WR/P65
WAIT/P66
ASTB/P67
Data Sheet U14045EJ1V0DS00
RESET
X1
X2
XT1
XT2
µPD780031AY, 780032AY, 780033AY, 780034AY
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Pin Name
P00
I/O
I/O
Function
Port 0
After
Alternate
Reset
Function
Input
4-bit input/output port
P01
INTP1
Input/output can be specified in 1-bit units.
P02
INTP0
INTP2
An on-chip pull-up resistor can be connected by means of software.
P03
P10 to P17
INTP3/ADTRG
Input
Port 1
Input
ANI0 to ANI7
Input
SI30
8-bit input-only port
P20
I/O
Port 2
6-bit input/output port
P21
SO30
Input/output can be specified in 1-bit units.
P22
SCK30
An on-chip pull-up resistor can be connected by means of software.
P23
RxD0
P24
TxD0
P25
ASCK0
P30
I/O
P31
P32
Port 3
N-ch open-drain input/output port
7-bit input/output port
The mask option can be used to specify the
Input/output can be
connection of an on-chip pull-up resistor to P30, P31.
specified in 1-bit units.
LEDs can be driven directly.
Input
—
SDA0
P33
SCL0
P34
An on-chip pull-up resistor can be
P35
connected by means of software.
—
P36
P40 to P47
I/O
Port 4
Input
AD0 to AD7
Input
A8 to A15
Input
RD
8-bit input/output port
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be connected by means of software.
The interrupt request flag (KRIF) is set to 1 by falling edge detection.
P50 to P57
I/O
Port 5
8-bit input/output port
LEDs can be driven directly.
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be connected by means of software.
P64
P65
P66
I/O
Port 6
4-bit input/output port
WR
Input/output can be specified in 1-bit units.
WAIT
An on-chip pull-up resistor can be connected by means of software.
P67
ASTB
Data Sheet U14045EJ1V0DS00
11
µPD780031AY, 780032AY, 780033AY, 780034AY
3.1 Port Pins (2/2)
Pin Name
P70
I/O
I/O
Function
Port 7
After
Alternate
Reset
Function
Input
6-bit input/output port
P71
TI01
Input/output can be specified in 1-bit units.
P72
TI00/TO0
TI50/TO50
An on-chip pull-up resistor can be connected by means of software.
P73
TI51/TO51
P74
PCL
P75
BUZ
3.2 Non-Port Pins (1/2)
Pin Name
INTP0
I/O
Input
INTP1
Function
External interrupt request input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified
After
Alternate
Reset
Function
Input
P00
P01
INTP2
P02
INTP3
P03/ADTRG
SI30
Input
Serial interface serial data input
Input
P20
SO30
Output
Serial interface serial data output
Input
P21
SDA0
I/O
Serial interface serial data input/output
Input
P32
SCK30
I/O
Serial interface serial clock input/output
Input
P22
SCL0
P33
RxD0
Input
Serial data input for asynchronous serial interface
Input
P23
TxD0
Output
Serial data output for asynchronous serial interface
Input
P24
ASCK0
Input
Serial clock input for asynchronous serial interface
Input
P25
TI00
Input
External count clock input to 16-bit timer (TM0)
Input
P70/TO0
Capture trigger input to capture register (CR01) of 16-bit timer (TM0)
TI01
Capture trigger input to capture register (CR00) of 16-bit timer (TM0)
P71
TI50
External count clock input to 8-bit timer (TM50)
P72/TO50
TI51
External count clock input to 8-bit timer (TM51)
P73/TO51
TO0
Output
16-bit timer (TM0) output
Input
P70/TI00
TO50
8-bit timer (TM50) output (also used for 8-bit PWM output)
Input
P72/TI50
TO51
8-bit timer (TM51) output (also used for 8-bit PWM output)
P73/TI51
PCL
Output
Clock output (for trimming of main system clock and subsystem clock)
Input
P74
BUZ
Output
Buzzer output
Input
P75
Lower address/data bus for expanding memory externally
Input
P40 to P47
AD0 to AD7
I/O
A8 to A15
Output
Higher address bus for expanding memory externally
Input
P50 to P57
RD
Output
Strobe signal output for reading from external memory
Input
P64
WR
Strobe signal output for writing to external memory
WAIT
Input
ASTB
Output
12
P65
Wait insertion at external memory access
Input
P66
Strobe output that externally latches address information output to
ports 4 and 5 to access external memory
Input
P67
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
3.2 Non-Port Pins (2/2)
Pin Name
I/O
Function
After
Alternate
Reset
Function
ANI0 to ANI7
Input
A/D converter analog input
Input
P10 to P17
ADTRG
Input
A/D converter trigger signal input
Input
P03/INTP3
AVREF
Input
A/D converter reference voltage input
—
—
AVDD
—
A/D converter analog power supply. Set potential to that of VDD0 or VDD1.
—
—
AVSS
—
A/D converter ground potential. Set potential to that of VSS0 or VSS1.
—
—
RESET
Input
System reset input
—
—
X1
Input
Connecting crystal resonator for main system clock oscillation
—
—
X2
—
—
—
—
—
—
—
XT1
Input
Connecting crystal resonator for subsystem clock oscillation
XT2
—
VDD0
—
Positive power supply for ports
—
—
VSS0
—
Ground potential of ports
—
—
VDD1
—
Positive power supply (except ports)
—
—
VSS1
—
Ground potential (except ports)
—
—
IC
—
Internally connected. Connect directly to VSS0 or VSS1.
—
—
Data Sheet U14045EJ1V0DS00
13
µPD780031AY, 780032AY, 780033AY, 780034AY
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the input/output circuit configuration of each type, see Figure 3-1.
Table 3-1. Types of Pin Input/Output Circuits
Pin Name
Input/Output
Circuit Type
I/O
Recommended Connection of Unused Pins
P00/INTP0 to P02/INTP2
8-C
Input
Independently connect to VSS0 via a resistor.
P10/ANI0 to P17/ANI7
25
Input
Independently connect to VDD0 or VSS0 via a resistor.
P20/SI30
8-C
I/O
P21/SO30
5-H
P22/SCK30
8-C
P03/INTP3/ADTRG
P23/RxD0
P24/TxD0
5-H
P25/ASCK0
8-C
P30, P31
13-Q
P32/SDA0
13-R
I/O
Independently connect to VDD0 via a resistor.
P33/SCL0
P34
8-C
P35
5-H
P36
8-C
P40/AD0 to P47/AD7
5-H
Independently connect to VDD0 or VSS0 via a resistor.
I/O
Independently connect to VDD0 via a resistor.
P50/A8 to P57/A15
I/O
Independently connect to VDD0 or VSS0 via a resistor.
P64/RD
I/O
P65/WR
P66/WAIT
P67/ASTB
P70/TI00/TO0
8-C
P71/TI01
P72/TI50/TO50
P73/TI51/TO51
P74/PCL
5-H
P75/BUZ
RESET
2
XT1
16
XT2
AVDD
AVREF
Input
Connect to VDD0.
—
—
—
Leave open.
Connect to VDD0.
Connect to VSS0.
AVSS
IC
14
Connect directly to VSS0 or VSS1.
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
Figure 3-1. Pin Input/Output Circuits
TYPE 2
TYPE 13-R
IN/OUT
Data
Output disable
N-ch
IN
VSS0
Schmitt-triggered input with hysteresis characteristics
TYPE 5-H
Pullup
enable
Data
TYPE 16
VDD0
Feedback
cut-off
P-ch
VDD0
P-ch
P-ch
IN/OUT
Output
disable
N-ch
VSS0
XT1
Input
enable
XT2
TYPE 25
TYPE 8-C
VDD0
Pullup
enable
Data
P-ch
P-ch
Comparator
VDD0
–
N-ch
VSS0
VREF (threshold voltage)
P-ch
IN/OUT
Output
disable
+
N-ch
Input
enable
VSS0
TYPE 13-Q
IN
VDD0
 Mask 


 option 
IN/OUT
Data
Output disable
N-ch
VSS0
Input
enable
Data Sheet U14045EJ1V0DS00
15
µPD780031AY, 780032AY, 780033AY, 780034AY
4. MEMORY SPACE
Figure 4-1 shows the memory map of the µPD780031AY, 780032AY, 780033AY, and 780034AY.
Figure 4-1. Memory Map
FFFFH
Special function registers
(SFRs) 256 × 8 bits
FF00H
FEFFH
FEE0H
FEDFH
General-purpose
registers
32 × 8 bits
Internal high-speed
RAMNote
mmmmH
mmmmH – 1
nnnnH
Data memory
space
Reserved
Program area
1000H
0FFFH
CALLF entry area
F800H
F7FFH
0800H
07FFH
Program area
External memory
0080H
007FH
Program memory
space
nnnnH + 1
nnnnH
CALLT table area
Internal ROM
0040H
003FH
Note
Vector table area
0000H
0000H
Note
The internal ROM and internal high-speed RAM capacities differ depending on the product (see the
following table).
Part Number
16
Last Address of Internal ROM
nnnnH
Start Address of Internal High-Speed RAM
mmmmH
µPD780031AY
1FFFH
FD00H
µPD780032AY
3FFFH
µPD780033AY
5FFFH
µPD780034AY
7FFFH
Data Sheet U14045EJ1V0DS00
FB00H
µPD780031AY, 780032AY, 780033AY, 780034AY
5. PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 Ports
The following 3 types of I/O ports are available.
• CMOS input (Port 1):
8
• CMOS input/output (Ports 0, 2 to 7, P34 to P36):
39
• N-ch open-drain input/output (P30 to P33):
4
Total:
51
Table 5-1. Port Functions
Name
Pin Name
Function
Port 0
P00 to P03
I/O port pins. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be connected by means of software.
Port 1
P10 to P17
Dedicated input port pins.
Port 2
P20 to P25
I/O port pins. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be connected by means of software.
Port 3
P30 to P33
N-ch open-drain I/O port pins. Input/output can be specified in 1-bit units.
The mask option can be used to specify the connection of an on-chip pull-up resistor to P30, P31.
LEDs can be driven directly.
P34 to P36
I/O port pins. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be connected by means of software.
Port 4
P40 to P47
I/O port pins. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be connected by means of software.
The interrupt request flag (KRIF) is set to 1 by falling edge detection.
Port 5
P50 to P57
I/O port pins. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be connected by means of software.
LEDs can be driven directly.
Port 6
P64 to P67
I/O port pins. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be connected by means of software.
Port 7
P70 to P75
I/O port pins. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be connected by means of software.
Data Sheet U14045EJ1V0DS00
17
µPD780031AY, 780032AY, 780033AY, 780034AY
5.2 Clock Generator
A system clock generator is incorporated.
The minimum instruction execution time can be changed.
• 0.24 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs (@ 8.38-MHz operation with main system clock)
• 122 µs (@ 32.768-kHz operation with subsystem clock)
Figure 5-1. Clock Generator Block Diagram
XT1
XT2
Subsystem
clock
oscillator
fXT
Watch timer, clock
output function
Prescaler
1
X1
X2
Main system
clock
oscillator
STOP
18
Prescaler
fX
fX
2
fX
22
fX
23
2
fXT
2
Clock to peripheral
hardware
fX
24
Selector
Data Sheet U14045EJ1V0DS00
Standby
control
circuit
Wait control
circuit
CPU clock
(fCPU)
µPD780031AY, 780032AY, 780033AY, 780034AY
5.3 Timer/Counter
Five timer/counter channels are incorporated.
• 16-bit timer/event counter: 1 channel
• 8-bit timer/event counter:
2 channels
• Watch timer:
1 channel
• Watchdog timer:
1 channel
Table 5-2. Operations of Timer/Event Counters
16-Bit Timer/
Event Counter TM0
8-Bit Timer/
Event Counters TM50, TM51
Watch Timer
Watchdog Timer
Interval timer
1 channel
2 channels
1 channelNote 1
1 channelNote 2
External event counter
1 channel
2 channels
—
—
Timer output
1 output
2 outputs
—
—
PPG output
1 output
—
—
—
PWM output
—
2 outputs
—
—
Pulse width measurement
2 inputs
—
—
—
Square wave output
1 output
2 outputs
—
—
One-shot pulse output
1 output
—
—
—
2
2
2
1
Operation mode
Function
Interrupt source
Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.
2. The watchdog timer has watchdog timer and interval timer functions. However, use the watchdog timer
by selecting either the watchdog timer function or the interval timer function.
Data Sheet U14045EJ1V0DS00
19
µPD780031AY, 780032AY, 780033AY, 780034AY
Figure 5-2. Block Diagram of 16-Bit Timer/Event Counter TM0
TI01/P71
Selector
Noise
elimination
circuit
Selector
Internal bus
16-bit capture/compare
register 00 (CR00)
INTTM00
fX
fX/22
fX/26
TI00/TO0/P70
16-bit timer counter 0
(TM0)
Noise
elimination
circuit
Output
control
circuit
Match
Noise
elimination
circuit
TO0/TI00/P70
16-bit capture/compare
register 01 (CR01)
Internal bus
20
Clear
Selector
fX/23
Selector
Match
Data Sheet U14045EJ1V0DS00
INTTM01
µPD780031AY, 780032AY, 780033AY, 780034AY
Figure 5-3. Block Diagram of 8-Bit Timer/Event Counter TM50
Internal bus
Selector
Match
Selector
INTTM50
S
Q
INV
8-bit timer counter OVF
50 (TM50)
Selector
TI50/TO50/P72
fX
fX/22
fX/24
fX/26
fX/28
fX/210
Mask circuit
8-bit compare
register 50 (CR50)
R
TO50/TI50/P72
Clear
S
3
Invert
level
R
Selector
TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50
8-bit timer mode control
register 50 (TMC50)
TCL502 TCL501 TCL500
Timer clock select
register 50 (TCL50)
Internal bus
Figure 5-4. Block Diagram of 8-Bit Timer/Event Counter TM51
Internal bus
8-bit timer
counter 51
(TM51)
Selector
S
Q
INV
OVF
R
INTTM51
Selector
Match
Selector
TI51/TO51/P73
fX/2
fX/23
fX/25
fX/27
fX/29
fX/211
Mask circuit
8-bit compare
register 51
(CR51)
TO51/TI51/P73
Clear
S
3
R
Selector
TCL512 TCL511 TCL510
Timer clock select
register 51 (TCL51)
Invert
level
TCE51 TMC516 TMC514 LVS51 LVR51 TMC511 TOE51
8-bit timer mode control
register 51 (TMC51)
Internal bus
Data Sheet U14045EJ1V0DS00
21
µPD780031AY, 780032AY, 780033AY, 780034AY
Figure 5-5. Watch Timer Block Diagram
fX/2
5-bit counter
9-bit prescaler
fW
fW
24
fW
25
fW
26
fW
27
fW
28
fW
29
INTWT
Clear
Selector
fXT
Selector
Clear
7
INTWTI
WTM7 WTM6 WTM5 WTM4 WTM1 WTM0
Watch timer operation
mode register (WTM)
Internal bus
Figure 5-6. Watchdog Timer Block Diagram
Clock
input
control
circuit
fX/28
RUN
Division
circuit
Division mode
selection circuit
Divided
clock
selection
circuit
Output
control
circuit
INTWDT
RESET
3
WDT mode signal
OSTS2 OSTS1 OSTS0
Oscillation
stabilization time
select register
(OSTS)
WDCS2 WDCS1 WDCS0
Watchdog timer
clock select
register (WDCS)
Internal bus
22
RUN WDTM4 WDTM3
Watchdog timer
mode register
(WDTM)
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
5.4 Clock Output/Buzzer Output Control Circuit
A clock output/buzzer output control circuit (CKU) is incorporated.
Clocks with the following frequencies can be output as clock output.
• 65.5 kHz/131 kHz/262 kHz/524 kHz/1.05 MHz/2.10 MHz/4.19 MHz/8.38 MHz (@ 8.38-MHz operation with main
system clock)
• 32.768 kHz (@ 32.768-kHz operation with subsystem clock)
Clocks with the following frequencies can be output as buzzer output.
• 1.02 kHz/2.05 kHz/4.10 kHz/8.19 kHz (@ 8.38-MHz operation with main system clock)
Figure 5-7. Block Diagram of Clock Output/Buzzer Output Control Circuit CKU
Prescaler
8
4 fX/210 to fX/213
Selector
fX
BZOE
BUZ/P75
BCS0, BCS1
Selector
fX to fX/27
fXT
Clock
control
circuit
PCL/P74
CLOE
BZOE
BCS1
BCS0
CLOE
CCS3
CCS2
CCS1
CCS0
Clock output select register (CKS)
Internal bus
Data Sheet U14045EJ1V0DS00
23
µPD780031AY, 780032AY, 780033AY, 780034AY
5.5 A/D Converter
An A/D converter consisting of eight 10-bit resolution channels is incorporated.
The following two A/D conversion operation start-up methods are available.
• Hardware start
• Software start
Figure 5-8. A/D Converter Block Diagram
Series resistor string
AVDD
Sample & hold circuit
ANI0/P10
AVREF
ANI1/P11
Voltage comparator
ANI2/P12
Tap
selector
ANI3/P13
ANI4/P14
Selector
ANI5/P15
ANI6/P16
Succesive approximation
register (SAR)
ANI7/P17
ADTRG/INTP3/P03
Edge
detection
circuit
Edge
detection
circuit
Control
circuit
INTAD
A/D conversion
result register 0 (ADCR0)
INTP3
Internal bus
24
AVSS
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
5.6 Serial Interface
Three serial interface channels are incorporated.
• Serial interface UART0:
1 channel
• Serial interface SIO30:
1 channel
• Serial interface IIC0:
1 channel
(1) Serial interface UART0
The serial interface UART0 has two modes: asynchronous serial interface (UART) mode and infrared data
transfer mode.
• Asynchronous serial interface (UART) mode
This mode enables full-duplex operation wherein one byte of data starting from the start bit is transmitted
and received.
The on-chip UART-dedicated baud-rate generator enables communication using a wide range of selectable
baud rates. In addition, a baud rate can be also defined by dividing the clock input to the ASCK0 pin.
The UART-dedicated baud-rate generator can also be used to generate a MIDI-standard baud rate (31.25
kbps).
• Infrared data transfer mode
This mode enables pulse output and pulse reception in data format.
This mode can be used for office equipment applications such as personal computers.
Figure 5-9. Block Diagram of Serial Interface UART0
Internal bus
Asynchronous serial
interface mode register 0
(ASIM0)
Receive
buffer
RXB0 register 0
RxD0/P23
RX0
Receive
shift
register 0
TXE0 RXE0 PS01 PS00 CL0
SL0 ISRM0 IRDAM0
Asynchronous serial
interface status
register 0 (ASIS0) Transmit
TXS0 shift
PE0 FE0 OVE0
register 0
TxD0/P24
Receive
control
circuit
(parity
check)
Transmit
INTSER0 control
INTSR0
circuit
(parity
addition)
INTST0
Baud rate
generator
Data Sheet U14045EJ1V0DS00
ASCK0/P25
fX/2 to fX/27
25
µPD780031AY, 780032AY, 780033AY, 780034AY
(2) Serial interface SIO30
The serial interface SIO30 has one mode: 3-wire serial I/O mode.
• 3-wire serial I/O mode (fixed as MSB first)
This is an 8-bit data transfer mode using three lines: a serial clock line (SCK30), serial output line (SO30),
and serial input line (SI30).
Since simultaneous transmit and receive operations are enabled in the 3-wire serial I/O mode, the
processing time for data transfer is reduced.
The first bit in 8-bit data in the serial transfer is fixed as MSB.
The 3-wire serial I/O mode is useful for connection to peripheral I/O devices, display controllers, etc. that
include a clocked serial interface.
Figure 5-10. Block Diagram of Serial Interface SIO30
Internal bus
8
Serial I/O shift register
30 (SIO30)
SI30/P20
SO30/P21
SCK30/P22
Serial clock
counter
Serial clock
control circuit
26
Data Sheet U14045EJ1V0DS00
Interrupt request
signal generator
Selector
INTCSI30
fX/23
fX/24
fX/25
µPD780031AY, 780032AY, 780033AY, 780034AY
(3) Serial interface IIC0
The serial interface IIC0 has the I2C (Inter IC) bus mode (multimaster supported).
• I2C bus mode (multimaster supported)
This is an 8-bit data transfer mode using two lines: a serial clock line (SCL0) and serial data bus line (SDA0).
This mode complies with the I2C bus format, and can output "start condition", "data", and "stop condition"
during transmission via the serial data bus. This data is automatically detected by hardware during
reception.
Since the SCL0 and SDA0 are open-drain outputs in IIC0, pull-up resistors for the serial clock line and the
serial data bus line are required.
Figure 5-11. Block Diagram of Serial Interface IIC0
Internal bus
IIC status register 0
(IICS0)
MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
IIC control register 0
(IICC0)
Slave address
register 0 (SVA0)
SDA0/P32
Noise elimination
circuit
Matched
signal
IIC shift register 0
(IIC0)
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0
SPT0
CLEAR
SET
SO0 latch
D
CL00
Acknowledge
detection
circuit
Data hold
time correction
circuit
N-ch opendrain output
Wake-up control
circuit
Acknowledge
detection circuit
Start condition
detection circuit
Stop condition
detection circuit
SCL0/P33
Noise elimination
circuit
Interrupt request
signal generator
Serial clock counter
INTIIC0
Serial clock wait
control circuit
Serial clock control circuit
N-ch open-drain
output
fX
Prescaler
CLD0 DAD0 SMC0 DFC0 CL00
IIC transfer clock select
register 0 (IICCL0)
Internal bus
Data Sheet U14045EJ1V0DS00
27
µPD780031AY, 780032AY, 780033AY, 780034AY
6. INTERRUPT FUNCTION
A total of 20 interrupt sources are provided, divided into the following three types.
• Non-maskable: 1
• Maskable:
18
• Software:
1
Table 6-1. Interrupt Source List
Interrupt
Default
Type
PriorityNote 1
Name
Nonmaskable
—
Maskable
Software
Interrupt Source
Internal/
Vector Table
Trigger
External
Address
INTWDT
Watchdog timer overflow (with watchdog timer
mode 1 selected)
Internal
0
INTWDT
Watchdog timer overflow (with interval timer
mode selected)
1
INTP0
Pin input edge detection
2
INTP1
0008H
3
INTP2
000AH
4
INTP3
000CH
5
INTSER0
Generation of serial interface UART0
reception error
6
INTSR0
End of serial interface UART0 reception
0010H
7
INTST0
End of serial interface UART0 transmission
0012H
8
INTCSI30
End of serial interface SIO30 transfer
0014H
9
INTIIC0
End of serial interface IIC0 transfer
0016H
10
INTWTI
Reference time interval signal from watch timer
001AH
11
INTTM00
Matching of TM0 and CR00 (when CR00 is
specified as a compare register)
Detection of TI01 pin valid edge (when CR00
is specified as a capture register)
001CH
12
INTTM01
Matching of TM0 and CR01 (when CR01 is
specified as a compare register)
Detection of TI00 pin valid edge (when CR00
is specified as a capture register)
001EH
13
INTTM50
Matching of TM50 and CR50
0020H
14
INTTM51
Matching of TM51 and CR51
0022H
15
INTAD0
End of conversion by A/D converter
0024H
16
INTWT
Watch timer overflow
17
INTKR
Detection of port 4 falling edge
—
BRK
Execution of BRK instruction
0004H
Basic
Configuration
TypeNote 2
(A)
(B)
External
Internal
0006H
000EH
(C)
(B)
0026H
External
0028H
(D)
—
003EH
(E)
Notes 1. Default priority is the priority order when several maskable interrupt requests are generated at the same
time. 0 is the highest and 17 is the lowest.
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1.
28
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
Figure 6-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal bus
Interrupt
request
Vector table
address
generator
Priority control
circuit
Standby release
signal
(B) Internal maskable interrupt
Internal bus
MK
Interrupt
request
PR
IE
ISP
Priority control
circuit
IF
Vector table
address
generator
Standby release
signal
(C) External maskable interrupt (INTP0 to INTP3)
Internal bus
External interrupt
edge enable register
(EGP, EGN)
Interrupt
request
Edge
detection
circuit
MK
IE
IF
PR
Priority control
circuit
ISP
Vector table
address
generator
Standby release
signal
Data Sheet U14045EJ1V0DS00
29
µPD780031AY, 780032AY, 780033AY, 780034AY
Figure 6-1. Basic Configuration of Interrupt Function (2/2)
(D) External maskable interrupt (INTKR)
Internal bus
MK
Interrupt
request
Falling edge
detection circuit
IE
PR
ISP
Priority control
circuit
IF
1 when MEM = 01H
Standby release
signal
(E) Software interrupt
Internal bus
Priority control
circuit
Interrupt
request
IF:
Interrupt request flag
IE:
Interrupt enable flag
ISP:
In-service priority flag
MK:
Interrupt mask flag
PR:
Priority specification flag
MEM: Memory expansion mode register
30
Vector table
address
generator
Data Sheet U14045EJ1V0DS00
Vector table
address
generator
µPD780031AY, 780032AY, 780033AY, 780034AY
7. EXTERNAL DEVICE EXPANSION FUNCTION
The external device expansion function is for connecting external devices to areas other than the internal ROM,
RAM, and SFR. Ports 4 to 6 are used for external device connection.
8. STANDBY FUNCTION
The following two standby modes are available for further reduction of system current consumption.
• HALT mode: In this mode, the CPU operation clock is stopped. The average current consumption can be
reduced by intermittent operation by combining this mode with the normal operation mode.
• STOP mode: In this mode, oscillation of the main system clock is stopped. All the operations performed on
the main system clock are suspended, and only the subsystem clock is used, resulting in
extremely small power consumption. This can be used only when the main system clock is
operating (the subsystem clock oscillation cannot be stopped).
Figure 8-1. Standby Function
CSS = 1
Main system clock
operation
Interrupt
request
Subsystem clock
operation
CSS = 0
HALT
instruction
STOP
instruction
HALT
instruction
Interrupt
request
STOP mode
Main system clock
operation is stopped
Interrupt
request
HALT mode
HALT mode
Clock supply for CPU is stopped,
oscillation is maintained
Clock supply for CPU is stopped,
oscillation is maintained
9. RESET FUNCTION
The following two reset methods are available.
• External reset by RESET signal input
• Internal reset by watchdog timer runaway time detection
10. MASK OPTION
Table 10.1 Pin Mask Option Selection
Pins
P30, P31
Mask Option
An on-chip pull-up resistor can be specified in 1-bit units.
The mask option can be used to specify the connection of an on-chip pull-up resistor to P30, P31, in 1-bit units.
Data Sheet U14045EJ1V0DS00
31
µPD780031AY, 780032AY, 780033AY, 780034AY
11. INSTRUCTION SET
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR,
ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2nd
Operand
[HL + byte]
#byte
1st
Operand
A
rNote
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL + B]
$addr16
1
None
[HL + C]
A
ADD
MOV
MOV
MOV
MOV
ADDC
XCH
XCH
XCH
XCH
SUB
ADD
ADD
SUBC
ADDC
AND
MOV
MOV
MOV
ROR
XCH
XCH
XCH
ROL
ADD
ADD
ADD
RORC
ADDC
ADDC
ADDC
ADDC
ROLC
SUB
SUB
SUB
SUB
SUB
SUBC
OR
SUBC
SUBC
SUBC
SUBC
XOR
AND
AND
AND
AND
AND
CMP
OR
OR
OR
OR
OR
MOV
r
MOV
XOR
XOR
XOR
XOR
XOR
CMP
CMP
CMP
CMP
CMP
INC
DEC
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
DBNZ
B, C
sfr
MOV
MOV
saddr
MOV
MOV
DBNZ
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16
MOV
PSW
MOV
MOV
PUSH
POP
[DE]
MOV
[HL]
MOV
ROR4
ROL4
[HL + byte]
MOV
[HL + B]
[HL + C]
X
MULU
C
DIVUW
Note
32
Except r = A
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
1st Operand
#word
rpNote
AX
MOVW
ADDW
SUBW
CMPW
AX
MOVW
MOVWNote
sfrp
MOVW
MOVW
saddrp
MOVW
MOVW
!addr16
Note
MOVW
saddrp
!addr16
MOVW
MOVW
SP
None
MOVW
XCHW
rp
SP
sfrp
INCW, DECW
PUSH, POP
MOVW
MOVW
MOVW
Only when rp = BC, DE or HL
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand
A.bit
1st Operand
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
$addr16
None
A.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
sfr.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
saddr.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
PSW.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
[HL].bit
MOV1
BT
BF
BTCLR
SET1
CLR1
CY
MOV1
AND1
MOV1
AND1
MOV1
AND1
MOV1
AND1
MOV1
AND1
SET1
CLR1
OR1
XOR1
OR1
XOR1
OR1
XOR1
OR1
XOR1
OR1
XOR1
NOT1
(4) Call instructions/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd Operand
1st Operand
Basic instruction
AX
BR
!addr16
CALL
BR
!addr11
CALLF
[addr5]
CALLT
$addr16
BR, BC, BNC
BZ, BNZ
BT, BF
BTCLR
DBNZ
Compound
instruction
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
Data Sheet U14045EJ1V0DS00
33
µPD780031AY, 780032AY, 780033AY, 780034AY
12. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Input voltage
Symbol
Test Conditions
VDD
Unit
–0.3 to +6.5
V
AVDD
–0.3 to VDD +
0.3Note
V
AVREF
–0.3 to VDD + 0.3Note
V
AVSS
–0.3 to +0.3
V
VI1
P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47,
P50 to P57, P64 to P67, P70 to P75, X1, X2, XT1, XT2,
RESET
VI2
P30 to P33
N-ch open-drain Without pull-up resistor
With pull-up resistor
Output voltage
Ratings
VO
–0.3 to VDD +
V
–0.3 to +6.5
V
–0.3 to VDD + 0.3Note
V
0.3Note
V
–0.3 to VDD +
0.3Note
Analog input voltage
VAN
P10 to P17
Output current,
high
IOH
Per pin
–10
Total for P00 to P03, P40 to P47, P50 to P57, P64 to P67, P70 to P75
–15
mA
Total for P20 to P25, P30 to P36
–15
mA
Per pin for P00 to P03, P20 to P25, P34 to
P36, P40 to P47, P64 to P67, P70 to P75
20
mA
Per pin for P30 to P33, P50 to P57
30
mA
Total for P00 to P03, P40 to P47,
P64 to P67, P70 to P75
50
mA
Total for P20 to P25
20
mA
Total for P30 to P36
100
mA
Output current,
low
IOL
Analog input pin
0.3Note
Total for P50 to P57
Operating ambient
TA
AVSS – 0.3 to AVREF +
and –0.3 to VDD + 0.3Note
V
mA
100
mA
–40 to +85
°C
–65 to +150
°C
temperature
Storage
temperature
Tstg
Note 6.5 V or below
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
34
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input
capacitance
CIN
f = 1 MHz
Unmeasured pins returned to 0 V.
15
pF
I/O
capacitance
CIO
f = 1 MHz
Unmeasured pins
returned to 0 V.
15
pF
20
pF
P00
P34
P50
P70
to
to
to
to
P03, P20 to P25,
P36, P40 to P47,
P57, P64 to P67,
P75
P30 to P33
Remark
Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Main System Clock Oscillator Characteristics (TA = –40 to 85°C, VDD = 1.8 to 5.5 V)
Resonator
Ceramic
resonator
Recommended
Circuit
X2 IC
X1
C1
Crystal
resonator
X1
C1
External
clock
X1
C2
X2 IC
C2
X2
µ PD74HCU04
Parameter
Test Conditions
Oscillation
frequency (fX)Note 1
VDD = 4.0 to 5.5 V
Oscillation
stabilization timeNote 2
After VDD reaches
oscillation voltage range
MIN.
Oscillation
frequency (fX)Note 1
VDD = 4.0 to 5.5 V
Oscillation
stabilization timeNote 2
VDD = 4.0 to 5.5 V
X1 input
frequency (fX)Note 1
VDD = 4.0 to 5.5 V
X1 input
high-/low-level width
(tXH, tXL)
VDD = 4.0 to 5.5 V
MIN.
TYP.
MAX.
Unit
1.0
8.38
MHz
1.0
5.0
4
ms
1.0
8.38
MHz
1.0
5.0
10
ms
30
1.0
8.38
1.0
5.0
50
500
85
500
MHz
ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
Data Sheet U14045EJ1V0DS00
35
µPD780031AY, 780032AY, 780033AY, 780034AY
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Crystal
resonator
Recommended Circuit
XT2
XT1 IC
R
C4
External
clock
C3
XT2
Parameter
Oscillation
frequency (fXT)Note 1
Oscillation
stabilization timeNote 2
XT1
µPD74HCU04
Test Conditions
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.2
2
s
VDD = 4.0 to 5.5 V
10
XT1 input
frequency (fXT)Note 1
32
38.5
kHz
XT1 input
high-/low-level width
(tXTH , tXTL)
5
15
µs
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
36
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
Recommended Oscillator Constant
Main system clock: Ceramic resonator (TA = –40 to +85°C)
Manufacturer
Part Number
Frequency
Recommended Circuit Constant
(MHz)
Murata Mfg.
Co., Ltd.
TDK
C1 (pF)
C2 (pF)
Oscillation Voltage Range
MIN. (V)
MAX. (V)
CSB1000J
1.00
100
100
1.8
5.5
CSA2.00MG040
2.00
100
100
1.8
5.5
CST2.00MG040
2.00
On-chip
On-chip
1.8
5.5
CSA3.58MG
3.58
30
30
1.8
5.5
CST3.58MGW
3.58
On-chip
On-chip
1.8
5.5
CSA4.19MG
4.19
30
30
1.8
5.5
CST4.19MGW
4.19
On-chip
On-chip
1.8
5.5
CSA5.00MG
5.00
30
30
1.8
5.5
CST5.00MGW
5.00
On-chip
On-chip
1.8
5.5
CSA8.00MTZ
8.00
30
30
4.0
5.5
CST8.00MTW
8.00
On-chip
On-chip
4.0
5.5
CSA8.00MTZ093
8.00
30
30
4.0
5.5
CST8.00MTW093
8.00
On-chip
On-chip
4.0
5.5
CSA8.38MTZ
8.38
30
30
4.0
5.5
CST8.38MTW
8.38
On-chip
On-chip
4.0
5.5
CSA8.38MTZ093
8.38
30
30
4.0
5.5
CST8.38MTW093
8.38
On-chip
On-chip
4.0
5.5
CCR3.58MC3
3.58
On-chip
On-chip
1.8
5.5
CCR4.19MC3
4.19
On-chip
On-chip
1.8
5.5
CCR5.0MC3
5.00
On-chip
On-chip
1.8
5.5
CCR8.0MC5
8.00
On-chip
On-chip
4.0
5.5
CCR8.38MC5
8.38
On-chip
On-chip
4.0
5.5
Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation.
Oscillation frequency precision is not guaranteed.
For applications requiring oscillation
frequency precision, the oscillation frequency must be adjusted on the implementation circuit.
For details, please contact directly the manufacturer of the resonator you will use.
Data Sheet U14045EJ1V0DS00
37
µPD780031AY, 780032AY, 780033AY, 780034AY
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Output current,
high
IOH
Output current,
low
IOL
Test Conditions
MIN.
TYP.
MAX.
Unit
Per pin
–1
mA
All pins
–15
mA
10
mA
Per pin for P00 to P03, P20 to P25, P34 to P36,
P40 to P47, P64 to P67, P70 to P75
Per pin for P30 to P33, P50 to P57
15
mA
Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75
20
mA
Total for P20 to P25
10
mA
Total for P30 to P36
70
mA
Total for P50 to P57
Input voltage,
high
VIH1
P10 to P17, P21, P24, P35,
P40 to P47, P50 to P57,
P64 to P67, P74, P75
VDD = 2.7 to 5.5 V
VIH2
P00 to P03, P20, P22, P23, P25,
P34, P36, P70 to P73, RESET
VDD = 2.7 to 5.5 V
VIH3
P30 to P33
(N-ch open-drain)
VDD = 2.7 to 5.5 V
X1, X2
VDD = 2.7 to 5.5 V
VIH4
VIH5
Input voltage,
low
VIL1
VIL2
VIL3
V
0.8VDD
VDD
V
0.8VDD
VDD
V
0.85VDD
VDD
V
0.7VDD
5.5
V
0.8VDD
5.5
V
VDD – 0.5
VDD
V
VDD – 0.2
VDD
V
0.8VDD
VDD
V
0.9VDD
VDD
V
0
0.3VDD
V
0
0.2VDD
V
0
0.2VDD
V
0
0.15VDD
V
P10 to P17, P21, P24, P35,
P40 to P47, P50 to P57,
P64 to P67, P74, P75
VDD = 2.7 to 5.5 V
P00 to P03, P20, P22, P23, P25,
P34, P36, P70 to P73, RESET
VDD = 2.7 to 5.5 V
P30 to P33
4.0 V ≤ VDD ≤ 5.5 V
0
0.3VDD
V
2.7 V ≤ VDD < 4.0 V
0
0.2VDD
V
1.8 V ≤ VDD < 2.7 V
0
0.1VDD
V
0.4
V
X1, X2
VDD = 2.7 to 5.5 V
0
0
0.2
V
VIL5
XT1, XT2
VDD = 4.0 to 5.5 V
0
0.2VDD
V
0
0.1VDD
V
VDD = 4.0 to 5.5 V, IOH = –1 mA
VDD – 1.0
VDD
V
IOH = –100 µA
VDD – 0.5
VDD
V
2.0
V
2.0
V
P00 to P03, P20 to P25, P34 to P36, VDD = 4.0 to 5.5 V,
P40 to P47, P64 to P67, P70 to P75 IOL = 1.6 mA
0.4
V
IOL = 400 µA
0.5
V
VOH1
Output voltage,
low
VOL1
P30 to P33
P50 to P57
VOL2
38
VDD = 4.0 to 5.5 V
mA
VDD
VIL4
Output voltage,
high
Remark
XT1, XT2
70
0.7VDD
VDD = 4.0 to 5.5 V,
IOL = 15 mA
0.4
Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Input leakage
current, high
Symbol
Test Conditions
TYP.
MAX.
Unit
VIN = VDD
P00 to P03, P10 to P17, P20 to P25,
P34 to P36, P40 to P47, P50 to P57,
P64 to P67, P70 to P75,
RESET
3
µA
X1, X2, XT1, XT2
20
µA
ILIH3
VIN = 5.5 V
P30 to P33Note
3
µA
ILIL1
VIN = 0 V
P00 to P03, P10 to P17, P20 to P25,
P34 to P36, P40 to P47, P50 to P57,
P64 to P67, P70 to P75,
RESET
–3
µA
–20
µA
ILIH1
ILIH2
Input leakage
MIN.
current, low
ILIL2
X1, X2, XT1, XT2
–3
µA
Output leakage
current, high
ILOH
VOUT = VDD
3
µA
Output leakage
current, low
ILOL
VOUT = 0 V
–3
µA
Mask option
pull-up resistance
R1
VIN = 0 V,
P30, P31
15
30
90
kΩ
Software pullup resistance
R2
VIN = 0 V,
P00 to P03, P20 to P25, P34 to P36, P40 to P47,
P50 to P57, P64 to P67, P70 to P75
15
30
90
kΩ
ILIL3
Note
Remark
P30 to P33
Note
When pull-up resistors are not connected to P30, P31 (specified by the mask option).
Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U14045EJ1V0DS00
39
µPD780031AY, 780032AY, 780033AY, 780034AY
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Power supply
currentNote 1
Symbol
IDD1
TYP.
MAX.
Unit
8.38-MHz
VDD = 5.0V±10%Note 2
crystal oscillation
operating mode
Test Conditions
When A/D converter is
stopped
5.5
11
mA
When A/D converter is
operating
6.5
13
mA
VDD = 3.0V±10%Note 2
When A/D converter is
stopped
2
4
mA
When A/D converter is
operating
3
6
mA
When A/D converter is
stopped
0.4
1.5
mA
When A/D converter is
operating
1.4
4.2
mA
8.38-MHz
VDD = 5.0V±10%Note 2
crystal oscillation
HALT mode
When peripheral functions
are stopped
1.1
2.2
mA
4.7
mA
5.00-MHz
VDD = 3.0V±10%Note 2
crystal oscillation
HALT mode
When peripheral functions
are stopped
0.7
mA
1.7
mA
VDD = 2.0V±10%Note 3
When peripheral functions
are stopped
0.4
mA
1.1
mA
5.00-MHz
crystal oscillation
operating mode
VDD = 2.0V±10%Note 3
IDD2
MIN.
When peripheral functions
are operating
0.35
When peripheral functions
are operating
0.15
When peripheral functions
are operating
IDD3
IDD4
IDD5
32.768-kHz crystal oscillation
operating modeNote 4
32.768-kHz crystal oscillation
HALT modeNote 4
XT1 = 0V STOP mode
When feedback resistor is not used
VDD = 5.0 V ±10%
40
80
µA
VDD = 3.0 V ±10%
20
40
µA
VDD = 2.0 V ±10%
10
20
µA
VDD = 5.0 V ±10%
30
60
µA
VDD = 3.0 V ±10%
6
18
µA
VDD = 2.0 V ±10%
2
10
µA
VDD = 5.0 V ±10%
0.1
30
µA
VDD = 3.0 V ±10%
0.05
10
µA
VDD = 2.0 V ±10%
0.05
10
µA
Notes 1. Total current through the internal power supply (VDD0, VDD1), including the peripheral operation current
(except the current through pull-up resistors of ports and the AVREF pin).
2. When the processor clock control register (PCC) is set to 00H.
3. When PCC is set to 02H.
4. When main system clock operation is stopped.
40
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
AC Characteristics
(1) Basic Operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Cycle time
(Min. instruction
execution time)
Symbol
TCY
Test Conditions
Operating with
main system clock
MIN.
TYP.
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
0.24
16
µs
2.7 V ≤ VDD < 4.0 V
0.4
16
µs
1.6
16
µs
125
µs
Operating with subsystem clock
103.9Note 1
4.0 V ≤ VDD ≤ 5.5 V
2/fsam + 0.1Note2
µs
2.7 V ≤ VDD < 4.0 V
2/fsam + 0.2Note2
µs
2/fsam + 0.5Note2
µs
122
TI00, TI01 input
high-/low-level
width
tTIH0, tTIL0
TI50, TI51 input
frequency
fTI5
VDD = 2.7 to 5.5 V
0
4
MHz
0
275
kHz
TI50, TI51 input
tTIH5, tTIL5
VDD = 2.7 to 5.5 V
100
ns
1.8
ns
1
µs
2
µs
10
µs
20
µs
high-/low-level
width
Interrupt request
input high-/low
-level width
tINTH, tINTL
RESET
low-level width
tRSL
INTP0 to INTP3,
P40 to P47
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
Notes 1. Value when an external clock is used. When a crystal resonator is used, it is 114 µs (MIN.).
2. Selection of fsam = fX, fX/4, fX/64 is possible using bits 0 and 1 (PRM00, PRM01) of prescaler mode register
0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes fsam = fX/8.
Data Sheet U14045EJ1V0DS00
41
µPD780031AY, 780032AY, 780033AY, 780034AY
TCY vs. VDD (main system clock operation)
16.0
Cycle time TCY [ µ s]
10.0
Operation
guaranteed
range
5.0
2.0
1.6
1.0
0.4
0.24
0.1
0
1.0
2.0
1.8
3.0
4.0
2.7
Supply voltage VDD [V]
42
Data Sheet U14045EJ1V0DS00
5.0 5.5 6.0
µPD780031AY, 780032AY, 780033AY, 780034AY
(2) Read/Write Operation (TA = –40 to + 85°C, VDD = 4.0 to 5.5 V)
(1/3)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
20
ns
Address hold time
tADH
6
ns
Data input time from address
tADD1
(2 + 2n)tCY – 54
ns
tADD2
(3 + 2n)tCY – 60
ns
100
ns
Address output time from RD↓
tRDAD
0
Data input time from RD↓
tRDD1
(2 + 2n)tCY – 87
ns
tRDD2
(3 + 2n)tCY – 93
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 33
ns
tRDL2
(2.5 + 2n)tCY – 33
ns
WAIT↓ input time from RD↓
WAIT↓ input time from WR↓
tRDWT1
tCY – 43
ns
tRDWT2
tCY – 43
ns
tWRWT
tCY – 25
ns
(2 + 2n)tCY
ns
WAIT low-level width
tWTL
(0.5 + n)tCY + 10
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
6
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 15
ns
RD↓ delay time from ASTB↓
tASTRD
6
ns
WR↓ delay time from ASTB↓
tASTWR
2tCY – 15
ns
ASTB↑ delay time from
tRDAST
0.8tCY – 15
1.2tCY
ns
Address hold time from
RD↑ at external fetch
tRDADH
0.8tCY – 15
1.2tCY + 30
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
10
60
ns
Address hold time from WR↑
tWRADH
0.8tCY – 15
1.2tCY + 30
ns
RD↑ delay time from WAIT↑
tWTRD
0.8tCY
2.5tCY + 25
ns
WR↑ delay time from WAIT↑
tWTWR
0.8tCY
2.5tCY + 25
ns
RD↑ at external fetch
Remarks
1.
ns
tCY = TCY/4
2.
n indicates the number of waits.
3.
CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and
ASTB pins.)
Data Sheet U14045EJ1V0DS00
43
µPD780031AY, 780032AY, 780033AY, 780034AY
(2) Read/Write Operation (TA = –40 to + 85°C, VDD = 2.7 to 4.0 V)
(2/3)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
30
ns
Address hold time
tADH
10
ns
Data input time from address
tADD1
(2 + 2n)tCY – 108
ns
tADD2
(3 + 2n)tCY – 120
ns
200
ns
Address output time from RD↓
tRDAD
0
Data input time from RD↓
tRDD1
(2 + 2n)tCY – 148
ns
tRDD2
(3 + 2n)tCY – 162
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 40
ns
tRDL2
(2.5 + 2n)tCY – 40
ns
WAIT↓ input time from RD↓
WAIT↓ input time from WR↓
tRDWT1
tCY – 75
ns
tRDWT2
tCY – 60
ns
tWRWT
tCY – 50
ns
(2 + 2n)tCY
ns
WAIT low-level width
tWTL
(0.5 + 2n)tCY + 10
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
10
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 30
ns
RD↓ delay time from ASTB↓
tASTRD
10
ns
WR↓ delay time from ASTB↓
tASTWR
2tCY – 30
ns
ASTB↑ delay time from
RD↑ at external fetch
tRDAST
0.8tCY – 30
1.2tCY
ns
Address hold time from
tRDADH
0.8tCY – 30
1.2tCY + 60
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
20
120
ns
Address hold time from WR↑
tWRADH
0.8tCY – 30
1.2tCY + 60
ns
RD↑ delay time from WAIT↑
tWTRD
0.5tCY
2.5tCY + 50
ns
WR↑ delay time from WAIT↑
tWTWR
0.5tCY
2.5tCY + 50
ns
RD↑ at external fetch
Remarks
1.
tCY = TCY/4
2.
n indicates the number of waits.
3.
CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT,
and ASTB pins.)
44
ns
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
(2) Read/Write Operation (TA = –40 to + 85°C, VDD = 1.8 to 2.7 V)
(3/3)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
120
ns
Address hold time
tADH
20
ns
Data input time from address
tADD1
(2 + 2n)tCY – 233
ns
tADD2
(3 + 2n)tCY – 240
ns
400
ns
Address output time from RD↓
tRDAD
0
Data input time from RD↓
tRDD1
(2 + 2n)tCY – 325
ns
tRDD2
(3 + 2n)tCY – 332
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 92
ns
tRDL2
(2.5 + 2n)tCY – 92
ns
WAIT↓ input time from RD↓
WAIT↓ input time from WR↓
WAIT low-level width
tRDWT1
tCY – 350
ns
tRDWT2
tCY – 132
ns
tWRWT
tCY – 100
ns
(2 + 2n)tCY
ns
tWTL
(0.5 + 2n)tCY + 10
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
20
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 60
ns
RD↓ delay time from ASTB↓
tASTRD
20
ns
WR↓ delay time from ASTB↓
tASTWR
2tCY – 60
ns
ASTB↑ delay time from
RD↑ at external fetch
tRDAST
0.8tCY – 60
1.2tCY
ns
Address hold time from
tRDADH
0.8tCY – 60
1.2tCY + 120
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
40
240
ns
Address hold time from WR↑
tWRADH
0.8tCY – 60
1.2tCY + 120
ns
RD↑ delay time from WAIT↑
tWTRD
0.5tCY
2.5tCY + 100
ns
WR↑ delay time from WAIT↑
tWTWR
0.5tCY
2.5tCY + 100
ns
RD↑ at external fetch
Remarks
ns
1.
tCY = TCY/4
2.
n indicates the number of waits.
3.
CL = 100pF (CL indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT, and
ASTB pins.)
Data Sheet U14045EJ1V0DS00
45
µPD780031AY, 780032AY, 780033AY, 780034AY
(3) Serial Interface (TA = –40 to + 85°C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (SCK30 ... Internal clock output)
Parameter
SCK30 cycle time
SCK30 high-/low-level
Symbol
tKCY1
tKH1, tKL1
Test Conditions
tSIK1
(to SCK30↑)
SI30 hold time
(from SCK30↑)
tKSI1
SO30 output
delay time from
SCK30↓
tKSO1
TYP.
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
954
ns
2.7 V ≤ VDD < 4.0 V
1600
ns
3200
ns
tKCY1/2 – 50
ns
tKCY1/2 – 100
ns
4.0 V ≤ VDD ≤ 5.5V
100
ns
2.7 V ≤ VDD < 4.0V
150
ns
300
ns
400
ns
VDD = 4.0 to 5.5 V
width
SI30 setup time
MIN.
C = 100 pFNote
300
ns
MAX.
Unit
Note C is the load capacitance of the SCK30 and SO30 output lines.
(b) 3-wire serial I/O mode (SCK30 ... External clock input)
Parameter
SCK30 cycle time
SCK30 high-/low-level
Symbol
tKCY2
tKH2, tKL2
width
Test Conditions
MIN.
TYP.
4.0 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.0 V
1600
ns
3200
ns
4.0 V ≤ VDD ≤ 5.5 V
400
ns
2.7 V ≤ VDD < 4.0 V
800
ns
1600
ns
SI30 setup time
(to SCK30↑)
tSIK2
100
ns
SI30 hold time
(from SCK30↑)
tKSI2
400
ns
SO30 output
delay time from
SCK30↓
tKSO2
C = 100 pFNote
Note C is the load capacitance of the SO30 output line.
46
Data Sheet U14045EJ1V0DS00
300
ns
µPD780031AY, 780032AY, 780033AY, 780034AY
(c) UART mode (Dedicated baud-rate generator output)
Parameter
Symbol
Transfer rate
Test Conditions
MIN.
TYP.
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
131031
bps
2.7 V ≤ VDD < 4.0 V
78125
bps
39063
bps
MAX.
Unit
(d) UART mode (External clock input)
Parameter
ASCK0 cycle time
ASCK0 high-/low-level width
Symbol
tKCY3
Test Conditions
MIN.
TYP.
4.0 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.0 V
1600
ns
3200
ns
tKH3,
4.0 V ≤ VDD ≤ 5.5 V
400
ns
tKL3
2.7 V ≤ VDD < 4.0 V
800
ns
1600
ns
Transfer rate
4.0 V ≤ VDD ≤ 5.5 V
39063
bps
2.7 V ≤ VDD < 4.0 V
19531
bps
9766
bps
MAX.
Unit
(e) UART mode (Infrared ray data transfer mode)
Parameter
Symbol
Test Conditions
MIN.
Transfer rate
VDD = 4.0 to 5.5 V
131031
bps
Bit rate allowable error
VDD = 4.0 to 5.5 V
±0.87
%
Output pulse width
VDD = 4.0 to 5.5 V
1.2
0.24/fbrNote
µs
Input pulse width
VDD = 4.0 to 5.5 V
4/fX
Note
µs
fbr: Specified baud rate
Data Sheet U14045EJ1V0DS00
47
µPD780031AY, 780032AY, 780033AY, 780034AY
(f) I2C bus Mode
Standard Mode
Parameter
High-Speed Mode
Symbol
Unit
MIN.
MAX.
MIN.
MAX.
SCL0 clock frequency
fCLK
0
100
0
400
kHz
Bus-free time
(between stop and start condition)
tBUF
4.7
—
1.3
—
µs
Hold timeNote 1
tHD:STA
4.0
—
0.6
—
µs
SCL0 clock low-level width
tLOW
4.7
—
1.3
—
µs
SCL0 clock high-level width
tHIGH
4.0
—
0.6
—
µs
Start/restart condition setup time
tSU:STA
4.7
—
0.6
—
µs
Data hold time
tHD:DAT
5.0
—
—
—
µs
—
0Note 2
0.9Note 3
µs
—
100Note 4
CBUS compatible master
I2C
0Note 2
bus
Data setup time
tSU:DAT
SDA0 and SCL0 signal rise time
tR
250
—
1000
—
ns
Note 5
300
ns
0.1CbNote 5
300
ns
20 + 0.1Cb
SDA0 and SCL0 signal fall time
tF
—
300
20 +
Stop condition setup time
tSU:STO
4.0
—
0.6
—
µs
Spike pulse width controlled by input filter
tSP
—
—
0
50
ns
Capacitive load per bus line
Cb
—
400
—
400
pF
Notes 1. In the start condition, the first clock pulse is generated after this hold time.
2. To fill in the undefined area of the SCL0 falling edge, it is necessary for the device to internally provide
at least 300 ns of hold time for the SDA0 signal (which is VIHmin. of the SCL0 signal).
3. If the device does not extend the SCL0 signal low hold time (tLOW), only maximum data hold time tHD:DAT
needs to be fulfilled.
4. The high-speed mode I2C bus is available in a standard mode I2C bus system. At this time, the conditions
described below must be satisfied.
• If the device does not extend the SCL0 signal low state hold time
tSU:DAT ≥ 250 ns
• If the device extends the SCL0 signal low state hold time
Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU:DAT
= 1000 + 250 = 1250 ns by standard mode I2C bus specification).
5. Cb: Total capacitance per bus line (unit: pF)
48
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
AC Timing Test Points (Excluding X1, XT1 Inputs)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Test points
Clock Timing
1/fX
tXL
tXH
VIH4 (MIN.)
VIL4 (MAX.)
X1 Input
1/fXT
tXTL
tXTH
VIH5 (MIN.)
VIL5 (MAX.)
XT1 Input
TI Timing
tTIL0
tTIH0
TI00, TI01
1/fTI5
tTIL5
tTIH5
TI50, TI51
Data Sheet U14045EJ1V0DS00
49
µPD780031AY, 780032AY, 780033AY, 780034AY
Read/Write Operation
External fetch (no wait):
A8 to A15
Higher 8-bit address
tADD1
AD0 to AD7
Lower-8-bit address
tADS
tADH
Hi-Z
Instruction code
tRDAD
tRDD1
tRDADH
tASTH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
External fetch (wait insertion):
A8 to A15
Higher 8-bit address
tADD1
AD0 to AD7
Hi-Z
Lower 8-bit address
tADS
tADH
tRDAD
Instruction code
tRDADH
tRDD1
tASTH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
WAIT
tRDWT1
50
tWTL
Data Sheet U14045EJ1V0DS00
tWTRD
µPD780031AY, 780032AY, 780033AY, 780034AY
External data access (no wait):
A8 to A15
Higher 8-bit address
tADD2
AD0 to AD7
Hi-Z
tRDAD
tRDD2
Lower 8-bit address
tADS
tADH
Read data
tASTH
Hi-Z
Write data
tRDH
ASTB
RD
tASTRD
tRDWD
tRDL2
tWDS
tWDH
tWRADH
tWRWD
WR
tASTWR
tWRL1
External data access (wait insertion):
A8 to A15
Higher 8-bit address
tADD2
AD0 to AD7
Lower 8-bit
address
tADS tADH
tASTH
Hi-Z
Read data
Hi-Z
Write data
tRDAD
tRDH
tRDD2
ASTB
tASTRD
RD
tRDWD
tRDL2
tWDH
tWDS
tWRWD
WR
tASTWR
tWRL1
tWRADH
WAIT
tRDWT2
tWTL
tWTRD
tWTL
tWRWT
Data Sheet U14045EJ1V0DS00
tWTWR
51
µPD780031AY, 780032AY, 780033AY, 780034AY
Serial Transfer Timing
3-wire serial I/O mode:
tKCYm
tKLm
tKHm
SCK30
tSIKm
SI30
tKSIm
Input data
tKSOm
SO30
Output data
m = 1, 2
UART mode (external clock input):
t KCY3
t KL3
t KH3
ASCK0
52
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
I2C Bus Mode:
tLOW
tR
SCL0
tHD:DAT
tHD:STA
tHIGH
tSU:DAT
tF
tSU:STA
tHD:STA
tSP
tSU:STO
SDA0
tBUF
Stop
condition
Start
condition
Restart
condition
Data Sheet U14045EJ1V0DS00
Stop
condition
53
µPD780031AY, 780032AY, 780033AY, 780034AY
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = AVREF = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
10
10
10
bit
4.0 V ≤ AVREF ≤ 5.5 V
±0.2
±0.4
%FSR
2.7 V ≤ AVREF < 4.0 V
±0.3
±0.6
%FSR
1.8 V ≤ AVREF < 2.7 V
±0.6
±1.2
%FSR
Resolution
Overall errorNotes 1, 2
Conversion time
Zero-scale
Full-scale
tCONV
offsetNotes 1, 2
offsetNotes 1, 2
Integral linearity
errorNote 1
Differential linearity
errorNote 1
4.0 V ≤ AVREF ≤ 5.5 V
14
96
µs
2.7 V ≤ AVREF < 4.0 V
19
96
µs
1.8 V ≤ AVREF < 2.7 V
28
96
µs
4.0 V ≤ AVREF ≤ 5.5 V
±0.4
%FSR
2.7 V ≤ AVREF < 4.0 V
±0.6
%FSR
1.8 V ≤ AVREF < 2.7 V
±1.2
%FSR
4.0 V ≤ AVREF ≤ 5.5 V
±0.4
%FSR
2.7 V ≤ AVREF < 4.0 V
±0.6
%FSR
1.8 V ≤ AVREF < 2.7 V
±1.2
%FSR
4.0 V ≤ AVREF ≤ 5.5 V
±2.5
LSB
2.7 V ≤ AVREF < 4.0 V
±4.5
LSB
1.8 V ≤ AVREF < 2.7 V
±8.5
LSB
4.0 V ≤ AVREF ≤ 5.5 V
±1.5
LSB
2.7 V ≤ AVREF < 4.0 V
±2.0
LSB
1.8 V ≤ AVREF < 2.7 V
Analog input voltage
VIAN
Reference voltage
AVREF
Resistance between AVREF and AVSS
RREF
When A/D conversion is not performed
Notes 1. Excludes quantization error (±1/2 LSB).
2. Shown as a percentage of the full scale value.
54
Data Sheet U14045EJ1V0DS00
±3.5
LSB
0
AVREF
V
1.8
AVDD
V
20
40
kΩ
µPD780031AY, 780032AY, 780033AY, 780034AY
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Data retention power
supply voltage
VDDDR
Data retention
IDDDR
Oscillation stabilization
Note Selection of
0.1
214/fX
MAX.
Unit
5.5
V
30
µA
µs
0
tWAIT
and
TYP.
1.6
tSREL
time
212/fX
MIN.
VDDDR = 1.6 V
Subsystem clock stop (XT1 = VDD) and
feed-back resistor disconnected
power supply
current
Release signal set time
Test Conditions
Release by RESET
217/fx
ms
Release by interrupt request
Note
ms
to
217/fX
is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
Data Retention Timing (STOP mode release by RESET)
Internal reset operation
HALT mode
Operating mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
RESET
tWAIT
Data Sheet U14045EJ1V0DS00
55
µPD780031AY, 780032AY, 780033AY, 780034AY
Data Retention Timing (Standby release signal: STOP mode release by interrupt request signal)
HALT mode
Operating mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP Instruction execution
Standby release signal
(interrupt request)
tWAIT
Interrupt Request Input Timing
tINTL
tINTH
INTP0 to INTP2
tINTL
INTP3
RESET Input Timing
tRSL
RESET
56
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
13. PACKAGE DRAWINGS
64 PIN PLASTIC SHRINK DIP (750 mil)
64
33
1
32
A
K
J
L
I
F
D
H
C
N
B
M
R
M
G
NOTES
1. Controlling dimension
millimeter.
2. Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
3. Item "K" to center of leads when formed parallel.
ITEM
MILLIMETERS
INCHES
A
58.0+0.68
–0.20
2.283+0.028
–0.008
B
1.78 MAX.
0.070 MAX.
C
1.778 (T.P.)
0.070 (T.P.)
D
0.50±0.10
0.020+0.004
–0.005
F
0.9 MIN.
0.035 MIN.
G
3.2±0.3
0.126±0.012
H
0.51 MIN.
0.020 MIN.
I
4.05+0.26
–0.20
0.159+0.011
–0.008
J
5.08 MAX.
0.200 MAX.
K
19.05 (T.P.)
0.750 (T.P.)
L
17.0±0.2
0.669+0.009
–0.008
M
0.25+0.10
–0.05
0.010+0.004
–0.003
N
0.17
0.007
R
0 to 15°
0 to 15°
P64C-70-750A,C-3
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced
version.
Data Sheet U14045EJ1V0DS00
57
µPD780031AY, 780032AY, 780033AY, 780034AY
64 PIN PLASTIC QFP ( 14)
A
B
48
49
33
32
detail of lead end
S
C D
Q
64
1
R
17
16
F
J
G
H
I
M
P
K
S
N
S
L
M
NOTE
1. Controlling dimension
ITEM
millimeter.
2. Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
MILLIMETERS
INCHES
A
17.6±0.4
B
14.0±0.2
0.693±0.016
0.551 +0.009
–0.008
C
14.0±0.2
0.551 +0.009
–0.008
D
17.6±0.4
0.693±0.016
F
G
1.0
1.0
0.039
0.039
H
0.37 +0.08
–0.07
0.015 +0.003
–0.004
0.006
I
0.15
J
0.8 (T.P.)
0.031 (T.P.)
K
1.8±0.2
0.071±0.008
L
0.8±0.2
0.031 +0.009
–0.008
M
0.17 +0.08
–0.07
0.007 +0.003
–0.004
N
0.10
0.004
P
2.55±0.1
0.100±0.004
Q
0.1±0.1
0.004±0.004
R
S
5°±5°
2.85 MAX.
5°±5°
0.113 MAX.
P64GC-80-AB8-4
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced
version.
58
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
64 PIN PLASTIC LQFP (12x12)
A
B
33
32
48
49
detail of lead end
S
C
D
R
Q
64
17
16
1
F
J
G
H
I
M
ITEM
K
P
S
N
S
L
M
NOTES
1. Controlling dimension
millimeter.
2. Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
INCHES
A
14.8±0.4
0.583±0.016
B
12.0±0.2
0.472+0.009
−0.008
C
12.0±0.2
0.472+0.009
−0.008
D
F
14.8±0.4
1.125
0.583±0.016
0.044
G
1.125
0.044
H
0.32±0.08
0.013+0.003
−0.004
I
0.13
0.005
J
K
0.65 (T.P.)
1.4±0.2
0.026
0.055±0.008
L
0.6±0.2
0.024+0.008
−0.009
M
0.17 +0.08
−0.07
0.007+0.003
−0.004
N
0.10
0.004
P
1.4±0.1
0.055+0.004
−0.005
Q
R
S
0.125±0.075
5°±5°
1.7 MAX.
0.005±0.003
5°±5°
0.067 MAX.
P64GK-65-8A8-2
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced
version.
Data Sheet U14045EJ1V0DS00
59
µPD780031AY, 780032AY, 780033AY, 780034AY
14. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales representative.
Table 14-1. Surface Mounting Type Soldering Conditions
(1) µPD780031AYGC-×××-AB8: 64-pin plastic QFP (14 × 14 mm)
µPD780032AYGC-×××-AB8: 64-pin plastic QFP (14 × 14 mm)
µPD780033AYGC-×××-AB8: 64-pin plastic QFP (14 × 14 mm)
µPD780034AYGC-×××-AB8: 64-pin plastic QFP (14 × 14 mm)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max.
(at 210°C or higher), Count: three times or less
IR35-00-3
VPS
Package peak temperature: 215°C, Time: 40 seconds max.
(at 200°C or higher), Count: three times or less
VP15-00-3
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max.,
Count: once, Preheating temperature: 120°C max. (package surface
temperature)
WS60-00-1
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Caution Do not use different soldering methods together (except for partial heating).
60
Data Sheet U14045EJ1V0DS00
––
µPD780031AY, 780032AY, 780033AY, 780034AY
(2) µPD780031AYGK-×××-8A8: 64-pin plastic LQFP (12 × 12 mm)
µPD780032AYGK-×××-8A8: 64-pin plastic LQFP (12 × 12 mm)
µPD780033AYGK-×××-8A8: 64-pin plastic LQFP (12 × 12 mm)
µPD780034AYGK-×××-8A8: 64-pin plastic LQFP (12 × 12 mm)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max.
(at 210°C or higher),
Count: two times or less, Exposure limit: 7 days Note (after that,
prebake at 125°C for 10 hours)
IR35-107-2
VPS
Package peak temperature: 215°C, Time: 40 seconds max.
(at 200°C or higher),
Count: two times or less, Exposure limit: 7 daysNote (after that,
prebake at 125°C for 10 hours)
VP15-107-2
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max.,
Count: once, Preheating temperature: 120°C max. (package
surface temperature), Exposure limit: 7 daysNote (after that, prebake
WS60-107-1
at 125°C for 10 hours)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
––
Note After opening the dry pack, store it at 25°C or less and 65%RH or less for the allowable storage
period.
Caution Do not use different soldering methods together (except for partial heating).
Table 14-2. Insertion Type Soldering Conditions
µPD780031AYCW-×××: 64-pin plastic shrink DIP (750mils)
µPD780032AYCW-×××: 64-pin plastic shrink DIP (750mils)
µPD780033AYCW-×××: 64-pin plastic shrink DIP (750mils)
µPD780034AYCW-×××: 64-pin plastic shrink DIP (750mils)
Soldering Method
Soldering Conditions
Wave soldering
(only for pins)
Solder bath temperature: 260°C max., Time: 10 seconds max.
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Caution Apply wave soldering only to the pins and be careful not to bring solder into direct contact with
the package.
Data Sheet U14045EJ1V0DS00
61
µPD780031AY, 780032AY, 780033AY, 780034AY
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD780034AY Subseries.
Also refer to (5) Cautions on Using Development Tools.
(1) Language Processing Software
RA78K/0
Assembler package common to 78K/0 Series
CC78K/0
C compiler package common to 78K/0 Series
DF780034
Device file common to µPD780034A Subseries
CC78K/0-L
C compiler library source file common to 78K/0 Series
(2) Flash Memory Writing Tools
Flashpro II (FL-PR2)
Flashpro III (FL-PR3, PG-FP3)
Flash programmer dedicated to microcontrollers with on-chip flash memory
FA-64CW
FA-64GC
FA-64GK
Adapter for flash memory writing
(3) Debugging Tools
• When using in-circuit emulator IE-78K0-NS
IE-78K0-NS
In-circuit emulator common to 78K/0 Series
IE-70000-MC-PS-B
Power supply unit for IE-78K0-NS
IE-78K0-NS-PANote
Performance board to enhance and expand the functions of IE-78K0-NS
IE-70000-98-IF-C
Interface adapter when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported)
IE-70000-CD-IF-A
PC card and interface cable when using notebook PC as host machine (PCMCIA socket supported)
IE-70000-PC-IF-C
Interface adapter when using IBM PC/ATTM or compatible as host machine (ISA bus supported)
IE-70000-PCI-IF
Adapter required when using PC in which PCI bus is embedded as host machine
IE-780034-NS-EM1
Emulation board to emulate µPD780034AY Subseries
NP-64CW
Emulation probe for 64-pin plastic shrink DIP (CW type)
NP-64GC
NP-64GC-TQ
Emulation probe for 64-pin plastic QFP (GC-AB8 type)
NP-64GK
Emulation probe for 64-pin plastic LQFP (GK-8A8 type)
TGK-064SBW
Conversion adapter to connect NP-64GK and target system board on which a 64-pin plastic LQFP
(GK-8A8 type) can be mounted.
EV-9200GC-64
Socket to be mounted on target system board made for 64-pin plastic QFP (GC-AB8 type)
ID78K0-NS
Integrated debugger for IE-78K0-NS
SM78K0
System simulator common to 78K/0 Series
DF780034
Device file common to µPD780034A Subseries
Note
62
Under development
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
• When using in-circuit emulator IE-78001-R-A
IE-78001-R-A
In-circuit emulator common to 78K/0 Series
IE-70000-98-IF-C
Interface adapter when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported)
IE-70000-PC-IF-C
Interface adapter when using IBM PC/AT or compatible as host machine (ISA bus supported)
IE-70000-PCI-IF
Adapter required when using PC in which PCI bus is embedded as host machine
IE-78000-R-SV3
Interface adapter and cable when using EWS as host machine
IE-780034-NS-EM1
Emulation board to emulate µPD780034AY Subseries
IE-78K0-R-EX1
Emulation probe conversion board necessary when using IE-780034-NS-EM1 on IE-78001-R-A
EP-78240CW-R
Emulation probe for 64-pin plastic shrink DIP (CW type)
EP-78240GC-R
Emulation probe for 64-pin plastic QFP (GC-AB8 type)
EP-78012GK-R
Emulation probe for 64-pin plastic LQFP (GK-8A8 type)
TGK-064SBW
Conversion adapter to connect EP-78012GK-R and target system board on which a 64-pin plastic
LQFP (GK-8A8 type) can be mounted.
EV-9200GC-64
Socket to be mounted on target system board made for 64-pin plastic QFP (GC-AB8 type)
ID78K0
Integrated debugger for IE-78001-R-A
SM78K0
System simulator common to 78K/0 Series
DF780034
Device file common to µPD780034A Subseries
(4) Real-time OS
RX78K/0
Real-time OS for 78K/0 Series
MX78K0
OS for 78K/0 Series
Data Sheet U14045EJ1V0DS00
63
µPD780031AY, 780032AY, 780033AY, 780034AY
(5) Cautions on Using Development Tools
• The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780034.
• The CC78K/0 and RX78K/0 are used in combination with the RA78K/0 and the DF780034.
• FL-PR2, FL-PR3, FA-64CW, FA-64GC, FA-64GK, NP-64CW, NP-64GC, NP-64GC-TQ, and NP-64GK are
products made by Naito Densei Machida Mfg. Co., Ltd. (+81-44-822-3813).
Contact an NEC distributor regarding the purchase of these products.
• The TGK-064SBW is a product made by TOKYO ELETECH CORPORATION.
Refer to: Daimaru Kogyo, Ltd.
Tokyo Electronic Division (+81-3-3820-7112)
Osaka Electronic Division (+81-6-6244-6672)
• For third-party development tools, see the 78K/0 Series Selection Guide (U11126E).
• The host machines and OSs supporting each software are as follows.
Host Machine
PC
EWS
Software
PC-9800 series [WindowsTM]
IBM PC/AT and compatibles
[Japanese/English Windows]
HP9000 series 700TM [HP-UXTM]
SPARCstationTM [SunOSTM, SolarisTM]
NEWSTM (RISC) [NEWS-OSTM]
RA78K/0
√ Note
√
CC78K/0
√
Note
√
ID78K0-NS
√
–
ID78K0
√
√
SM78K0
√
–
RX78K/0
√ Note
√
MX78K0
√
√
[OS]
Note
64
Note
DOS-based software
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
APPENDIX B. RELATED DOCUMENTS
Documents Related to Devices
Document Name
Document No.
(English)
µPD780024A, 780034A, 780024AY, 780034AY Subseries User’s Manual
µPD780031AY, 780032AY, 780033AY, 780034AY Data Sheet
U14046E
Document No.
(Japanese)
U14046J
This document
U14045J
µPD78F0034AY Data Sheet
U14041E
U14041J
78K/0 Series User’s Manual Instructions
U12326E
U12326J
78K/0 Series Instruction Table
—
U10903J
78K/0 Series Instruction Set
—
U10904J
Document No.
(English)
Document No.
(Japanese)
Operation
U11802E
U11802J
Assembly Language
U11801E
U11801J
Structured Assembly Language
U11789E
U11789J
RA78K Series Structured Assembler Preprocessor
EEU-1402
U12323J
CC78K0 C Compiler
Operation
U11517E
U11517J
Language
U11518E
U11518J
Programming Know-how
U13034E
U13034J
IE-78K0-NS
To be prepared
To be prepared
IE-78001-R-A
To be prepared
To be prepared
IE-780034-NS-EM1
To be prepared
To be prepared
EP-78240
U10332E
EEU-986
EP-78012GK-R
EEU-1538
EEU-5012
Documents Related to Development Tools (User’s Manuals)
Document Name
RA78K0 Assembler Package
CC78K0 C Compiler Application Note
SM78K0 System Simulator Windows based
Reference
U10181E
U10181J
SM78K Series System Simulator
External Part User Open
Interface Specifications
U10092E
U10092J
U12900E
U12900J
ID78K0-NS Integrated Debugger Windows based Reference
ID78K0 Integrated Debugger EWS based
Reference
—
U11151J
ID78K0 Integrated Debugger PC based
Reference
U11539E
U11539J
ID78K0 Integrated Debugger Windows based
Guide
U11649E
U11649J
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
Data Sheet U14045EJ1V0DS00
65
µPD780031AY, 780032AY, 780033AY, 780034AY
Documents Related to Embedded Software (User’s Manuals)
Document Name
78K/0 Series Real-time OS
78K/0 Series OS MX78K0
Document No.
(English)
Document No.
(Japanese)
Basics
U11537E
U11537J
Installation
U11536E
U11536J
Basics
U12257E
U12257J
Document No.
(English)
Document No.
(Japanese)
Other Related Documents
Document Name
SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM)
X13769X
Semiconductor Device Mounting Technology Manual
C10535E
C10535J
Quality Grades on NEC Semiconductor Devices
C11531E
C11531J
NEC Semiconductor Device Reliability/Quality Control System
C10983E
C10983J
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
C11892J
—
U11416J
Guide to Microcomputer-Related Products by Third Party
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
66
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
[MEMO]
Data Sheet U14045EJ1V0DS00
67
µPD780031AY, 780032AY, 780033AY, 780034AY
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Caution Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use
these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
68
Data Sheet U14045EJ1V0DS00
µPD780031AY, 780032AY, 780033AY, 780034AY
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics (France) S.A.
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Taiwan Ltd.
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Data Sheet U14045EJ1V0DS00
69
µPD780031AY, 780032AY, 780033AY, 780034AY
FIP and IEBus are trademarks of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/
or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8