DATA SHEET MOS INTEGRATED CIRCUIT µPD78P064B 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD78P064B is a product of µPD78064B subseries in 78K/0 series, in which the on-chip mask ROM of the µPD78064B is replaced by one-time PROM. As program write by user is possible, the µPD78P064B is best suited for evaluation, short-run and multiple-device production, and early rise upon system development. Functions are described in detail in the following User’s Manuals, which should be read when carrying out design work. µPD78064B Subseries User’s Manual: U10785E 78K/0 Series User’s Manual Instruction: U12326E FEATURES • Pin compatible with mask ROM products (except the VPP pin) • Internal PROM: 32K bytes One-time programming possible (most suitable for small-scale production) • Internal high-speed RAM: 1024 bytes • LCD display RAM: 40 × 4 bits • Operable in the same supply voltage as mask ROM products (VDD = 2.0 to 6.0 V) • Corresponding to QTOPTM microcomputers Remarks 1. For the differences between PROM products and mask ROM products, refer to 1. DIFFERENCES BETWEEN µ PD78P064B AND MASK ROM PRODUCTS. 2. QTOP Microcomputer is the general name for a total support as far as writing service, marking, screening, and verification after programming one-time PROM internal signal-chip microcontroller offered by NEC. ORDERING INFORMATION Part Number Package On-Chip ROM µPD78P064BGC-7EA 100-pin plastic QFP (fine pitch) (14 × 14 mm) One-time PROM µPD78P064BGC-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm) One-time PROM µPD78P064BGF-3BA 100-pin plastic QFP (14 × 20 mm) One-time PROM Caution The µPD78P064BGC has two types of package. (Refer to 7. PACKAGE DRAWINGS). For the package suppliable to your device, consult NEC sales personnels. The information in this document is subject to change without notice. Document No. U11598EJ2V0DS00 (2nd edition) Date Published May 1997 N Printed in Japan The mark shows major revised points. © 1996 µPD78P064B 78K/0 SERIES DEVELOPMENT The following shows the products organized according to usage. The names in the parallelograms afe subseries names. Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin µ PD78075B µ PD78078 µ PD78070A µPD78075BY µPD78078Y µ PD78070AY µ PD780018Note µ PD780018Y µ PD780058 µ PD780058YNote µ PD78058F µ PD78058FY EMI-noise reduced version of µ PD78078 A timer was added to the µ PD78054 and external interface was enhanced ROM-less version of the µPD78078 Serial I/O of the µ PD78078 was enhanced and the function is limited. Serial I/O of the µ PD78054 was enhanced and EMI-noise was reduced. EMI-noise reduced version of the µ PD78054 80-pin µPD78054 64-pin µPD780034 64-pin 64-pin µ PD780024 µ PD78014H 64-pin µ PD78014Y 64-pin µPD78018F µPD78014 µ PD780001 An A/D converter and 16-bit timer were added to the µPD78002 An A/D converter was added to the µPD78002 64-pin µPD78002 µ PD78002Y Basic subseries for control 42/44-pin µ PD78083 64-pin µ PD78054Y µPD780034Y µ PD780024Y µPD78018FY UART and D/A converter were enhanced to the µ PD78014 and I/O was enhanced A/D converter of the µ PD780024 was enhanced Serial I/O of the µ PD78018F was added and EMI-noise was reduced. EMI-noise reduced version of µPD78018F Low-voltage (1.8 V) operation version of the µPD78014, with larger selection of ROM and RAM capacities On-chip UART, capable of operating at low voltage (1.8 V) Inverter control 64-pin 64-pin A/D converter of the µ PD780924 was enhanced On-chip inverter control circuit and UART. EMI-noise was reduced. µPD780964 µPD780924 FIPTM drive µ PD780208 µ PD780228 The I/O and FIP C/D of the µ PD78044F were enhanced, Display output total: 53 100-pin 80-pin µ PD78044H An N-ch open drain I/O was added to theµ PD78044F, Display output total: 34 80-pin µPD78044F Basic subseries for driving FIP, Display output total: 34 100-pin 78K/0 Series The I/O and FIP C/D of the µ PD78044H were enhanced, Display output total: 48 LCD drive 100-pin µ PD780308 µPD780308Y 100-pin µPD78064B µ PD78064 The SIO of the µPD78064 was enhanced, and ROM, RAM capacity increased EMI-noise reduced version of the µ PD78064 µ PD78064Y Basic subseries for driving LCDs, On-chip UART 100-pin IEBusTM supported 80-pin µ PD78098B EMI-noise reduced version of the µPD78098 80-pin µ PD78098 An IEBus controller was added to the µPD78054 Meter control 80-pin µ PD780973 General purpose version of automobile meter driving controller of the µ PD780805 100-pin µ PD780805 On-chip automobile meter driving controller/driver LV 64-pin Note 2 Under planning µ PD78P0914 On-chip PWM output, LV digital code decoder, and Hsync counter µPD78P064B The following lists the main functional differences between subseries products. Function Subseries Name Control ROM Capacity µPD78075B 32K-40K µPD78078 48K-60K µPD78070A Timer 8-bit 10-bit 8-bit 8-bit 16-bit Watch WDT A/D A/D D/A 4ch 1ch 1ch 1ch 8ch – 2ch 3ch (UART: 1ch) – µPD780018 48K-60K µPD780058 24K-60K µPD78058F 48K-60K µPD78054 16K-60K µPD780034 8K-32K – 2ch 8K-60K µPD78014 8K-32K µPD780001 8K µPD78002 8K-16K – µPD780964 FIP drive µPD780208 32K-60K 2ch 1ch µPD780228 48K-60K 3ch µPD78044H 32K-48K 2ch 1ch µPD78044F 16K-40K 32K µPD78064 16K-32K IEBus µPD78098B supported µPD78098 40K-60K Meter control µPD780973 µPD780805 LV µPD78P0914 32K 61 2.7 V 2ch 3ch (time division UART: 1ch) 68 1.8 V 69 2.7 V – 8ch 8ch – – 3ch Note – 3ch (UART: 1ch, time division 3-wire: 1ch) 51 1.8 V 2ch 53 1.8 V – 1ch 1ch – – 8ch – 1ch 39 – 53 – 8ch 8ch – 1ch 1ch 8ch – µPD780924 µPD78064 1.8 V 2.7 V Inverter control µPD780308B 48K-60K 88 External Expansion 2.0 V µPD78083 8K-32K VDD MIN. Value 88 µPD78014H µPD78018F I/O 2ch (time division 3-wire: 1ch) 3ch (UART: 1ch) µPD780024 LCD drive Serial Interface 1ch (UART: 1ch) 33 1.8 V – 2ch (UART: 2ch) 47 2.7 V – 2ch 74 2.7 V 1ch 72 4.5 V 68 2.7 V 57 2.0 V 69 2.7 V 56 4.5 V 39 2.7 V 54 4.5 V – 1ch – – 2ch 2ch 1ch 1ch 1ch 8ch – – 3ch (time division UART: 1ch) – 2ch (UART: 1ch) 2ch 1ch 1ch 1ch 8ch – 24K-32K 3ch 1ch 1ch 1ch 5ch – 40K-60K 2ch 2ch 3ch (UART: 1ch) 32K-60K 6ch – 2ch (UART: 1ch) 8ch – – 1ch 8ch – – 2ch – Note 10-bit timer: 1 channel 3 µPD78P064B FUNCTION DESCRIPTION Item Internal memory • PROM • RAM High-speed RAM LCD display RAM : 32 K bytes : 1024 bytesNote : 40 × 4 bits General-purpose register 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Instruction cycles When main system clock is selected 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (when operating at 5.0 MHz) When subsystem clock is selected 122 µs (when operating at 32.768 kHz) Instruction set • • • • I/O ports Include segment signal output dual-function pin Total • CMOS input • CMOS input/output A/D converter • 8-bit resolution × 8 ch LCD controller/driver • Segment signal output • Common signal output • Bias Serial interface • 3-wire serial I/O/SBI/2-wire serial I/O mode selectable • 3-wire serial I/O/UART mode selectable Timer • • • • Timer output 3 pins (14-bit PWM output enable 1 pin) Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (when operating at main system clock 5.0 MHz), 32.768 kHz (when operating at subsystem clock 32.768 kHz) Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (when operating at main system clock 5.0 MHz) Vectored interrupt sources 4 Function 16-bit operation Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits) Bit manipulation (set, reset, test, boolean operation) BCD correction, etc. : 57 : 2 : 55 : : : 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer Maskable Internal : 12, External : 6 Non-maskable Internal : 1 Software 1 40 max. 4 max. 1/2, 1/3, Bias switchable : : : : 1 2 1 1 : 1 ch : 1 ch ch ch ch ch Test input Internal : 1, External : 1 Supply voltage VDD = 2.0 to 6.0 V Package • 100-pin plastic (fine pitch) QFP (14 × 14 mm) • 100-pin plastic LQFP (fine pitch) (14 × 14 mm) • 100-pin plastic QFP (14 × 20 mm) µPD78P064B PIN CONFIGURATION (Top View) (1) Normal operating mode • 100-pin plastic QFP (fine pitch) (14 × 14 mm) µPD78P064BGC-7EA • 100-pin plastic LQFP (fine pitch) (14 × 14 mm) P11/ANI1 X2 VPP P72/SCK2/ASCK P71/SO2/TXD XT2 XT1/P07 VDD X1 P112 P111 P110 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1/TI01 P00/INTP0/TI00 RESET P10/ANI0 AVSS P117 P116 P115 P114 P113 µPD78P064BGC-8EU 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AVDD AVREF P100 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 P101 VSS P102 P103 P30/TO0 P31/TO1 P32/TO2 P33/TI1 11 65 12 64 13 63 14 62 15 61 16 60 17 59 18 58 P34/TI2 P35/PCL P36/BUZ P37 COM0 COM1 COM2 19 57 20 56 21 55 22 54 23 53 52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Cautions 1. 2. P86/S33 P87/S32 P90/S31 P91/S30 P92/S29 P93/S28 P94/S27 P95/S26 P96/S25 P97/S24 S23 S22 S21 S20 S19 S15 S16 S17 S18 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 COM3 BIAS VLC0 VLC1 VLC2 VSS S0 24 P70/SI2/RXD P27/SCK0 P26/SO0/SB1 P25/SI0/SB0 P80/S39 P81/S38 P82/S37 P83/S36 P84/S35 P85/S34 Connect VPP pin directly to VSS. AVDD pin shares the port power supply with that of the A/D converter. When using in applications where noise from inside the microcomputer has to be reduced, connect the AVDD pin to a separate power supply, whose electrical potential is the same as that of VDD. 3. AVSS pin shares the port GND with that of the A/D converter. When using in applications where noise from inside the microcomputer has to be reduced, connect the AVSS pin to a separate ground line. 5 µPD78P064B • 100-pin plastic QFP (14 × 20 mm) P86/P33 P87/P32 P90/S31 P91/S30 P92/S29 P93/S28 P94/S27 P95/S26 P96/S25 P97/S24 S23 S22 S21 P25/SI0/SB0 P80/S39 P81/S38 P82/S37 P83/S36 P84/S35 P85/P34 µPD78P068BGF-3BA 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 XT2 RESET P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 11 70 12 69 13 68 14 67 15 66 P03/INTP3 P04/INTP4 P05/INTP5 16 65 17 64 18 63 P110 P111 P112 P113 P114 P115 P116 19 62 20 61 21 60 22 59 23 58 24 57 25 56 P117 AVSS P10/ANI0 P11/ANI1 P12/ANI2 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Cautions 1. 2. S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 VSS VLC2 VLC1 VLC0 BIAS COM3 COM2 COM1 COM0 P100 P101 VSS P102 P103 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 1 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AVDD AVREF P26/SO0/SB1 P27/SCK0 P70/SI2/RXD P71/SO2/TXD P72/SCK2/ASCK VPP X2 X1 VDD XT1/P07 Connect VPP pin directly to VSS. AVDD pin shares the port power supply with that of the A/D converter. When using in applications where noise from inside the microcomputer has to be reduced, connect the AVDD pin to a separate power supply, whose electrical potential is the same as that of VDD. 3. AVSS pin shares the port GND with that of the A/D converter. When using in applications where noise from inside the microcomputer has to be reduced, connect the AVSS pin to a separate ground line. 6 µPD78P064B ANI0-ANI7 : Analog Input PCL : Programmable Clock ASCK : Asynchronous Serial Clock RESET : Reset AVDD : Analog Power Supply RxD : Receive Data AVREF : Analog Reference Voltage S0-S39 : Segment Output AVSS : Analog Ground SB0, SB1 : Serial Bus BIAS : LCD Power Supply Bias Control SI0, SI2 : Serial Input BUZ : Buzzer Clock SO0, SO2 : Serial Output COM0-COM3 : Common Output SCK0, SCK2 : Serial Clock INTP0-INTP5 : Interrupt from Peripherals TI00, TI01 : Timer Input P00-P05, P07 : Port 0 TI1,TI2 : Timer Input P10-P17 : Port 1 TO0-TO2 : Timer Output P25-P27 : Port 2 TxD : Transmit Data P30-P37 : Port 3 VDD : Power Supply P70-P72 : Port 7 VLC0-VLC2 : LCD Power Supply P80-P87 : Port 8 VSS : Ground P90-P97 : Port 9 VPP : Programming Power Supply P100-P103 : Port 10 X1, X2 : Crystal (Main System Clock) P110-P117 : Port 11 XT1, XT2 : Crystal (Subsystem Clock) 7 µPD78P064B (2) PROM programming mode • 100-pin plastic QFP (fine pitch) (14 × 14 mm) µPD78P064BGC-7EA • 100-pin plastic LQFP (fine pitch) (14 × 14 mm) (L) Open VPP PGM (L) A9 RESET Open (L) VDD (L) (L) CE OE (L) µPD78P064BGC-8EU 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 12 64 13 63 14 62 D0 D1 D2 D3 15 61 16 60 17 59 18 58 D4 D5 D6 D7 19 57 20 56 21 55 22 54 23 53 (L) VDD VSS (L) VSS (L) (L) 52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (L) 24 Cautions 1. 8 (L) : Individually connect to VSS via a pull-down resistor. 2. VSS : Connect to GND. 3. RESET : Set to low level. 4. Open : No connection (L) A0 A1 A2 A3 A4 A5 A6 A7 A8 A16 A10 A11 A12 A13 A14 A15 (L) µPD78P064B • 100-pin plastic QFP (14 × 20 mm) (L) 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (L) (L) 78 4 (L) D0 D1 D2 D3 D4 D5 D6 D7 OE CE 79 3 (L) (L) 2 VSS Open RESET A9 (L) PGM 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 (L) VPP Open (L) VDD (L) 1 VDD VSS (L) A6 A7 A8 A16 A10 A11 A12 A13 A14 A15 (L) A0 A1 A2 A3 A4 A5 µPD78P064BGF-3BA Cautions 1. (L) : Individually connect to VSS via a pull-down resistor. 2. VSS : Connect to GND. 3. RESET : Set to low level. 4. Open : No connection A0 to A16 : Address Bus RESET : Reset CE : Chip Enable VDD : Power Supply D0 to D7 : Data Bus VPP : Programming Power Supply OE : Output Enable VSS : Ground PGM : Program 9 µPD78P064B BLOCK DIAGRAM TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 P00 16-bit TIMER/ EVENT COUNTER PORT0 P01-P05 P07 TO1/P31 TI1/P33 TO2/P32 TI2/P34 8-bit TIMER/EVENT COUNTER 1 8-bit TIMER/EVENT COUNTER 2 PORT1 P10-P17 PORT2 P25-P27 PORT3 P30-P37 PORT7 P70-P72 PORT8 P80-P87 PORT9 P90-P97 PORT10 P100-P103 PORT11 P110-P117 WATCHDOG TIMER WATCH TIMER SI0/SB0/P25 SO0/SB1/P26 SERIAL INTERFACE 0 78K/0 CPU CORE PROM SCK0/P27 SI2/RxD/P70 SO2/TxD/P71 SERIAL INTERFACE 2 SCK2/ASCK/P72 S0-S23 ANI0/P10ANI7/P17 AVREF INTP0/P00INTP5/P05 INTERRUPT CONTROL BUZ/P36 BUZZER OUTPUT PCL/P35 10 A/D CONVERTER CLOCK OUTPUT CONTROL RAM LCD CONTROLLER/ DRIVER S24/P97S31/P90 S32/P97S39/P80 COM0-COM3 VLC0-VLC2 BIAS fLCD VDD VSS AVDD AVSS VPP SYSTEM CONTROL RESET X1 X2 XT1/P07 XT2 µPD78P064B CONTENTS 1. DIFFERENCES BETWEEN µPD78P064B AND MASK ROM PRODUCTS ........................................... 12 2. PIN FUNCTION TABLE ............................................................................................................................. 13 2.1 PINS IN NORMAL OPERATING MODE ........................................................................................................... 13 2.2 PINS IN PROM PROGRAMMING MODE ......................................................................................................... 16 2.3 PIN INPUT/OUTPUT CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS ...................... 17 3. MEMORY SIZE SWITCHING REGISTER (IMS) ....................................................................................... 20 4. PROM PROGRAMMING ............................................................................................................................ 21 4.1 OPERATING MODES ......................................................................................................................................... 21 4.2 PROM WRITE PROCEDURE ............................................................................................................................ 23 4.3 PROM READ PROCEDURE .............................................................................................................................. 27 5. ONE-TIME PROM PRODUCTS SCREENING .......................................................................................... 28 6. ELECTRICAL SPECIFICATIONS ............................................................................................................ 29 7. PACKAGE DRAWINGS ............................................................................................................................. 52 8. RECOMMENDED SOLDERING CONDITIONS ...................................................................................... 55 APPENDIX A. DEVELOPMENT TOOLS........................................................................................................ 56 APPENDIX B. RELATED DOCUMENTS ....................................................................................................... 61 11 µPD78P064B 1. DIFFERENCES BETWEEN µPD78P064B AND MASK ROM PRODUCTS The µPD78P064B is a single-chip microcontroller with an on-chip one-time writable PROM. It is possible to make all the functions exception PROM specification, and mask option of LCD drive power supply dividing resistor, to the same as those of mask ROM products by setting the memory size switching register (IMS). Difference between the PROM product (µPD78P064B) and mask ROM product (µPD78064B) are shown is Table 1-1. Table 1-1. Differences between µPD78P064B and Mask ROM Products µPD78P064B Mask ROM Products One-time PROM Mask ROM IC pin No Yes VPP pin Yes No Mask option of LCD drive power supply dividing resistor No Yes Item Internal ROM structure Electrical characteristics Caution Refer to Data Sheet for each product Noise resistance and noise radiation are different in PROM version and mask ROM versions. If using a mask ROM version instead of the PROM version for processes between prototype development and full production, be sure to fully evaluate the CS of the mask ROM version (not ES). Remark The internal PROM becomes to 32K bytes and the internal high-speed RAM becomes 1024 bytes by the RESET input. 12 µPD78P064B 2. PIN FUNCTION TABLE 2.1 PINS IN NORMAL OPERATING MODE (1) PORT PINS (1/2) Pin Name Input/Output P00 Input P01 Input/output P02 P03 Function Port 0 7-bit input/output port After Reset Dual-Function Pin Input only Input INTP0/TI00 Input/output is specifiable bit-wise. When used as the input port, an on-chip pull-up resistor can be used by software. Input INTP1/TI01 INTP2 INTP3 P04 INTP4 P05 INTP5 P07Note 1 Input P10 to P17 Input/output P25 Input/output P26 P27 P30 Input/output P31 P32 Input XT1 Port 1 8-bit input/output port Input/output is specifiable bit-wise. When used as the input port, an on-chip pull-up resistor can be used by software.Note 2 Input ANI0 to ANI7 Port 2 3-bit input/output port Input/output is specifiable bit-wise. When used as the input port, an on-chip pull-up resistor can be used by software. Input SI0/SB0 Port 3 8-bit input/output port Input/output is specifiable bit-wise. When used as the input port, an on-chip pull-up resistor can be used by software. Input Input only SO0/SB1 SCK0 TO0 TO1 TO2 P33 TI1 P34 TI2 P35 PCL P36 BUZ P37 —— P70 P71 P72 Input/output Port 7 3-bit input/output port Input/output is specifiable bit-wise. When used as the input port, an on-chip pull-up resistor can be used by software. Input SI2/RXD SO2/TXD SCK2/ASCK Notes 1. When P07/XT1 pins are used as the input ports, set processor clock control register (PCC) bit 6 (FRC) to 1. (Do not use the on-chip feedback resistor of the subsystem clock oscillation circuit.) 2. When P10/ANI0 to P17/ANI7 pins are used as the analog inputs for A/D converter, set port 1 to input mode. The on-chip pull-up resistor is automatically disabled. 13 µPD78P064B (1) PORT PINS (2/2) After Reset Dual-Function Pin Port 8 8-bit input/output port Input/output is specifiable bit-wise. When used as the input port, an on-chip pull-up resistor can be used by software. Input/output port/segment signal output function specifiable in 2-bit units by LCD display control register (LCDC). Input S39 to S32 Input/output Port 9 8-bit input/output port. Input/output is specifiable bit-wise. When used as the input port, an on-chip pull-up resistor can be used by software. Input/output port/segment signal output function specifiable in 2-bit units by LCD display control register. (LCDC). Input S31 to S24 P100 to P103 Input/output Port 10 4-bit input/output port Input/output is specifiable in bit-wise. When used as the input port, an on-chip pull-up resistor can be used by software. It is possible to directly drive LED. Input P110 to P117 Input/output Port 11 8-bit input/output port Input/output is specifiable in bit-wise. When used as the input port, an on-chip pull-up resistor can be used by software. Falling edge detection possible. Input Pin Name Input/Output P80 to P87 Input/output P90 to P97 Caution Function Do not perform the following operation on the pins shared with port pins during A/D conversion operation; otherwise, the specifications of the total error during A/D conversion cannot be satisfied (except the pins shared with LCD segment output pins). (1) Rewriting the output latch of an output pin used as a port pin (2) Changing the output level of an output pin even when it is not used as a port pin 14 µPD78P064B (2) PINS OTHER THAN PORT PINS (1/2) Pin Name Input/Output INTP0 Input INTP1 Function External interrupt request input with specifiable Valid edges (rising edge, falling edge, and both rising and falling edges). After Reset Dual-Function Pin Input P00/TI00 P01/TI01 INTP2 P02 INTP3 P03 INTP4 P04 INTP5 P05 SI0 Input Serial data input of the serial interface Input SI2 SO0 P70/RXD Output Serial data output of the serial interface Input SO2 SB0 P26/SBI P71/TXD Input/output Serial data input/output of the serial interface Input SB1 SCK0 P25/SB0 P25/SI0 P26/SO0 Input/output Serial clock input/output of the serial interface Input P27 P72/ASCK SCK2 RX D Input Serial data input for asynchronouse serial interface Input P70/SI2 T XD Outpu Serial data output for asynchronous serial interface Input P71/SO2 ASCK Input Serial clock input for asynchronous serial interface Input P72/SCK2 TI00 Input External count clock input to the 16-bit timer (TM0). Input P00/INTP0 TI01 Capture trigger signal input to the capture register (CR00). TI1 External count clock input to the 8-bit timer (TM1). P33 TI2 External count clock input to the 8-bit timer (TM2). P34 TO0 Output 16-bit timer (TM0) output (dual-function as 14-bit PWM output) P01/INTP1 Input P30 TO1 8-bit timer (TM1) output P31 TO2 8-bit timer (TM2) output P32 PCL Output Clock output (for trimming main system clock and subsystem clock) Input BUZ Output Buzzer output Input Output LCD controller/driver segment signal output S0 to S23 S32 to S39 COM0 to COM3 VLC0 to VLC2 BIAS P36 Output Input S24 to S31 P35 P97-P90 P87-P80 Output LCD controller/driver common signal output Output LCD drive voltage LCD drive power supply 15 µPD78P064B (2) PINS OTHER THAN PORT PINS (2/2) Pin Name Input/Output Function ANI0 to ANI7 Input Analog input of A/D converter AVREF Input Reference voltage input of A/D converter AVDD Analog power supply of A/D converter (shared by power supply of port) AVSS Ground potential of A/D converter (shared by ground potential of port) RESET Input System reset input X1 Input Main system clock oscillation crystal connection Input Subsystem clock oscillation crystal connection After Reset Dual-Function Pin Input P10 to P17 Input P07 X2 XT1 XT2 VDD Positive power supply (except port) VPP High-voltage applied during program write/verification Connected directly to VSS in normal operating mode VSS Ground potential (except port) Cautions 1. AVDD pin shares the port power supply with that of the A/D converter. When using in applications where noise from inside the microcomputer has to be reduced, connect the AVDD pin to a separate power supply, whose electrical potential is the same as that of VDD. 2. AVSS pin shares the port GND with that of the A/D converter. When using in applications where noise from inside the microcomputer has to be reduced, connect the AVSS pin to a separate ground line. 2.2 16 PINS IN PROM PROGRAMMING MODE Pin Name Input/Output Function RESET Input PROM programming mode setting When +5 V or +12.5 V is applied to the VPP pin and a low level signal is applied to the RESET pin, this chip is set in the PROM programming mode. VPP Input PROM programming mode setting and high-voltage applied during program write/ verification A0 to A16 Input Address bus D0 to D7 Input/output CE Input PROM enable input/program pulse input OE Input Read strobe input to PROM PGM Input Program/program inhibit input in PROM programing mode. Data bus VDD Positive power supply VSS Ground potential µPD78P064B 2.3 PIN INPUT/OUTPUT CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS Types of input/output circuits of the pins and recommended connection of unused pins are shown in Table 2-1. For the configuration of each type of input/output circuit, refer to Figure 2-1. Table 2-1. Type of Input/Output Circuit of Each Pin Input/Output Circuit Type I/O P00/INTP0/TI00 2 Input P01/INTP1/TI01 8-D I/O Pin Name Recommended Connection When not Used Connect to VSS. Individually connect to VSS via a resistor P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P07/XT1 16 Input P10/ANI0 to P17/ANI7 11-C I/O P25/SI0/SB0 10-C Connect to VDD. Individually connect to VDD or VSS via a resistor P26/SO0/SB1 P27/SCK0 P30/TO0 5-J P31/TO1 P32/TO2 P33/TI1 8-D P34/TI2 P35/PCL 5-J P36/BUZ P37 P70/SI2/RxD 8-D P71/SO2/TxD 5-J P72/SCK2/ASCK 8-D P80/S39 to P87/S32 17-E P90/S31 to P97/S24 P100 to P103 5-J P110 to P117 8-D S0 to S23 17-D COM0 to COM3 18-B Individually connect to VDD via resistor Output Leave open VLC0 to VLC2 BIAS RESET 2 XT2 16 Input Leave open AVREF Connect to VSS AVDD Connect to separate power supply whose electrical potential is the same as that of VDD. AVSS Connect to separate ground line whose electrical potential is the same as that of VSS. VPP Connect directly to VSS 17 µPD78P064B Figure 2-1. List of Pin Input/Output Circuits (1/2) Type 10-C Type 2 AVDD pull-up enable P-ch AVDD data IN P-ch IN/OUT open drain output disable N-ch AVSS Schmitt-Triggered Input with Hysteresis Characteristic Type 11-C Type 5-J AVDD AVDD pull-up enable Pull-up enable P-ch AVDD P-ch data P-ch AVDD Data IN/OUT output disable P-ch IN/OUT Output disable N-ch P-ch Comparator AVSS + – N-ch N-ch AVSS VREF (Threshold voltage) AVSS Input enable input enable Type 16 Type 8-D AVDD feedback cut-off pull-up enable P-ch P-ch AVDD data P-ch IN/OUT output disable N-ch XT1 AVSS 18 XT2 µPD78P064B Figure 2-1. List of Pin Input/Output Circuits (2/2) Type 18-B Type 17-D VLC0 VLC0 P-ch P-ch VLC1 VLC1 N-ch N-ch N-ch P-ch P-ch SEG data OUT N-ch COM data N-ch P-ch P-ch OUT P-ch VLC2 VLC2 N-ch N-ch VSS VSS Type 17-E AVDD pull-up enable P-ch AVDD data P-ch IN/OUT output disable N-ch AVSS input enable VLC0 P-ch VLC1 N-ch P-ch SEG data P-ch N-ch VLC2 N-ch VSS 19 µPD78P064B 3. MEMORY SIZE SWITCHING REGISTER (IMS) This is a register to disable use of part of internal memories by software. By setting this memory size switching register (IMS), it is possible to get the same memory mapping as that of mask ROM product having different internal memories (ROM, RAM). The IMS is set up by the 8-bit memory manipulating instruction. C8H will result by the RESET input. Figure 3-1. Memory Size Switching Register Format Symbol IMS 7 6 5 4 3 2 1 0 Address After Reset R/W RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 FFF0H C8H R/W ROM3 ROM2 ROM1 ROM0 1 0 0 0 Other than above Selection of Internal ROM Capacity 32K bytes Setting prohibited Selection of Internal RAM2 RAM1 RAM0 High-Speed RAM Capacity 1 1 0 Other than above 1024 bytes Setting prohibited Table 3-1 shows the set values of IMS which makes the memory map the same as that of the various mask ROM products. Table 3-1. Memory Size Switching Register Setting Values 20 Target Mask ROM Product IMS Setting Value µPD78064B C8H µPD78P064B 4. PROM PROGRAMMING The µPD78P064B has an on-chip 32K-byte PROM as a program memory. For programming, set the PROM programming mode by the VPP and RESET pins. For processing unused pins, refer to Pin Configuration (2) PROM programming mode. Caution 4.1 When writing in a program, use locations 0000H-7FFFH. (Specify the last address as 7FFFH). You cannot write in using a PROM programmer that cannot specify the addresses to write. OPERATING MODES When +5 V or +12.5 V is applied to the VPP pin and a low level signal is applied to the RESET pin, the PROM programming mode is set. This mode will become the operating mode as shown in Table 4-1 when the CE, OE and PGM pins are set as shown. Further, when the read mode is set, it is possible to read the contents of the PROM. Table 4-1. Operating Modes of PROM Programming Pin RESET VPP VDD CE OE PGM D0 to D7 L +12.5 V +6.5 V H L H Data input Page write H H L High-impedance Byte write L H L Data input Program verify L L H Data output Program inhibit × H H High-impedance × L L L L H Data output Output disable L H × High-impedance Standby H × × High-impedance Operating Mode Page data latch Read +5 V +5 V × : L or H 21 µPD78P064B (1) Read mode Read mode is set if CE = L, OE = L is set. (2) Output disable mode Data output becomes high-impedance, and is in the output disable mode, of OE = H is set. Therefore, it allows data to be read from any device by controlling the OE pin, if multiple µPD78P064Bs are connected to the data bus. (3) Standby mode Standby mode is set if CE = H is set. In this mode, data outputs become high-impedance irrespective of the OE status. (4) Page data latch mode Page data latch mode is set if CE = H, PGM = H, OE = L are set at the beginning of page write mode. In this mode, 1 page 4-byte data is latched in an internal address/data latch circuit. (5) Page write mode After 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed by applying a 0.1 ms program pulse (active low) to the PGM pin with CE = H, OE = H. Then, program verification can be performed, if CE = L, OE = L are set. If programming is not performed by a one-time program pulse, X (X ≤ 10) write and verification operations should be executed repeatedly. (6) Byte write mode Byte write is executed when a 0.1 ms program pulse (active low) is applied to the PGM pin with CE = L, OE = H. Then, program verification can be performed if OE = L is set. If programming is not performed by a one-time program pulse, X (X ≤ 10) write and verification operations should be executed repeatedly. (7) Program verify mode Program verify mode is set if CE = L, PGM = H, OE = L are set. In this mode, check if a write operation is performed correctly, after the write. (8) Program inhibit mode Program inhibit mode is used when the OE pin, VPP pin and D0 to D7 pins of multiple µPD78P064Bs are connected in parallel and a write is performed to one of those devices. When a write operation is performed, the page write mode or byte write mode described above is used. At this time, a write is not performed to a device which has the PGM pin driven high. 22 µPD78P064B 4.2 PROM WRITE PROCEDURE Figure 4-1. Page Program Mode Flow Chart Start Address = G VDD = 6.5 V, VPP = 12.5 V X=0 Latch Address = address + 1 Latch Address = address + 1 Latch Address = address + 1 Address = address + 1 Latch No X=X+1 X = 10 ? 0.1 ms program pulse Verify 4 bytes Yes Fail Pass No Address = N ? Yes VDD = 4.5 to 5.5 V, VPP = VDD Pass Verify all bytes Fail All Pass Write end Faulty product G = Start address N = Program last address 23 µPD78P064B Figure 4-2. Page Program Mode Timing Page Data Latch Page Program Program Verify A2 to A16 A0, A1 D0 to D7 Data Input VPP VPP VDD VDD + 1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL 24 Data Output µPD78P064B Figure 4-3. Byte Program Mode Flow Chart Start Address = G VDD = 6.5 V, VPP = 12.5 V X=0 X=X+1 No X = 10 ? 0.1 ms Program pulse Yes Address = address + 1 Fail Verify Pass No Address = N ? Yes VDD = 4.5 to 5.5 V, VPP = VDD Pass Verify all bytes Fail All Pass Write end Faulty product G = Start address N = Program last address 25 µPD78P064B Figure 4-4. Byte Program Mode Timing Program Program Verify A0 to A16 D0 to D7 Data Input Data Output VPP VPP VDD VDD + 1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL Cautions 1. VDD should be applied before VPP and cut after VPP. 2. VPP must not exceed +13.5 V including overshoot. 3. Reliability may be adversely affected of removal/reinsertion is performed while +12.5 V is being applied to VPP. 26 µPD78P064B 4.3 PROM READ PROCEDURE The contents of PROM are readable to the external data bus (D0 to D7) according to the read procedure shown below. (1) Fix the RESET pin at low level, supply +5 V to the VPP pin, and process all other unused pins as shown in Pin Configuration (2) PROM programming mode. (2) Supply +5 V to the VDD and VPP pins. (3) Input address of read data into the A0 to A16 pins. (4) Read mode (5) Output data to D0 to D7 pins. The timings of the above steps (2) to (5) are shown in Figure 4-5. Figure 4-5. PROM Read Timings Address Input A0 to A16 CE (Input) OE (Input) D0 to D7 Hi-Z Data Output Hi-Z 27 µPD78P064B 5. ONE-TIME PROM PRODUCTS SCREENING The one-time PROM product (µPD78P064BGC-7EA, µPD78P064BGC-8EU, µPD78P064BGF- 3BA) can not be tested completely by NEC before it is shipped, because of its structure. It is recommended to perform screening to verify PROM after writing necessary data and performing high-temperature storage under the condition below. Storage Temperature Storage Time 125 °C 24 hours At present, a fee is charged by NEC for one-time PROM after-programming writing, marking, screening, and verify service for the QTOP Microcomputer. For details, contact your sales representative. 28 µPD78P064B 6. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Parameter Supply voltage Rating Unit VDD –0.3 to +7.0 V VPP –0.3 to +13.5 V AVDD –0.3 to VDD +0.3 V AVREF –0.3 to VDD +0.3 V –0.3 to +0.3 V –0.3 to VDD +0.3 V –0.3 to +13.5 V –0.3 to VDD +0.3 V AVSS –0.3 to AVREF +0.3 V –10 mA –15 mA Peak value 30 mA R.m.s. value 15 mA Peak value 100 mA R.m.s. value 70 mA Symbol Test Conditions AVSS VI P00-P05, P07, P10-P17, P25-P27, P30-P37, P70-P72, P80-P87, P90-P97, P100-P103, P110-P117 VI2 A9 (PROM programming mode) Input voltage Output voltage VO Analog input voltage VAN P10-P17 Analog input pin 1 pin Output current, high Total for P01-P05, P10-P17, P25-P27, P30-P37, P70-P72, P80-P87, P90-P97, P100-P103, P110-P117 IOH 1 pin Output current, low IOLNote Total for P01-P05, P10-P17, P25-P27, P30-P37, P70-P72, P80-P87, P90-P97, P100-P103, P110-P117 Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Note The r.m.s. value should be calculated as follows: [R.m.s. value] = [Peak value] × √ Duty Caution The product quality may be damaged even if a value of only one of the above parameters exceeds the absolute maximum rating or any value exceeds the absolute maximum rating for an instant. That is, the absolute maximum rating is a rating value which may cause a product to be damaged physically. The absolute maximum rating values must therefore be observed in using the product. Remark Unless specified otherwise, the characteristics of dual-function pins are the same as the those of port pins. CAPACITANCE (TA= 25 °C, VDD = VSS = 0 V) Parameter Input capacitance Symbol Test Conditions CIN Output capacitance COUT I/O capacitance CIO f = 1 MHz unmeasured pins returned to 0 V. MIN. TYP. MAX. Unit 15 pF 15 pF 15 pF 29 µPD78P064B MAIN SYSTEM CLOCK OSCILLATION CIRCUIT CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.0 to 6.0 V) Resonator Ceramic resonator Recommended circuit X1 VPP X2 C2 Crystal resonator C1 X1 VPP X2 C2 C1 External clock X2 µPD74HCU04 X1 Test conditions Parameter Oscillator frequency (fX)Note 1 V DD = Oscillator voltage range Oscillation stabilization timeNote 2 After VDD reaches oscillator voltage range MIN. Oscillator frequency (fX)Note 1 Oscillation stabilization timeNote 2 MIN. TYP. 1 1 MAX. Unit 5 MHz 4 ms 5 MHz 10 V DD = 4.5 to 6.0 V ms 30 X1 input frequency (fX)Note 1 1.0 5.0 MHz X1 input high/low level width (tXH , tXL) 85 500 ns Notes 1. Indicates only oscillation circuit characteristics. Refer to “AC Characteristics” for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. • Wiring should be as short as possible. • Wiring should not cross other signal lines. • Wiring should not be placed close to a varying high current. • The potential of the oscillator capacitor ground should be the same as VSS. • Do not ground it to the ground pattern in which a high current flows. • Do not fetch a signal from the oscillator. 2. If the main system clock oscillation circuit is operated by the subsystem clock when the main system clock is stopped, reswitching to the main system clock should be performed after the stable oscillation time has been obtained by the program. 30 µPD78P064B SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85°C, VDD = 2.0 to 6.0 V) Resonator Recommended Circuit VPP XT1 XT2 R1 Parameter Test Conditions Oscillator frequency (fXT)Note 1 MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 s Crystal resonator C3 C4 Oscillation stabilization timeNote 2 VDD = 4.5 to 6.0 V 10 XT1 XT2 XT1 input frequency (fXT)Note 1 32 100 kHz XT1 input high-/low-level width (tXTH/tXTL) 5 15 µs External clock Notes 1. Indicates only oscillation circuit characteristics. Refer to “AC Characteristics” for instruction execution time. 2. Time required to stabilize oscillation after VDD has reached the minimum oscillation voltage range. Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. • Wiring should be as short as possible. • Wiring should not cross other signal lines. • Wiring should not be placed close to a varying high current. • The potential of the oscillator capacitor ground should be the same as VSS. • Do not ground it to the ground pattern in which a high current flows. • Do not fetch a signal from the oscillator. 2. The subsystem clock oscillation circuit is designed as a low amplification circuit to provide low consumption current, causing misoperation to noise more frequently than the main system clock oscillation circuit. Special care should therefore be taken to wiring method when the subsystem clock is used. 31 µPD78P064B RECOMMENDED OSCILLATION CIRCUIT CONSTANT MAIN SYSTEM CLOCK: CERAMIC RESONATOR (TA = –40 to +85 °C) Manufaturer Murata Mfg. Co., Ltd. Matsushita Electronics Components Co., Ltd. Kyocera Corporation Caution Product Name Frequency (MHZ) Recommended Circuit Constant Oscillator Voltage Range C1 (pF) C2 (pF) MIN. (V) MAX. (V) Remarks CSA5.00MG 5.00 30 30 2.7 6.0 CST5.00MGW 5.00 Built-in Built-in 2.7 6.0 EF0GC5004A4 5.00 Built-in Built-in 2.7 6.0 Lead type EF0EC5004A4 5.00 Built-in Built-in 2.7 6.0 Round lead type EF0EN5004A4 5.00 33 33 2.7 6.0 Lead type EF0S5004B4 5.00 Built-in Built-in 2.7 6.0 Chip type KBR-5.0MSA 5.00 33 33 2.7 6.0 Lead type PBRC5.00A 5.00 33 33 2.7 6.0 Chip type KBR-5.0MKS 5.00 Built-in Built-in 2.7 6.0 Lead type KBR-5.0MWS 5.00 Built-in Built-in 2.7 6.0 Chip type The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being used. 32 µPD78P064B DC CHARACTERISTICS (TA = –40 to +85°C, VDD = 2.0 to 6.0 V) Parameter Symbol Test Conditions MAX. Unit 0.7 VDD VDD V 0.8 VDD VDD V 0.8 VDD VDD V 0.85 VDD VDD V VDD–0.5 VDD V VDD–0.2 VDD V 4.5 ≤ VDD ≤ 6.0 V 0.8 VDD VDD V 2.7 ≤ VDD < 4.5 V 0.9 VDD VDD V 0.9 VDD VDD V 0 0.3 VDD V 0 0.2 VDD V 0 0.2 VDD V 0 0.15 VDD V 0 0.4 V 0 0.2 V 4.5 ≤ VDD ≤ 6.0 V 0 0.2 VDD V 2.7 ≤ VDD < 4.5 V 0 0.1 VDD V 2.0 ≤ VDD < 2.7 VNote 0 0.1 VDD V VDD = 4.5 to 6.0 V IOH = –1 mA VDD–1.0 VDD V IOH = –100 µA VDD–0.5 VDD V 2.0 V 0.4 V 0.2 VDD V 0.5 V P10-P17, P30-P32, VIH1 VDD = 2.7 to 6.0 V Input voltage, high VDD = 2.7 to 6.0 V P33, P34, P70-P72, P110-P117, RESET VDD = 2.7 to 6.0 V VIH3 VIH4 X1, X2 XT1/P07, XT2 2.0 ≤ VDD < 2.7 P10-P17, P30-P32, VIL1 VNote VDD = 2.7 to 6.0 V P35-P37, P80-P87, P90-P97, P100-P103 P00-P05, P25-P27, VIL2 Input voltage, low VIL4 Output voltage, high X1, X2 XT1/P07, XT2 VOH VOL1 Output voltage, low Note VDD = 2.7 to 6.0 V P33, P34, P70-P72, P110-P117, RESET VDD = 2.7 to 6.0 V VIL3 TYP. P35-P37, P80-P87, P90-P97, P100-P103 P00-P05, P25-P27, VIH2 MIN. P100-P103 VDD = 4.5 to 6.0 V, IOL = 15 mA P01-P05, P25-P27, P70-P72, P90-P97, VDD = 4.5 to 6.0 V, IOL = 1.6 mA P10-P17, P30-P37, P80-P87, P110-P117 VOL2 SB0, SB1, SCK0 VOL3 IOL = 400 µA 0.4 VDD = 4.5 to 6.0 V, open-drain, pulled up (R = 1 kΩ) When used as P07, the inverse phase of P07 should be input to XT2 using an inverter. Remark Unless specified otherwise, the characteristics of dual-function pins are the same as the those of port pins. 33 µPD78P064B DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.0 to 6.0 V) Parameter Symbol Input leakage current, high ILIH1 Test Conditions VIN = VDD ILIH2 Input leakage current, low ILIL1 VIN = 0 V ILIH2 Output leakage current, high Output leakage current, low MAX. Unit P00-P05, P10-P17, P25-P27, P30-P37, P70-P72, P80-P87, P90-P97, P100-P103, P110-P117 3 µA X1, X2, XT1/P07, XT2 20 µA P00-P05, P10-P17, P25-P27, P30-P37, P70-P72, P80-P87, P90-P97, P100-P103, P110-P117 –3 µA X1, X2, XT1/P07, XT2 –20 µA VOUT = VDD 3 µA ILOL VOUT = 0 V –3 µA 90 kΩ 500 kΩ 15.0 2.1 1.2 27.0 3.0 4.2 1500 840 4.8 1950 270 190 140 55 15 12.5 30 10 10 30 10 10 mA mA mA mA mA mA µA µA mA µA µA µA µA µA µA µA µA µA µA µA µA µA R IDD1 IDD2 Supply currentNote 1 TYP. ILOH VIN = 0 V, P01-P05, P10-P17, Software pull-up resistor MIN. IDD3 IDD4 IDD5 IDD6 P25-P27, P30-P37, P70-P72, P80-P87, P90-P97, P100-P103, P110-P117 4.5 V ≤ VDD ≤ 6.0 V 15 2.7 V ≤ VDD < 4.5 V 20 VDD VDD VDD 5.00 MHz, Crystal oscillation (fXX VDD = 5.0 MHz)Note 3 operating mode VDD VDD 5.00 MHz, Crystal oscillation VDD (fXX = 2.5 MHz)Note 2 VDD HALT mode 5.00 MHz, Crystal oscillation (fXX VDD = 5.0 MHz)Note 3 HALT mode VDD VDD 32.768 kHz, Crystal oscillation VDD operating modeNote 4 VDD VDD 32.768 kHz, Crystal oscillation VDD Note 4 HALT mode VDD VDD XT1 = VDD STOP mode VDD When feedback resistor is connected VDD VDD XT1 = VDD STOP mode VDD When feedback resistor is disconnected VDD 5.00 MHz, Crystal oscillation (fXX = 2.5 MHz)Note 2 operating mode = = = = = = = = = = = = = = = = = = = = = = 5.0 3.0 2.2 5.0 3.0 5.0 3.0 2.2 5.0 3.0 5.0 3.0 2.2 5.0 3.0 2.2 5.0 3.0 2.2 5.0 3.0 2.2 V V V V V V V V V V V V V V V V V V V V V V ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 %Note 5 %Note 6 %Note 6 %Note 5 %Note 6 % % % % % % % % % % % % % % % % % 40 5.0 0.7 0.4 9.0 1.0 1.4 500 280 1.6 650 135 95 70 25 5 2.5 1 0.5 0.3 0.1 0.05 0.05 Notes 1. Current flowing VDD and AVDD pin. Not including A/D converter, on-chip pull-up resistors or LCD dividing resistors. 2. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H) 3. Main system clock fXX = fX operation (when OSMS is set to 01H) 4. When the main system clock is stopped. 5. High-speed mode operation (when processor clock control register (PCC) is set to 00H) 6. Low-speed mode operation (when PCC is set to 04H) Remark Unless specified otherwise, the characteristics of dual-function pins are the same as the those of port pins. 34 µPD78P064B DC CHARACTERISTICS (TA = –10 to +85 °C) (1) Static Display Mode (VDD = 2.0 to 6.0 V) Parameter LCD drive voltage LCD dividing resistor LCD output voltage deviationNote (common) LCD output voltage deviationNote (segment) Note Symbol Test Conditions VLCD RLCD VODC IO = ±5 µA VODS IO = ±1 µA 2.0 V ≤ VLCD ≤ VDD VLCD0 = VLCD MIN. TYP. MAX. Unit 2.0 60 100 VDD 150 V kΩ 0 ±0.2 V 0 ±0.2 V The voltage deviation is the difference from the out voltage corresponding to the ideal value of the segment and common outputs (VLCDn; n = 0, 1, 2). (2) 1/3 Bias Method (VDD = 2.5 to 6.0 V) Parameter LCD drive voltage LCD dividing resistor LCD output voltage deviationNote (common) LCD output voltage deviationNote (segment) Note Symbol Test Conditions VLCD RLCD VODC IO = ±5 µA VODS IO = ±1 µA 2.5 V ≤ VLCD ≤ VDD VLCD0 = VLCD 2 VLCD1 = VLCD × 3 1 VLCD2 = VLCD × 3 MIN. TYP. MAX. Unit 2.5 60 100 VDD 150 V kΩ 0 ±0.2 V 0 ±0.2 V The voltage deviation is the difference from the out voltage corresponding to the ideal value of the segment and common outputs (VLCDn; n = 0, 1, 2). (3) 1/2 Bias Method (VDD = 2.7 to 6.0 V) Parameter Symbol LCD drive voltage VLCD LCD dividing resistor LCD output voltage deviationNote (common) LCD output voltage deviationNote(segment) RLCD Note Test Conditions VODC IO = ±5 µA VODS IO = ±1 µA 2.7 V ≤ VLCD ≤ VDD VLCD0 = VLCD 1 VLCD1 = VLCD × 2 VLCD2 = VLCD1 MIN. TYP. MAX. Unit 2.7 60 100 VDD 150 V kΩ 0 ±0.2 V 0 ±0.2 V The voltage deviation is the difference from the out voltage corresponding to the ideal value of the segment and common outputs (VLCDn; n = 0, 1, 2). 35 µPD78P064B AC CHARACTERISTICS (1) Basic Operation (TA = –40 to +85 °C, VDD = 2.0 to 6.0 V) Parameter Cycle time (Min. instruction execution time) Symbol TCY Test Conditions Operating on main system clock (fXX = 2.5 MHz)Note 1 Operating on main system clock (fXX = 5.0 MHz)Note 2 MIN. VDD = 2.7 to 6.0 V 4.5 ≤ VDD ≤ 6.0 V 2.7 ≤ VDD < 4.5 V TI00 input high/ low-level width 122 MAX. Unit 64 64 32 32 µs µs µs µs 125 µs tTIH00, 4.5 V ≤ VDD ≤ 6.0 V 2/fsam+0.1Note 4 µs tTIL00 2.7 V ≤ VDD < 4.5 V 2/fsam+0.2Note 4 µs 2.0 V ≤ VDD < 2.7 V Note 4 µs TI01 input high/ low-level width tTIH01, TI input frequency fTI TI1, TI2 input high/low-level width tTIH, tTIL Interrupt input tINTH, INTP0 high/low-level tINTL INTP1-INTP5, P110-P117 2/fsam+0.5 VDD = 2.7 to 6.0 V tTIL01 VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V VDD = 2.7 to 6.0 V width RESET low level width 0.8 2.2 0.4 0.8 40Note 3 Operating on subsystem clock TYP. tRST 10 µs 20 µs 0 4 MHz 0 275 kHz 100 ns 1.8 µs 8/fsamNote 4 µs 10 µs 20 µs VDD = 2.7 to 6.0 V 10 20 µs µs Notes 1. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H) 2. Main system clock fXX = fX operation (when OSMS is set to 01H) 3. This is the value when the external clock is used. The value is 114 µs (min.) when the crystal resonator is used. 4. In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS), selection of fsam is possible between fXX/2N+1, fXX/32, fXX/64 and fXX/128 (when N = 0 to 4). 36 µPD78P064B TCY vs VDD (At main system clock fXX = fX/2 operation) TCY vs VDD (At main system clock fXX = fX operation) 60 60 Cycle Time TCY [µ s] Cycle Time TCY [µ s] 32 10 Guaranteed Operation Range 2.0 10 Guaranteed Operation Range 2.0 1.0 0.8 1.0 0.8 0.4 0.4 0 1 2 3 4 5 6 0 Supply Voltage VDD [V] 1 2 3 4 5 6 Supply Voltage VDD [V] (2) Serial Interface (TA = –40 to +85 °C, VDD = 2.0 to 6.0 V) (a) Serial interface channel 0 (i) 3-wire serial I/O mode (SCK0... Internal clock output) Parameter Symbol SCK0 cycle time tKCY1 SCK0 high/low-level width tKH1, tKL1 SI0 setup time (to SCK0↑) tSIK1 SI0 hold time (from SCK0↑) tKSI1 SO0 output delay time from SCK0↓ tKSO1 Test Conditions 4.5 V ≤ VDD ≤ 6.0 V 2.7 V ≤ VDD < 4.5 V VDD = 4.5 to 6.0 V 4.5 V ≤ VDD ≤ 6.0 V 2.7 V ≤ VDD < 4.5 V C = 100 pFNote MIN. TYP. MAX. Unit 800 1600 3200 tKCY1/2–50 tKCY1/2–100 100 150 300 ns ns ns ns ns ns ns ns 400 ns 300 ns Note C is the load capacitance of SCK0, SO0 output line. 37 µPD78P064B (ii) 3-wire serial I/O mode (SCK0...External clock input) Parameter Symbol Test Conditions SCK0 cycle time tKCY2 4.5 V ≤ VDD ≤ 6.0 V 2.7 V ≤ VDD < 4.5 V SCK0 high/low-level width tKH2, tKL2 4.5 V ≤ VDD ≤ 6.0 V 2.7 V ≤ VDD < 4.5 V SI0 setup time (to SCK0↑) MIN. TYP. MAX. Unit 800 1600 3200 400 800 1600 ns ns ns ns ns ns tSIK2 100 ns SI0 hold time (from SCK0↑) tKSI2 400 ns SO0 output delay time from SCK0↓ tKSO2 SCK0 rise, fall time C = 100 pFNote tR2, tF2 300 ns 1000 ns MAX. Unit Note C is the load capacitance of SO0 output line. (iii) SBI mode (SCK0...Internal clock output) Parameter Symbol Test Conditions VDD = 4.5 to 6.0 V SCK0 cycle time SCK0 high/low-level width MIN. TYP. 800 ns 3200 ns tKCY3/2–50 ns tKCY3/2–150 ns 100 ns 300 ns tKCY3/2 ns tKCY3 tKH3, VDD = 4.5 to 6.0 V tKL3 SB0, SB1 setup time (to SCK0↑) tSIK3 SB0, SB1 hold time (from SCK0↑) tKSI3 VDD = 4.5 to 6.0 V SB0, SB1 output delay time from SCK0↓ tKSO3 SB0, SB1↓ from SCK0↑ tKSB tKCY3 ns SCK0↓ from SB0, SB1↓ tSBK tKCY3 ns SB0, SB1 high-level width tSBH tKCY3 ns SB0, SB1 low-level width tSBL tKCY3 ns R = 1 kΩ , C = 100 pFNote VDD = 4.5 to 6.0 V 0 250 ns 0 1000 ns Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line. 38 µPD78P064B (iv) SBI mode (SCK0...External clock input) Parameter Symbol Test Conditions VDD = 4.5 to 6.0 V SCK0 cycle time SCK0 high/low-level width MIN. TYP. MAX. Unit 800 ns 3200 ns 400 ns 1600 ns 100 ns 300 ns tKCY4/2 ns tKCY4 tKH4, VDD = 4.5 to 6.0 V tKL4 SB0, SB1 setup time (to SCK0↑) tSIK4 SB0, SB1 hold time (from SCK0↑) tKSI4 VDD = 4.5 to 6.0 V SB0, SB1 output delay time from SCK0↓ tKSO4 SB0, SB1↓ from SCK0↑ tKSB tKCY4 ns SCK0↓ from SB0, SB1↓ tSBK tKCY4 ns SB0, SB1 high-level width tSBH tKCY4 ns SB0, SB1 low-level width tSBL tKCY4 ns SCK0 rise, fall time tR4, tF4 R = 1 kΩ , C = 100 VDD = 4.5 to 6.0 V pFNote 0 300 ns 0 1000 ns 1000 ns MAX. Unit Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line. (v) 2-wire serial I/O mode (SCK0... Internal clock output) Parameter Symbol SCK0 cycle time tKCY5 SCK0 high-level width tKH5 SCK0 low-level width tKL5 SB0, SB1 setup time (to SCK0↑) tSIK5 SB0, SB1 hold time (from SCK0↑) tKSI5 SB0, SB1 output delay time from SCK0↓ tKSO5 Test Conditions VDD = 2.7 to 6.0 V VDD = 2.7 to 6.0 V R = 1 kΩ, C = 100 pFNote VDD = 4.5 to 6.0 V 4.5 V ≤ VDD ≤ 6.0 V 2.7 V ≤ VDD < 4.5 V MIN. TYP. 1600 3200 tKCY5/2–160 tKCY5/2–190 tKCY5/2–50 tKCY5/2–100 300 350 400 ns ns ns ns ns ns ns ns ns 600 ns 300 ns Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line. 39 µPD78P064B (vi) 2-wire serial I/O mode (SCK0... External clock input) Parameter Symbol Test Conditions TYP. MAX. Unit 1600 3200 650 1300 800 1600 ns ns ns ns ns ns tSIK6 100 ns SB0, SB1 hold time (from SCK0↑) tKSI6 tKCY6/2 ns SB0, SB1 output delay time from SCK0↓ tKSO6 SCK0 rise, fall time tR6, tF6 SCK0 cycle time tKCY6 SCK0 high-level width tKH6 SCK0 low-level width tKL6 SB0, SB1 setup time (to SCK0↑) VDD = 2.7 to 6.0 V MIN. VDD = 2.7 to 6.0 V VDD = 2.7 to 6.0 V R = 1 kΩ, VDD = 4.5 to 6.0 V C = 100 pFNote 0 0 300 500 ns ns 1000 ns MAX. Unit Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line. (b) Serial interface channel 2 (i) 3-wire serial I/O mode (SCK2... Internal clock output) Parameter Symbol SCK2 cycle time tKCY7 SCK2 high/low-level width tKH7, tKL7 SI2 setup time (to SCK2↑) tSIK7 SI2 hold time (from SCK2↑) tKSI7 SO2 output delay time from SCK2↓ tKSO1 Test Conditions 4.5 V ≤ VDD ≤ 6.0 V 2.7 V ≤ VDD < 4.5 V VDD = 4.5 to 6.0 V 4.5 V ≤ VDD ≤ 6.0 V 2.7 V ≤ VDD < 4.5 V C = 100 pFNote Note C is the load capacitance of SCK2, SO2 output line. 40 MIN. TYP. 800 1600 3200 tKCY7/2–50 tKCY7/2–100 100 150 300 ns ns ns ns ns ns ns ns 400 ns 300 ns µPD78P064B (ii) 3-wire serial I/O mode (SCK2...External clock input) Parameter Symbol Test Conditions SCK2 cycle time tKCY8 4.5 V ≤ VDD ≤ 6.0 V 2.7 V ≤ VDD < 4.5 V SCK2 high/low-level width tKH8, tKL8 4.5 V ≤ VDD ≤ 6.0 V 2.7 V ≤ VDD < 4.5 V SI2 setup time (to SCK2↑) MIN. TYP. MAX. Unit 800 1600 3200 400 800 1600 ns ns ns ns ns ns tSIK8 100 ns SI2 hold time (from SCK2↑) tKSI8 400 ns SO2 output delay time from SCK2↓ tKSO8 SCK2 rise, fall time C = 100 pFNote tR8, tF8 300 ns 1000 ns MAX. Unit 78125 39063 19531 bps bps bps MAX. Unit 39063 19531 9766 ns ns ns ns ns ns bps bps bps 1000 ns Note C is the load capacitance of SO2 output line. (iii) UART mode (Dedicated baud rate generator output) Parameter Symbol Test Conditions MIN. TYP. 4.5 V ≤ VDD ≤ 6.0 V 2.7 V ≤ VDD < 4.5 V Transfer rate (iv) UART mode (External clock input) Parameter Symbol ASCK cycle time tKCY9 ASCK high/low-level width tKH9, tKL9 4.5 V ≤ VDD ≤ 6.0 V 2.7 V ≤ VDD < 4.5 V 4.5 V ≤ VDD ≤ 6.0 V 2.7 V ≤ VDD < 4.5 V 4.5 V ≤ VDD ≤ 6.0 V 2.7 V ≤ VDD < 4.5 V Transfer rate ASCK rise, fall time Test Conditions tR9, tF9 MIN. TYP. 800 1600 3200 400 800 1600 41 µPD78P064B AC Timing Test Point (Excluding X1, XT1 Input) 0.8 VDD 0.2 VDD 0.8 VDD 0.2 VDD Test Points Clock Timing 1/fX tXL tXH VIH3 (MIN.) VIL3 (MAX.) X1 Input 1/fXT tXTL tXTH VIH4 (MIN.) VIL4 (MAX.) XT1 Input TI Timing tTIL00, tTIL01 tTIH00, tTIH01 TI00, TI01 1/fTI tTIL TI1, TI2 42 tTIH µPD78P064B Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm tRn tFn SCK0, SCK2 tSIKm SI0, SI2 tKSIm Input Data tKSOm SO0, SO2 Output Data m = 1, 2, 7, 8 n = 2, 8 SBI mode (bus release signal transfer): tKCY3, 4 tKL3, 4 tKH3, 4 tR4 tF4 SCK0 tKSB tSBL tSBK tSBH tSIK3, 4 tKSI3, 4 SB0, SB1 tKSO3, 4 SBI mode (command signal transfer): tKCY3, 4 tKL3, 4 tKH3, 4 tR4 tF4 SCK0 tKSB tSBK tSIK3, 4 tKSI3.4 SB0, SB1 tKSO3, 4 43 µPD78P064B 2-wire serial I/O mode: tKCY5.6 tKL5, 6 tKH5, 6 tR6 tF6 SCK0 tSIK5, 6 tKSI5, 6 tKSO5, 6 SB0, SB1 UART mode: tKCY9 tKL9 tKH9 tR9 tF9 ASCK A/D Converter (TA = –40 to +85 °C, AVDD = VDD = 4.5 to 6.0 V, AVSS = V SS = 0 V) Parameter Symbol Test Conditions Resolution Overall error MIN. TYP. MAX. Unit 8 8 8 bit 2.0 % 200 µs 4.5 V ≤ AVREF ≤ AVDD Note Conversion time tCONV 19.1 Sampling time tSAMP 12/fXX Analog input voltage VIAN AVSS AVREF V Reference voltage AVREF 2.0 AVDD V AVREF-AVSS resistance RAIREF 4 µs 14 Note Quantization error (±1/2 LSB) is not included. This is expressed in proportion to the full-scale value. 44 kΩ µPD78P064B DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = –40 to +85 °C) Parameter Symbol Data retention supply voltage VDDDR Data retention power supply current IDDDR Release signal set time tSREL Oscillation stabilization wait time Note Test Conditions MIN. TYP. MAX. Unit 6.0 V 10 µA 1.8 VDDDR = 1.8 V Subsystem clock stop and feed-back resistor disconnected 0.1 µs 0 Release by RESET 217/fX ms Release by interrupt Note ms tWAIT In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register (OSTS), selection of 212/fXX and 214/fXX to 217/fXX is possible. Data Retention Timing (STOP Mode Release by RESET) Internal Reset Operation HALT Mode Operating Mode STOP Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT Mode Operating Mode STOP Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT 45 µPD78P064B Interrupt Input Timing tINTL tINTH INTP0–INTP5 RESET Input Timing tRSL RESET 46 µPD78P064B PROM PROGRAMMING CHARACTERISTICS DC Characteristics (1) PROM Write Mode (TA = 25 ± 5 ˚C, VDD = 6.5 ± 0.25 V, VPP = 12.5 ± 0.3 V) Symbol SymbolNote Input voltage, high VIH VIH Input voltage, low VIL VIL Output voltage, high VOH VOH IOH = –1 mA Output voltage, low VOL VOL IOL = 1.6 mA ILI ILI 0 ≤ VIN ≤ VDD VPP supply voltage VPP VPP 12.2 VDD supply voltage VDD VCC 6.25 VPP supply current IPP IPP VDD supply current IDD ICC Parameter Input leakage current Note Test Conditions MIN. TYP. MAX. Unit 0.7 VDD VDD V 0 0.3 VDD V VDD –1.0 V 0.4 V +10 µA 12.5 12.8 V 6.5 6.75 V 50 mA 50 mA MAX. Unit –10 PGM = VIL Symbol corresponding to the µPD27C1001A. (2) PROM Read Mode (TA = 25 ± 5 ˚C, VDD = 5.0 ± 0.5 V, VPP = VDD ± 0.6 V) Symbol SymbolNote Input voltage, high VIH VIH 0.7 VDD VDD V Input voltage, low VIL VIL 0 0.3 VDD V VOH1 VOH1 IOH = –1 mA VDD –1.0 V VOH2 VOH2 IOH = –100 µA VDD –0.5 V VOL VOL IOL = 1.6 mA Input leakage current ILI ILI 0 ≤ VIN ≤ VDD Output leakage current ILO ILO 0 ≤ VOUT ≤ VDD, OE = VIH VPP supply voltage VPP VPP VDD –0.6 VDD supply voltage VDD VCC 4.5 VPP supply current IPP IPP VDD supply current IDD ICCA1 Parameter Output voltage, high Output voltage, low Note Test Conditions MIN. TYP. 0.4 V –10 +10 µA –10 +10 µA VDD VDD +0.6 V 5.0 5.5 V VPP = VDD 100 µA CE = VIL, VIN = VIH 50 mA Symbol corresponding to the µPD27C1001A. 47 µPD78P064B AC Characteristics (1) PROM Write Mode (a) Page program mode (TA = 25 ± 5 °C, VDD = 6.5 ± 0.25 V, VPP = 12.5 ± 0.3 V) Symbol SymbolNote Address setup time (to OE↓) tAS tAS 2 µs OE setup time tOES tOES 2 µs CE setup time (to OE↓) tCES tCES 2 µs Input data setup time (to OE↓) tDS tDS 2 µs tAH tAH 2 µs tAHL tAHL 2 µs tAHV tAHV 0 µs Input data hold time (from OE↑) tDH tDH 2 µs Data output float delay time from OE↑ tDF tDF 0 VPP setup time (to OE↓) tVPS tVPS 1.0 ms VDD setup time (to OE↓) tVDS tVCS 1.0 ms Program pulse width tPW tPW 0.095 Valid data delay time from OE↓ tOE tOE OE pulse width during data latching tLW tLW 1 µs PGM setup time tPGMS tPGMS 2 µs CE hold time tCEH tCEH 2 µs OE hold time tOEH tOEH 2 µs Parameter Address hold time (from OE↑) Note (b) Test Conditions MIN. TYP. MAX. 250 0.1 Unit ns 0.105 ms 1 µs Corresponding µPD27C1001A symbol Byte program mode (TA = 25 ± 5 °C, VDD = 6.5 ± 0.25 V, VPP = 12.5 ± 0.3 V) Symbol SymbolNote Address setup time (to PGM↓) tAS tAS 2 µs OE setup time tOES tOES 2 µs CE setup time (to PGM↓) tCES tCES 2 µs Input data setup time (to PGM↓) tDS tDS 2 µs Address hold time (from OE↑) tAH tAH 2 µs nput data hold time (from PGM↑) tDH tDH 2 µs Data output float delay time from OE↑ tDF tDF 0 VPP setup time (to PGM↓) tVPS tVPS 1.0 ms VDD setup time (to PGM↓) tVDS tVCS 1.0 ms Program pulse width tPW tPW 0.095 Valid data delay time from OE↓ tOE tOE OE hold time tOEH — Parameter Note 48 Corresponding µPD27C1001A symbol Test Conditions MIN. 2 TYP. MAX. 250 0.1 Unit ns 0.105 ms 1 µs µs µPD78P064B (2) PROM Read Mode (TA = 25 ± 5 °C, VDD = 5.0 ± 0.5 V, VPP = VDD ± 0.6 V) Symbol SymbolNote Data output time from address tACC tACC Data output delay time from CE↓ tCE Data output delay time from OE↓ Parameter MAX. Unit CE = OE = VIL 800 ns tCE OE = VIL 800 ns tOE tOE CE = VIL 200 ns Data output float delay time from OE↑ tDF tDF CE = VIL 0 60 ns Data hold time from address tDH tDH CE = OE = VIL 0 Note Test Conditions MIN. TYP. ns Corresponding µPD27C1001A symbol (3) PROM Programming Mode Setting (TA = 25 °C, VSS = 0 V) Parameter Symbol PROM programming mode setup time Test Conditions MIN. tSMA TYP. MAX. Unit µs 10 PROM Write Mode Timing (Page program mode) Page Data Latch Page Program Program Verify A2–A16 tAS tALH tAHV tDS tDH tDF A0, A1 D0–D7 Hi–Z Hi–Z Hi–Z tPGMS tVPS Data Input tDF VPP Data Output tAH VPP VDD tVDS VDD + 1.5 VDD VDD tCES tDEH VIH CE VIL tCEH tPW VIH PGM VIL tLW tDES VIH OE VIL 49 µPD78P064B PROM Write Mode Timing (Byte program mode) Program Program/Verify A0–A16 t AS D0–D7 t DF Hi-Z Hi-Z Data Input t DS Hi-Z Data Output t DH t AH VPP VPP VDD t VPS VDD + 1.5 VDD VDD t VDS t DEM VIH CE VIL t CES t PW VIH PGM VIL t OES t OE VIH OE VIL Cautions 1. VDD must be applied before VPP and cut off after VPP. 2. VPP must not exceed +13.5 V including overshoot. 3. Removing and reinserting may adversely affect in reliability while +12.5 V is applied to VPP. PROM Read Mode Timing Effective Address A0–A16 VIH CE VIL t CE VIH OE VIL Note 1 t ACC D0–D7 Hi-Z t DF Note 1 t OE Note 2 t OH Data Output Hi-Z Notes 1. When reading within the tACC range, the OE input delay time from the CE fall time must be maximum of tACC – tOE. 2. tDF is the time from the point at which either OE or CE (whichever is first) reaches VIH. 50 µPD78P064B PROM Programming Mode Setting Timing VDD VPP 0 RESET VDD VPP 0 t SMA A0–A16 Effective Address 51 µPD78P064B 7. PACKAGE DRAWINGS 100 PIN PLASTIC QFP (FINE PITCH) ( 14) A B 75 76 51 50 F Q R S D C detail of lead end 26 25 100 1 G H I M J M P K N L NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. Remark Dimensions and materials of ES products are the same as those of the mass production product. ITEM MILLIMETERS INCHES A 16.0±0.2 B 14.0±0.2 0.630±0.008 0.551 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 16.0±0.2 0.630±0.008 F G 1.0 1.0 H 0.22 +0.05 –0.04 0.039 0.039 0.009±0.002 0.004 I 0.10 J 0.5 (T.P.) K 1.0±0.2 0.039 +0.009 –0.008 L 0.5±0.2 0.020 +0.008 –0.009 M 0.17 +0.03 –0.07 0.007 +0.001 –0.003 N 0.10 P 1.45 0.057 Q 0.125±0.075 0.005±0.003 R S 5°±5° 1.7 MAX. 0.020 (T.P.) 0.004 5°±5° 0.067 MAX. P100GC-50-7EA-2 52 µPD78P064B 100 PIN PLASTIC LQFP (FINE PITCH) (14×14) A B 75 76 51 50 detail of lead end S C D Q R 26 25 100 1 F G H I M J K P M N NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. Remark L ITEM MILLIMETERS INCHES A 16.00±0.20 0.630±0.008 B 14.00±0.20 0.551 +0.009 –0.008 C 14.00±0.20 0.551 +0.009 –0.008 D 16.00±0.20 0.630±0.008 F 1.00 0.039 G 1.00 0.039 H 0.22 +0.05 –0.04 0.009±0.002 I 0.08 0.003 J 0.50 (T.P.) 0.020 (T.P.) K 1.00±0.20 0.039 +0.009 –0.008 L 0.50±0.20 0.020 +0.008 –0.009 M 0.17 +0.03 –0.07 0.007 +0.001 –0.003 N 0.08 0.003 Dimensions and materials of ES products are the P 1.40±0.05 0.055±0.002 Q 0.10±0.05 0.004±0.002 same as those of the mass production product. R 3° +7° –3° 3° +7° –3° S 1.60 MAX. 0.063 MAX. S100GC-50-8EU 53 µPD78P064B 100 PIN PLASTIC QFP (14 × 20) A B Q F G H I M 5°±5° 31 30 S 100 1 detail of lead end D 51 50 C 80 81 J M P K N L P100GF-65-3BA1-2 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. Remark MILLIMETERS INCHES A 23.6 ± 0.4 0.929 ± 0.016 B 20.0 ± 0.2 0.795+0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.6 ± 0.4 0.693 ± 0.016 F 0.8 0.031 G 0.6 0.024 H 0.30 ± 0.10 0.012+0.004 –0.005 I 0.15 0.006 J 0.65 (T.P.) 0.026 (T.P.) K 1.8 ± 0.2 0.071+0.008 –0.009 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.10 0.004 P 2.7 0.106 Dimensions and materials of ES Q 0.1 ± 0.1 0.004 ± 0.004 products are the same as those of the S 3.0 MAX. 0.119 MAX. mass production product. 54 ITEM µPD78P064B 8. RECOMMENDED SOLDERING CONDITIONS The µPD78P064B should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact our sales personnel. Table 8-1. Surface Mounting Type Soldering Conditions (1) µPD78P064BGC-7EA: 100-pin plastic QFP (fine pitch) (14 × 14 mm) µPD78P064BGC-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm) Soldering Method Soldering Conditions Recommended Soldering Symbols Infrared reflow Package peak temperature: 235 °C, Duration: 30 sec. max. (at 210 °C or above), Number of times: Twice max., Time limit: 7 daysNote (thereafter 10 hours prebaking required at 125 °C) <Precaution> Products cannot be baked while packed in anything other than in a heat resistant tray (i.e. they cannot be baked in a magazine, taping, or heat-labile tray). IR35-107-2 VPS Package peak temperature: 235 °C, Duration: 30 sec. max. (at 210 °C or above), Number of times: Twice max., Time limit: 7 daysNote (thereafter 10 hours prebaking required at 125 °C) <Precaution> Products cannot be baked while packed in anything other than in a heat resistant tray (i.e. they cannot be baked in a magazine, taping, or heat-labile tray). VP15-107-2 Partial heating Pin temperature: 300 °C max., Duration: 3 sec. max. (per device side) Note — For the storage period after dry-pack decapsulation, storage conditions are max. 25 °C, 65 % RH. (2) µPD78P064BGF-3BA: 100-pin plastic QFP (14 × 20 mm) Soldering Method Soldering Conditions Recommended Soldering Symbols Infrared reflow Package peak temperature: 235 °C, Duration: 30 sec. max. (at 210 °C or above), Number of times: Three times max. IR35-00-3 VPS Package peak temperature: 215 °C, Duration: 40 sec. (at 200 °C or above), Number of times: Three times max. VP15-00-3 Wave soldering Solder bath temperature: 260 °C max., Duration: 10 sec. max., Number of times: Once, Preheating temperature: 120 °C max. (Package surface temperature) WS60-00-1 Partial heating Pin temperature: 300 °C max., Duration: 3 sec. max. (per device side) Caution — Use of more than one soldering method should be avoided (except in the case of partial heating). 55 µPD78P064B APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using µPD78P064B. Language Processing Software RA78K/0Note 1, 2, 3, 4 78K/0 series common assembler package Note 1, 2, 3, 4 78K/0 series common C compiler package CC78K/0 DF78064Note 1, 2, 3, 4 µPD78064 subseries common device file CC78K/0-LNote 1, 2, 3, 4 78K/0 series common C compiler library source file PROM Writing Tools PG-1500 PROM programmer PA-78P064GC Programmer adapters connected to PG-1500 PA-78P064GF PA-PG-1500 controllerNote 1, 2 PG-1500 control program Debugging Tools IE-78000-R 78K/0 series common in-circuit emulators IE-78000-R-A 78K/0 series common in-circuit emulators (for integrated debugger) IE-78000-R-BK 78K/0 series common break board IE-780308-R-EM µPD780308 subseries common evaluation emulation boards EP-78064GC-R µPD78064 subseries common emulation probes EP-78064GF-R TGC-100SDW Adapter to be mounted on a target system board made for 100-pin plastic QFP (GC-7EA, GC-8EU type) A product of Tokyo Eletech Corp. (Tokyo 03-5295-1661). When purchasing this product, consult your NEC distributor. EV-9200GF-100 Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) SM78K0Note 5, 6, 7 78K/0 series common system simulators ID78K0Note 4, 5, 6, 7 IE-78000-R-A integrated debuggers SD78K/0Note 1, 2 IE-78000-R screen debuggers DF78064Note 1, 2, 4, 5, 6, 7 µPD78064 subseries common device file Real-Time OS 56 RX78K/0Note 1, 2, 3, 4 78K/0 series real-time OS MX78K/0Note 1, 2, 3, 4 78K/0 series OS µPD78P064B Fuzzy Inference Development Support System FE9000Note 1, FE9200Note 6 Fuzzy knowledge data creation tool FT9080Note 1, FT9085Note 2 Translator FI78K/IINote 1, 2 Fuzzy inference module FD78K/IINote 1, 2 Fussy inference debugger Notes 1. PC-9800 series (MS-DOSTM) based 2. IBM PC/ATTM and compatible machines (PC DOSTM/IBM DOSTM/MS-DOS) based 3. HP9000 series 300TM (HP-UXTM) based 4. HP9000 series 700TM (HP-UX) based, SPARCstationTM (SunOSTM) based, EWS4800 series (EWS-UX/V) based 5. PC-9800 series (MS-DOS + WindowsTM) based 6. IBM PC/AT and compatible machines (PC DOS/IBM DOS/MS-DOS + Windows) based 7. NEWSTM (NEWS-OSTM) based Remarks 1. For third party development tools, refer to 78K/0 Series Selection Guide (U11126E). 2. RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, and RX78K/0 are used in combination with DF78064. 57 µPD78P064B CONVERSION SOCKET (EV-9200GF-100) PACKAGE DRAWINGS AND RECOMMENDED BOARD MOUNTING PATTERN Figure A-1. EV-9200GF-100 Package Drawing A B E M N O L K S J D C R F EV-9200GF-100 Q 1 No.1 pin index P G H I EV-9200GF-100-G0 ITEM 58 MILLIMETERS INCHES A 24.6 0.969 B 21 0.827 C 15 0.591 D 18.6 0.732 E 4-C 2 4-C 0.079 F 0.8 0.031 G 12.0 0.472 H 22.6 0.89 I 25.3 0.996 J 6.0 0.236 K 16.6 0.654 L 19.3 076 M 8.2 0.323 N 8.0 0.315 O 2.5 0.098 P 2.0 0.079 Q 0.35 0.014 R φ 2.3 φ 0.091 S φ 1.5 φ 0.059 µPD78P064B Figure A-2. EV-9200GF-100 Board Mounting Pattern G J H D F E K I L C B A EV-9200GF-100-P0 ITEM MILLIMETERS A 26.3 B 21.6 INCHES 1.035 0.85 C 0.65±0.02 × 29=18.85±0.05 D +0.003 0.65±0.02 × 19=12.35±0.05 0.026+0.001 –0.002 × 0.748=0.486 –0.002 0.026+0.001 –0.002 × 1.142=0.742+0.002 –0.002 E 15.6 0.614 F 20.3 0.799 G 12 ± 0.05 0.472+0.003 –0.002 H 6 ± 0.05 0.236+0.003 –0.002 I 0.35 ± 0.02 0.014+0.001 –0.001 J φ 2.36 ± 0.03 φ 0.093+0.001 –0.002 K φ 2.3 φ 0.091 L φ 1.57 ± 0.03 φ 0.062+0.001 –0.002 Caution Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). 59 µPD78P064B CONVERSION ADAPTER (TGC-100SDW) PACKAGE DRAWINGS Figure A-3. TGC-100SDW Package Drawing Reference diagram: TGC-100SDW Package dimension (unit: mm) A B X N L M V F E D H I J K O X T Protrusion height W C PQR S U G Y Z e a n m k g d c I b j i f h ITEM A INCHES ITEM 0.848 a MILLIMETERS 14.45 INCHES 0.569 B 0.5x24=12 0.020x0.945=0.472 b 1.85±0.25 0.073±0.010 0.5 0.020 0.5x24=12 0.020x0.945=0.472 c d 3.5 2.0 0.138 0.079 E F 15.0 21.55 0.591 0.848 e f 3.9 0.25 0.154 G φ 3.55 φ 0.140 g φ 4.5 φ 0.177 H I 10.9 13.3 0.429 0.524 h i 16.0 1.125±0.3 0.630 0.044±0.012 J K 15.7 18.1 0.618 0.713 j k 0~5° 5.9 0.000~0.197° 0.232 L 13.75 0.5x24=12.0 0.541 0.020x0.945=0.472 l 0.8 0.031 M m 2.4 0.094 N O 1.125±0.3 1.125±0.2 0.044±0.012 0.044±0.008 n 2.7 0.106 P 7.5 0.295 Q R 10.0 11.3 0.394 0.445 T U 60 21.55 C D S Remark Manufactured by Tokyo Eletech Corp. MILLIMETERS 18.1 0.713 φ 5.0 φ 0.197 5.0 0.197 V 4- φ 1.3 4-φ 0.051 W X 1.8 C 2.0 0.071 C 0.079 Y Z φ 0.9 φ 0.3 φ 0.035 φ 0.012 0.010 TGC-100SDW-G0E µPD78P064B APPENDIX B. RELATED DOCUMENTS Device Related Documents Document No. Document Name Japanese English µPD78064B Subseries User’s Manual U10785J U10785E µPD78064B Data Sheet U11590J U11590E µPD78P064B Data Sheet U11598J This document 78K/0 Series User’s Manual (Instruction) U12326J U12326E 78K/0 Series Instruction List U10903J — 78K/0 Series Instruction Set U10904J — µPD78064B Subseries Special Function Register Table Planned — Development Tool Related Documents (User’s Manual) (1/2) Document No. Document Name Japanese English Operation EEU-809 EEU-1399 Language EEU-815 EEU-1404 EEU-817 EEU-1402 Operation U11802J U11802E Assembly language U11801J U11801E Structured assembly language U11789J U11789E Operation EEU-656 EEU-1280 Language EEU-655 EEU-1284 Operation U11517J U11517E Language U11518J U11518E Programming know-how EEA-618 EEA-1208 CC78K Series Library Source File U12322J — PG-1500 PROM Programmer U11940J U11940E PG-1500 Controller PC-9800 Series (MS-DOS) Based EEU-704 EEU-1291 PG-1500 Controller IBM PC Series (PC DOS) Based EEU-5008 U10540E IE-78000-R U11376J U11376E IE-78000-R-A U10057J U10057E IE-78000-R-BK EEU-867 EEU-1427 IE-780308-R-EM U11362J U11362E EP-78064 EEU-934 EEU-1469 RA78K Series Assembler Package RA78K Series Structured Assembler Preprocessor RA78K0 Assembler Package CC78K Series C Compiler CC78K0 C Compiler CC78K/0 C Compiler Application Note 61 µPD78P064B Development Tool Related Documents (User’s Manual) (2/2) Document No. Document Name Japanese English EEU-5002 U10181E SM78K0 System Sumilator Windows Based Reference SM78K Series System Simulator External components user open interface specification U10092J U10092E ID78K0 Integrated Debugger EWS Based Reference U11151J — ID78K0 Integrated Debugger PC Based Reference U11539J U11539E ID78K0 Integrated Debugger Windows Based Guide U11649J U11649E SD78K/0 Screen Debugger Introduction EEU-852 U10539E PC-9800 Series (MS-DOS) Based Reference U10952J — EEU-5024 EEU-1414 U11279J U11279E SD78K/0 Screen Debugger Introduction IBM PC/AT (PC DOS) Based Reference Caution The above related documents are subject to change without notice. For design purpose, etc., be sure to use the latest documents. Embedded Software Related Documents (User’s Manual) Document No. Document Name Japanese English Basic U11537J — Installation U11536J — Basic U12257J — Fuzzy Knowledge Data Creation Tool EEU-829 EEU-1438 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System Translator EEU-862 EEU-1444 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module EEU-858 EEU-1441 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger EEU-921 EEU-1458 78K/0 Series Real-Time OS 78K/0 Series OS MX78K0 Other Related Documents Document Name Document No. Japanese IC Package Manual English C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability and Quality Control C10983J C10983E Electrostatic Discharge (ESD) Test MEM-539 — Semiconductor Devices Quality Guarantee Guide C11893J MEI-1202 Microcomputer-Related Product Guide (Products by Other Manufacturers) U11416J — Caution The above related documents are subject to change without notice. For design purpose, etc., be sure to use the latest documents. 62 µPD78P064B [MEMO] 63 µPD78P064B NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 64 µPD78P064B Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 65 µPD78P064B FIP, QTOP and IEBus are trademarks of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. IBM DOS, PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 series 300, HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Sun OS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. The documents referred to in this publication may include preliminary versions. However preliminary versions are not marked as such. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 2