DATA SHEET MOS INTEGRATED CIRCUIT µ PD8873 (5400 × 5400) PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR DESCRIPTION The µ PD8873 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The µ PD8873 has 3 rows of (5400 + 5400) staggered pixels, and each row has a dual-sided readout-type charge transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 1200 dpi/A4 color image scanners, color facsimiles and so on. FEATURES • Valid photocell : (5400 + 5400) staggered pixels × 3 • Photocell pitch : 5.25 µ m • Line spacing : 63 µ m (12 lines) Red line - Green line, Green line - Blue line • Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 10 lx•hour) • Resolution : 48 dot/mm A4 (210 × 297 mm) size (shorter side) 10.5 µ m (2 lines) Odd line - Even line (for each color) 7 1200 dpi US letter (8.5” × 11”) size (shorter side) • Drive clock level : CMOS output under 5 V operation • Data rate : 12.5 MHz Max. • Power supply : +12 V • On-chip circuits : Reset feed-through level clamp circuits Voltage amplifiers ORDERING INFORMATION Part Number µ PD8873CY Package CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S16614EJ2V0DS00 (2nd edition) Date Published July 2003 NS CP (K) Printed in Japan 2003 µ PD8873 BLOCK DIAGRAM VOD φ SEL 20 19 GND GND 2 11 φ2 φ2 φ1 17 15 14 13 φ TG1 (Blue) 12 φ TG2 (Green) 10 φ TG3 (Red) D67 D68 D66 S10800 S2 Photocell (Blue) D65 ······ D64 VOUT1 21 (Blue) S1 D14 CCD analog shift register Transfer gate Transfer gate CCD analog shift register D67 D68 D66 S10800 S2 Photocell (Green) D65 ······ D64 VOUT2 22 (Green) S1 D14 CCD analog shift register Transfer gate Transfer gate CCD analog shift register D68 D67 D66 S10800 S2 Photocell (Red) D65 ······ D64 1 S1 VOUT3 (Red) D14 CCD analog shift register Transfer gate Transfer gate CCD analog shift register 4 3 φ CLB φ R 2 Data Sheet S16614EJ2V0DS 5 9 8 φ1 φ2 φ1 µ PD8873 PIN CONFIGURATION (Top View) CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) • µ PD8873CY 22 VOUT2 Output signal 2 (Green) Ground GND 2 21 VOUT1 Output signal 1 (Blue) Reset gate clock φR 3 20 VOD Output drain voltage Reset feed-through level clamp clock φ CLB 4 19 φ SEL dpi selector Shift register clock 1 φ1 5 18 NC No connection No connection NC 6 17 φ2 Shift register clock 2 No connection NC 7 16 NC No connection Shift register clock 1 φ1 8 15 φ2 Shift register clock 2 Shift register clock 2 φ2 9 14 φ1 Shift register clock 1 Transfer gate clock 3 (for Red) φ TG3 10 13 φ TG1 Transfer gate clock 1 (for Blue) Ground GND 11 12 φ TG2 Transfer gate clock 2 (for Green) Blue 10800 Green 10800 Red 10800 1 1 1 VOUT3 1 Output signal 3 (Red) Caution Connect the No connection pins (NC) to GND. Data Sheet S16614EJ2V0DS 3 µ PD8873 PHOTOCELL STRUCTURE DIAGRAM 2.5 µ m 5.25 µ m 2.75 µ m Channel stopper Aluminum shield PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing) 5.25 µ m 5.25 µ m 5.25 µ m Blue photocell array Blue photocell array 2 lines (10.5 µ m) 10 lines (52.5 µ m) 5.25 µ m 5.25 µ m 5.25 µ m Green photocell array Green photocell array 2 lines (10.5 µ m) 10 lines (52.5 µ m) 5.25 µ m 5.25 µ m 5.25 µ m 4 Red photocell array Red photocell array Data Sheet S16614EJ2V0DS 12 lines (63 µ m) 2 lines (10.5 µ m) 12 lines (63 µ m) µ PD8873 ABSOLUTE MAXIMUM RATINGS (TA = +25°C) Parameter Symbol Ratings Unit Output drain voltage VOD −0.3 to +15 V Shift register clock voltage Vφ 1, Vφ 2 −0.3 to +8 V Reset gate clock voltage Vφ R −0.3 to +8 V Reset feed-through level clamp clock voltage Vφ CLB −0.3 to +8 V dpi select signal voltage Vφ SEL −0.3 to +8 V Vφ TG1 to Vφ TG3 Transfer gate clock voltage Operating ambient temperature Note Storage temperature −0.3 to +8 V TA 0 to +60 °C Tstg −40 to +70 °C Note Use at the condition without dew condensation. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATING CONDITIONS (TA = +25°C) Parameter Symbol Min. Typ. Max. Unit 12.6 V Output drain voltage VOD 11.4 12.0 Shift register clock high level Vφ 1H, Vφ 2H 4.75 5.0 5.5 V Shift register clock low level Vφ 1L, Vφ 2L 0 0 0.15 V Reset gate clock high level Vφ RH 4.75 5.0 5.5 V Reset gate clock low level Vφ RL 0 0 0.15 V Reset feed-through level clamp clock high level Vφ CLBH 4.75 5.0 5.5 V Reset feed-through level clamp clock low level Vφ CLBL 0 0 0.15 V dpi select signal high level Vφ SELH 4.75 5.0 5.5 V dpi select signal low level Vφ SELL Transfer gate clock high level Vφ TG1H to Vφ TG3H 4.75 Transfer gate clock low level Vφ TG1L to Vφ TG3L 0 0 0 Vφ 1H 0.15 Note 0 Vφ 1H Note 0.15 V V V Data rate fφ R − 2.0 12.5 MHz Clock pulse frequency fφ 1, fφ 2 − 2.0 12.5 MHz Note When Transfer gate clock high level (Vφ TG1H to Vφ TG3H) is higher than Shift register clock high level (Vφ 1H), Image lag can increase. Data Sheet S16614EJ2V0DS 5 µ PD8873 ELECTRICAL CHARACTERISTICS TA = +25°C, VOD = 12 V, data rate (fφ R) = 2 MHz, storage time = 5.5 ms, input signal clock = 5 Vp-p, light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm) Parameter Symbol Min. Typ. Max. Unit Vsat 2.4 2.7 − V Red SER − 0.423 − lx•s Green SEG − 0.431 − lx•s Saturation voltage Saturation exposure Test Conditions − 0.668 − lx•s Photo response non-uniformity PRNU VOUT = 1.0 V − 6 20 % Average dark signal ADS Light shielding − 0.2 2.0 mV Dark signal non-uniformity DSNU Light shielding − 1.5 5.0 mV Power consumption PW − 360 540 mW Output impedance ZO − 0.35 1.00 kΩ RR 4.47 6.38 8.30 V/lx•s Blue Response Red Green RG 4.38 6.26 8.14 V/lx•s Blue RB 2.83 4.04 5.25 V/lx•s − 3.0 7.0 % Image lag IL Offset level Output fall delay time SEB VOUT = 1.0 V VOS Note Total transfer efficiency 6.0 7.0 V VOUT = 1.0 V, t1, t2 = 25 ns − 20 − ns TTE VOUT = 1.0 V, data rate = 12.5 MHz 92 98 − % RI VOUT = 1.0 V − 1.0 4.0 % Red − 630 − nm Green − 540 − nm Register imbalance Response peak 5.0 td − 460 − nm DR1 Vsat/DSNU − 1800 − times DR2 Vsat/σ CDS − 2700 − times Blue Dynamic range Reset feed-through noise Random noise (CDS) RFTN Light shielding −2000 −100 +500 mV PRFTN Light shielding − 500 800 mV σ CDS Light shielding − 1.0 − mV Note When the fall time of φ 1 and φ 2 (t1, t2) is the Typ. value (refer to TIMING CHART 2-1 to 2-3). 6 Data Sheet S16614EJ2V0DS µ PD8873 INPUT PIN CAPACITANCE (TA = +25°C, VOD = 12 V) Parameter Symbol Shift register clock pin capacitance 1 Cφ 1 Pin name φ1 Pin No. Min. Typ. Max. Unit 5 − 370 − pF 8 − 370 − pF − 370 − pF − 1110 − pF 9 − 370 − pF 15 − 370 − pF 17 − 370 − pF − 1110 − pF 14 φ 1 total capacitance Shift register clock pin capacitance 2 Cφ 2 φ2 φ 2 total capacitance Reset gate clock pin capacitance Cφ R φR 3 − 10 − pF Reset feed-through level clamp clock pin capacitance Cφ CLB φ CLB 4 − 10 − pF dpi select signal pin capacitance Cφ SEL φ SEL 19 − 10 − pF Transfer gate clock pin capacitance Cφ TG φ TG1 13 − 100 − pF φ TG2 12 − 100 − pF φ TG3 10 − 100 − pF Remarks 1. 2. Pin 5, 8, 14 (φ 1) and pin 9, 15, 17 (φ 2) are each connected inside of the device. Cφ 1 and Cφ 2 show the equivalent capacity of the real drive including the capacity of between φ 1 and φ 2. Data Sheet S16614EJ2V0DS 7 8 TIMING CHART 1-1 (1200 dpi, bit clamp mode, for each color) φ TG1 to φ TG3 φ1 φ2 φR φ CLB 10864 10865 10866 10867 10868 10869 “H” 59 60 61 62 63 64 65 φ SEL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Data Sheet S16614EJ2V0DS Note Note VOUT1 to VOUT3 Optical black (47 pixels) Valid photocell (10800 pixels) Note Set the φ R to low level and φ CLB to high level during this period. Invalid photocell (4 pixels) µ PD8873 Invalid photocell (4 pixels) TIMING CHART 1-2 (1200 dpi, line clamp mode, for each color) φ TG1 to φ TG3 φ1 φ2 φR Note φ CLB ( φ TG1 to φ TG3) 10864 10865 10866 10867 10868 10869 “H” 59 60 61 62 63 64 65 φ SEL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Data Sheet S16614EJ2V0DS Note VOUT1 to VOUT3 Optical black (47 pixels) Valid photocell (10800 pixels) Note Set the φ R and φ CLB to low level during this period. 9 Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB. Invalid photocell (4 pixels) µ PD8873 Invalid photocell (4 pixels) 10 TIMING CHART 1-3 (600 dpi, bit clamp mode, for each color) φ TG1 to φ TG3 φ1 φ2 φR Note φ CLB 10870 10868 10866 10864 10862 68 66 64 62 60 58 16 14 12 10 8 6 “L” 4 φ SEL 2 Data Sheet S16614EJ2V0DS Note VOUT1 to VOUT3 Valid photocell (5400 pixels) Optical black (24 pixels) Note Set the φ R to low level and φ CLB to high level during this period. Invalid photocell (2 pixels) µ PD8873 Invalid photocell (2 pixels) TIMING CHART 1-4 (600 dpi, line clamp mode, for each color) φ TG1 to φ TG3 φ1 φ2 φR Note φ CLB ( φ TG1 to φ TG3) 10870 10868 10866 10864 10862 68 66 64 62 60 58 16 14 12 10 8 6 “L” 4 φ SEL 2 Data Sheet S16614EJ2V0DS Note VOUT1 to VOUT3 Valid photocell (5400 pixels) Optical black (24 pixels) Note Set the φ R and φ CLB to low level during this period. 11 Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB. Invalid photocell (2 pixels) µ PD8873 Invalid photocell (2 pixels) 12 TIMING CHART 1-5 (300 dpi, bit clamp mode, for each color) φ TG1 to φ TG3 φ1 φ2 φR Note φ CLB 10870 +10872 10866 +10868 10862 +10864 66 +68 62 +64 58 +60 14 +16 10 +12 “L” 6 +8 φ SEL 2 +4 Data Sheet S16614EJ2V0DS Note VOUT1 to VOUT3 Valid photocell (2700 pixels) Optical black (12 pixels) Note Set the φ R to low level and φ CLB to high level during this period. Invalid photocell (1 pixels) µ PD8873 Invalid photocell (1 pixels) TIMING CHART 1-6 (300 dpi, line clamp mode, for each color) φ TG1 to φ TG3 φ1 φ2 φR Note φ CLB ( φ TG1 to φ TG3) 10870 +10872 10866 +10868 10862 +10864 66 +68 62 +64 58 +60 14 +16 10 +12 “L” 6 +8 φ SEL 2 +4 Data Sheet S16614EJ2V0DS Note VOUT1 to VOUT3 Valid photocell (2700 pixels) Optical black (12 pixels) Note Set the φ R and φ CLB to low level during this period. 13 Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB. Invalid photocell (1 pixels) µ PD8873 Invalid photocell (1 pixels) µ PD8873 TIMING CHART 2-1 (1200 dpi, for each color) t2 t1 φ1 90% 10% φ2 90% 10% φR 90% 10% t4 t3 t5 t4 t3 t5 t6 t8 t7 t9 φ CLB (Bit clamp mode) φ CLB “H” (Line clamp mode) t6 t8 t7 t9 t10 90% 10% t11 t12 td td VOUT 10% Symbol Min. Typ. Note Max. Unit t1, t2 0 25 − ns t3 20 50 − ns t4, t5 0 20 − ns t6 15 25 − ns t7 10 50 − ns t8, t9 0 20 − ns t10 5 45 − ns t11 40 − − ns t12 40 − − ns Note Typ. is the case of φ R = 2 MHz. 14 t10 Data Sheet S16614EJ2V0DS µ PD8873 TIMING CHART 2-2 (600 dpi, for each color) t2 φ1 90% 10% φ2 90% 10% φR 90% 10% t1 t4 t3 t5 t6 t8 t7 t9 φ CLB (Bit clamp mode) φ CLB “H” (Line clamp mode) t10 90% 10% t11 t12 td VOUT 10% Symbol Min. Typ. Note Max. Unit t1, t2 0 25 − ns t3 20 50 − ns t4, t5 0 20 − ns t6 15 25 − ns t7 10 50 − ns t8, t9 0 20 − ns t10 5 45 − ns t11 40 − − ns t12 40 − − ns Note Typ. is the case of φ R = 2 MHz. Data Sheet S16614EJ2V0DS 15 µ PD8873 TIMING CHART 2-3 (300 dpi, for each color) t2 φ1 90% 10% φ2 90% 10% φR 90% 10% t1 t3 t4 t5 t6 φ CLB (Bit clamp mode) φ CLB “H” (Line clamp mode) t8 t7 t9 t10 90% 10% t11 t12 td VOUT 10% Symbol Min. Typ. Note Unit t1, t2 0 25 − ns t3 20 50 − ns t4, t5 0 20 − ns t6 15 25 − ns t7 10 50 − ns t8, t9 0 20 − ns t10 5 45 − ns t11 40 − − ns t12 40 − − ns Note Typ. is the case of φ R = 1 MHz. 16 Max. Data Sheet S16614EJ2V0DS µ PD8873 φ TG1 to φ TG3, φ 1, φ 2 TIMING CHART t14 t15 t13 90% 10% t16 φ TG1 to φ TG3 t17 90% φ1 φ2 t18 φR Note 1 t19 10% t6 90% φ CLB (Bit clamp mode) t21 t23 t22 Note 2 t24 90% 10% φ CLB (Line clamp mode) t8 Symbol t6 t20 t9 Min. Typ. Max. Unit 15 25 − ns 0 20 − ns 5000 10000 50000 ns t14, t15 0 50 − ns t16, t17 900 1000 − ns t18, t19 200 400 − ns t20 t8, t9 t13 t13 t13 50000 ns t21, t22 0 50 − ns t23 t6 t6 − ns t24 0 350 − ns Notes 1. Set the φ R to low level and φ CLB to high level during this period. 2. Set the φ R to low level during this period. Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB. Data Sheet S16614EJ2V0DS 17 µ PD8873 φ 1, φ 2 CROSS POINTS t25 t27 φ1 φ2 0.25 V 1.5 V to 3.5 V t26 Min. Typ. Max. Unit t25 Symbol 80 − − ns t26, t27 35 − − ns φ TG, φ SEL TIMING CHART 90% φ TG t28 φ SEL (High to Low) 90% 10% φ SEL (Low to High) Symbol t28 18 Min. Typ. Max. Unit 0 0 − ns Data Sheet S16614EJ2V0DS 4.75 V µ PD8873 SELECTION OF RESOLUTION MODE The µ PD8873 has function of two readout modes, High Resolution Mode and Low Resolution Mode. These two modes can be selected by φ SEL switch. Read Mode φ SEL Description High Resolution Mode 1200 dpi (Max.) High level Low Resolution Mode 600 dpi (Max.) (even line readout mode) Low level (1) High Resolution Mode In this mode, both signals in even lines and odd lines can be read out. This mode enables 1200 dpi (Max.) resolution with A4 size (210 × 297 mm, shorter side). Please refer to TIMING CHART 1-1, 1-2 and 2-1. (2) Low Resolution Mode In this mode, only signal in even lines can be read out. This mode enables 600 dpi (Max.) resolution with A4 size. To use intermittent reset drive enable signal charges of adjacent pixels in even line to add at the charge to voltage conversion area. Then it can achieve low resolution with A4 size such as 300, 200 or 150 dpi. Please refer to TIMING CHART 1-3 to 1-6, 2-2 and 2-3. Data Sheet S16614EJ2V0DS 19 µ PD8873 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = ∆x × 100 x ∆ x : maximum of xj − x 10800 Σx j x= j=1 10800 xj : Output voltage of valid pixel number j VOUT Register Dark DC level x ∆x 4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 10800 Σd j ADS (mV) = j=1 10800 dj : Dark signal of valid pixel number j 20 Data Sheet S16614EJ2V0DS µ PD8873 5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of dj − ADS j = 1 to 10800 dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx•s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line. φ TG Light ON OFF VOUT V1 VOUT IL (%) = V1 × 100 VOUT Data Sheet S16614EJ2V0DS 21 µ PD8873 9. Register imbalance: RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels. n 2 2 n ∑ (V2j –1 – V2j) j=1 RI (%) = n 1 n × 100 ∑ Vj j=1 n : Number of valid pixels Vj : Output voltage of each pixel 10. Offset level : VOS DC level of output signal is defined as follows. 11. Reset feed-through noise : RFTN, PRFTN Reset feed-through noise (RFTN) and peak of RFTN (PRFTN) are defined as follows. + PRFTN VOUT 22 PRFTN – RFTN VOS Data Sheet S16614EJ2V0DS µ PD8873 12. Random noise (CDS) : σ CDS Random noise σ CDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). σ CDS is calculated by the following procedure. 1. One valid photocell in one reading is fixed as measurement point. 2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get “VDi”. 3. The output level is measured during the video output time averaged over 100 ns to get “VOi”. 4. The correlated double sampling output is defined by the following formula. VCDSi = VDi – VOi 5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines). 6. Calculate the standard deviation σ CDS using the following formula equation. 100 σ CDS (mV) = Σ (VCDS – V) i 2 i=1 100 , V= 1 100 Σ VCDS i 100 i = 1 Reset feed-through Video output Data Sheet S16614EJ2V0DS 23 µ PD8873 STANDARD CHARACTERISTIC CURVES (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25°C) 8 2 1 Relative Output Voltage Relative Output Voltage 4 2 1 0.5 0.2 0.25 0.1 0 10 20 30 40 0.1 50 Operating Ambient Temperature TA (°C) 1 5 10 Storage Time (ms) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (TA = +25°C) 100 R B G Response Ratio (%) 80 60 40 G 20 B 0 400 500 600 Wavelength (nm) 24 Data Sheet S16614EJ2V0DS 700 800 µ PD8873 APPLICATION CIRCUIT EXAMPLE +12 V +5 V + + µ PD8873 10 µ F/16 V 0.1 µ F B3 1 2 φR φ CLB 47 Ω 3 47 Ω 4 4.7 Ω 5 6 7 4.7 Ω 8 4.7 Ω 9 φ2 10 Ω 10 11 VOUT3 VOUT2 VOUT1 GND φR VOD φ SEL φ CLB φ1 NC NC φ2 NC NC φ1 φ2 φ2 φ1 φ TG3 φ TG1 φ TG2 GND 22 21 B2 0.1 µ F 47 µ F/25 V +5 V B1 20 + 19 150 Ω 0.1 µ F 10 µ F/16 V 18 17 φ SEL 4.7 Ω 16 15 4.7 Ω 14 4.7 Ω 13 10 Ω 12 10 Ω φ1 φ TG Caution Connect the No connection pins (NC) to GND. Remarks 1. The inverters shown in the above application circuit example are the 74HC04 (fφ R < 2 MHz) or the 74AC04 (2 MHz ≤ fφ R ≤ 12.5 MHz). 2. Inverters B1 to B3 in the above application circuit example are shown in the figure below. B1 to B3 EQUIVALENT CIRCUIT 12 V + 100 Ω CCD VOUT 100 Ω 47 µ F/25 V 2SC945 2 kΩ Data Sheet S16614EJ2V0DS 25 µ PD8873 PACKAGE DRAWING µ PD8873CY CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400)) (Unit : mm) 44.0±0.3 1st valid pixel 0.5±0.3 1 9.25±0.3 12 22 11 1 37.5 4 1.02±0.15 0.46±0.1 2.0 4.39±0.4 2.54±0.25 (5.42) 4 (1.72) 2 2.62±0.2 3 10.16±0.2 0.25±0.05 10.16 +0.7 −0.2 4.21±0.5 Name Plastic cap Dimensions Refractive index 42.7×8.35×0.8(0.7 5) 1.5 1 1st valid pixel The center of the pin1 2 The surface of the CCD chip The top of the cap 3 The bottom of the package The surface of the CCD chip 4 Mirror finished surface 5 Thickness of mirror finished surface 22C-1CCD-PKG17 26 Data Sheet S16614EJ2V0DS µ PD8873 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. Type of Through-hole Device µ PD8873CY : CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) Process Partial heating method Cautions 1. Conditions Pin temperature : 300 °C or below, Heat time : 3 seconds or less (per pin) During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact. 2. Soldering by the solder flow method may have deleterious effects on prevention of plastic cap soiling and heat resistance. So the method cannot be guaranteed. Data Sheet S16614EJ2V0DS 27 µ PD8873 NOTES ON HANDLING THE PACKAGES 1 DUST AND DIRT PROTECTING The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don’t either touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents. CLEANING THE PLASTIC CAP Care should be taken when cleaning the surface to prevent scratches. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. RECOMMENDED SOLVENTS The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent. Solvents Ethyl Alcohol Methyl Alcohol Isopropyl Alcohol N-methyl Pyrrolidone Symbol EtOH MeOH IPA NMP 2 MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating 3 OPERATE AND STORAGE ENVIRONMENTS Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E) 4 ELECTROSTATIC BREAKDOWN CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. 2. 3. 4. 5. 6. 28 Ground the tools such as soldering iron, radio cutting pliers of or pincer. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. Either handle bare handed or use non-chargeable gloves, clothes or material. Ionized air is recommended for discharge when handling CCD image sensor. For the shipment of mounted substrates, use box treated for prevention of static charges. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 MΩ. Data Sheet S16614EJ2V0DS µ PD8873 [MEMO] Data Sheet S16614EJ2V0DS 29 µ PD8873 [MEMO] 30 Data Sheet S16614EJ2V0DS µ PD8873 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S16614EJ2V0DS 31 µ PD8873 • The information in this document is current as of July, 2003. The information is subject to change without notice. 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No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. • NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1