USBLC6-2 Very low capacitance ESD protection Features ■ ■ ■ ■ ■ ■ 2 data lines protection Protects VBUS Very low capacitance: 3.5 pF max. Very low leakage current: 150 nA max. SOT-666 and SOT23-6L packages RoHS compliant SOT23-6L USBLC6-2SC6 Benefits Applications ■ ■ ■ ■ ■ ■ ■ ■ ■ Very low capacitance between lines to GND for optimized data integrity and speed Low PCB space consumption: 2.9 mm2 max for SOT-666 and 9mm² max for SOT23-6L Enhanced ESD protection. IEC 61000-4-2 level 4 compliance guaranteed at device level, hence greater immunity at system level ESD protection of VBUS High reliability offered by monolithic integration Low leakage current for longer operation of battery powered devices Fast response time Consistent D+ / D- signal balance: – Very low capacitance matching tolerance I/O to GND = 0.015 pF – Compliant with USB 2.0 requirements Complies with the following standards ■ IEC 61000-4-2 level 4: – 15 kV (air discharge) – 8 kV (contact discharge) March 2008 ■ ■ ■ ■ ■ SOT-666 USBLC6-2P6 USB 2.0 ports up to 480 Mb/s (high speed) Compatible with USB 1.1 low and full speed Ethernet port: 10/100 Mb/s SIM card protection Video line protection Portable electronics Description The USBLC6-2SC6 and USBLC6-2P6 are monolithic application specific devices dedicated to ESD protection of high speed interfaces, such as USB 2.0, Ethernet links and video lines. The very low line capacitance secures a high level of signal integrity without compromising in protecting sensitive chips against the most stringent characterized ESD strikes. Figure 1. Rev 3 Functional diagram I/O1 1 6 I/O1 GND 2 5 VBUS I/O2 3 4 I/O2 1/14 www.st.com 14 Characteristics 1 USBLC6-2 Characteristics Table 1. Absolute ratings Symbol Parameter IEC 61000-4-2 air discharge IEC 61000-4-2 contact discharge MIL STD883G-Method 3015-7 Value Unit 15 15 25 kV VPP Peak pulse voltage Tstg Storage temperature range -55 to +150 °C Tj Operating junction temperature range -40 to +125 °C TL Lead solder temperature (10 seconds duration) 260 °C Table 2. Electrical characteristics (Tamb = 25 °C) Value Symbol Parameter Test conditions Unit Min. Max. VRM Reverse stand-off voltage IRM Leakage current VRM = 5 V VBR Breakdown voltage between VBUS and GND IR = 1 mA Forward voltage IF = 10 mA 1.1 V IPP = 1 A, 8/20 µs Any I/O pin to GND 12 V IPP = 5 A, 8/20 µs Any I/O pin to GND 17 V VF VCL Ci/o-GND Ci/o-i/o ΔCi/o-i/o 10 5 V 150 nA 6 V Clamping voltage Capacitance between I/O and GND VR = 1.65 V ΔCi/o-GND 2/14 Typ. 2.5 3.5 pF 0.015 Capacitance between I/O VR = 1.65 V 1.2 1.7 pF 0.04 USBLC6-2 Figure 2. Characteristics Capacitance versus voltage (typical values) Figure 3. Line capacitance versus frequency (typical values) C(pF) C(pF) 2.8 3.0 2.6 CO=I/O-GND 2.4 2.5 VOSC=30mVRMS Tj=25°C VLINE=0V to 3.3V 2.2 2.0 F=1MHz VOSC=30mVRMS Tj=25°C 2.0 1.8 1.6 1.4 1.5 Cj=I/O-I/O 1.2 1.0 1.0 0.8 0.6 0.5 0.4 Data line voltage (V) 0.2 0.0 F(MHz) 0.0 0.0 0.5 Figure 4. 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Relative variation of leakage current versus junction temperature (typical values) 1 Figure 5. IRM[Tj] / IRM[Tj=25°C] 10 100 1000 Frequency response 0.00 100 S21(dB) VBUS=5V -5.00 -10.00 10 -15.00 F(Hz) Tj(°C) -20.00 1 25 50 75 100 125 100.0k 1.0M 10.0M 100.0M 1.0G 3/14 Technical information 2 Technical information 2.1 Surge protection USBLC6-2 The USBLC6-2 is particularly optimized to perform surge protection based on the rail to rail topology. The clamping voltage VCL can be calculated as follow : VCL+ = VTRANSIL + VF for positive surges VCL- = - VF for negative surges with: VF = VT + Rd.Ip (VF forward drop voltage) / (VT forward drop threshold voltage) and VTRANSIL = VBR + Rd_TRANSIL.IP Calculation example We assume that the value of the dynamic resistance of the clamping diode is typically: Rd = 0.5 Ω and VT = 1.1 V We assume that the value of the dynamic resistance of the transil diode is typically: Rd_TRANSIL = 0.5 Ω and VBR = 6.1 V For an IEC 61000-4-2 surge Level 4 (Contact Discharge: Vg = 8 kV, Rg = 330 Ω), VBUS = +5 V, and if in first approximation, we assume that : Ip = Vg / Rg = 24 A. So, we find: VCL+ = +31.2 V VCL- = -13 V Note: The calculations do not take into account phenomena due to parasitic inductances. 2.2 Surge protection application example If we consider that the connections from the pin VBUS to VCC, from I/O to data line and from GND to PCB GND plane are done by tracks of 10 mm long and 0.5 mm large, we assume that the parasitic inductances LVBUS, LI/O and LGND of these tracks are about 6 nH. So when an IEC 61000-4-2 surge occurs on data line, due to the rise time of this spike (tr=1ns), the voltage VCL has an extra value equal to LI/O.dl/dt+LGND.dI/dt. The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns The overvoltage due to the parasitic inductances is: LI/O.dl/dt = LGND.dI/dt = 6 nH x 24 A/ns = 144 V By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be : VCL+ = +31.2 + 144 + 144 = 319.2 V VCL- = -13.1 - 144 - 144 = -301.1 V 4/14 USBLC6-2 Technical information We can significantly reduce this phenomena with simple layout optimization. It is for this reason that some recommendations have to be followed (see 2.3: How to ensure good ESD protection). Figure 6. ESD behavior: parasitic phenomena due to unsuitable layout ESD surge on data line VCL+ VBUS Data line LI/O di dt LI/O LI/O di + LGND di dt dt LVBUS Positive Surge VCC pin VF VTRANSIL I/O pin VTRANSIL + VF VCL t tr = 1 ns GND pin tr = 1 ns LGND LGND di dt t - VF VCL+ = VTRANSIL + VF + LI/O di + LGND di dt dt surge > 0 VCL- = -VF - LI/O di - LGND di dt dt surge > 0 Negative Surge -LI/O di - LGND di dt dt V TRANSIL = VBR + Rd.Ip VCL- 2.3 How to ensure good ESD protection While the USBLC6-2 provides high immunity to ESD surge, efficient protection depends on the layout of the board. In the same way, with the rail to rail topology, the track from data lines to I/O pins, from VCC to VBUS pin and from GND plane to GND pin must be as short as possible to avoid overvoltages due to parasitic phenomena (see Figure 6. and Figure 7. for layout consideration) Figure 7. ESD behavior: layout optimization 1 1 Figure 8. ESD behavior: measurement conditions 6 ESD SURGE 2 5 3 4 USBLC6-2SC6 Unsuitable layout TEST BOARD IN OUT +5 V 1 1 6 2 5 3 4 Optimized layout 5/14 Technical information Figure 9. USBLC6-2 ESD response to IEC 61000-4-2 (+15 kV air discharge) Figure 10. ESD response to IEC 61000-4-2 (-15 kV air discharge) Vin Vin Vout Vout Important: A good precaution to take is to put the protection device as close as possible to the disturbance source (generally the connector). 2.4 Crosstalk behavior 2.4.1 Crosstalk phenomenon Figure 11. Crosstalk phenomenon RG1 Line 1 VG1 RL1 RG2 VG2 Line 2 RL2 DRIVERS α 1 VG1 + β12VG2 α 2VG2 + β21VG1 RECEIVERS The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor (β12 or β21) increases when the gap across lines decreases, particularly in silicon dice. In the above example the expected signal on load RL2 is α2VG2, in fact the real voltage at this point has got an extra value β21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few kΩ). 6/14 USBLC6-2 Technical information Figure 12. Analog crosstalk measurements TEST BOARD USBLC6-2SC6 NETWORK ANALYSER PORT 2 NETWORK ANALYSER PORT 1 Vbus Figure 12. shows the measurement circuit for the analog application. In usual frequency range of analog signals (up to 240 MHz) the effect on disturbed line is less than -55 db ( see Figure 13.). Figure 13. Analog crosstalk results dB 0.00 - 30.00 - 60.00 - 90.00 F (Hz) - 120.00 100.0k 1.0M 10.0M 100.0M 1.0G As the USBLC6-2 is designed to protect high speed data lines, it must ensure a good transmission of operating signals. The frequency response (Figure 5.) gives attenuation information and shows that the USBLC6-2 is well suitable for data line transmission up to 480 Mbit/s while it works as a filter for undesirable signals like GSM (900 MHz) frequencies, for instance. 7/14 Technical information 2.5 USBLC6-2 Application examples Figure 14. USB 2.0 port application diagram using USBLC6-2 + 3.3V DEVICEUPSTREAM RPU TRANSCEIVER SW2 + 5V USB connector SW1 VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS GND TX LS/FS + TX LS/FS - Protecting Bus Switch VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS - VBUS D+ DGND RS RS RS USBLC6-2SC6 RS RPD + 3.3V DEVICEUPSTREAM RPU TRANSCEIVER SW2 GND TX LS/FS - TX LS/FS - RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS - D+ DGND RS RS USBLC6-2P6 Mode SW1 SW2 Low Speed LS Open Closed Full Speed FS Closed Open High Speed HS Closed then open Open RS RPD +VCC 100nF USBLC6-2SC6 Figure 15. T1/E1/Ethernet protection Tx SMP75-8 DATA +VCC 100nF SMP75-8 USBLC6-2SC6 TRANSCEIVER Rx GND TX LS/FS + USBLC6-4SC6 RPD 8/14 TX LS/FS + RPD VBUS RS GND USB connector SW1 VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS - TX LS/FS + HUBDOWNSTREAM TRANSCEIVER TX LS/FS - USBLC6-2 2.6 Technical information PSpice model Figure 16. shows the PSpice model of one USBLC6-2 cell. In this model, the diodes are defined by the PSpice parameters given in Figure 17. Figure 16. PSpice model LI/O RI/O RI/O LI/O D+out D+in MODEL = Dlow LGND RGND MODEL = Dhigh RI/O MODEL = Dzener LI/O GND VBUS MODEL = Dlow LI/O MODEL = Dhigh RI/O RI/O LI/O D-in D-out Note: This simulation model is available only for an ambient temperature of 27 °C. Figure 17. PSpice parameters Dlow Dhigh Figure 18. USBLC6-2 PCB layout considerations Dzener LI/O 750p RI/O 110m BV 50 50 7.3 CJ0 0.9p 2.0p 40p LGND 550p IBV 1m 1m 1m RGND 60m M 0.3333 0.3333 0.3333 RS 0.2 0.52 0.84 VJ 0.6 0.6 0.6 TT 0.1u 0.1u 0.1u D+in D+out 1 VBUS GND CBUS = 100nF D-in USBLC6-2 D-out 9/14 Ordering information scheme 3 USBLC6-2 Ordering information scheme Figure 19. Ordering information scheme USB Product Designation Low capacitance Breakdown Voltage 6 = 6 Volts Number of lines protected 2 = 2 lines Packages SC6 = SOT23-6L P6 = SOT-666 10/14 LC 6 - 2 xxx USBLC6-2 4 Package information Package information ● Epoxy meets UL94, V0 In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Table 3. SOT-666 dimensions Dimensions b1 L1 Ref. Millimeters Min. L3 b D E1 A L2 E A3 Min. Typ. Max. 0.45 0.60 0.018 0.024 A3 0.08 0.18 0.003 0.007 b 0.17 0.34 0.007 0.013 b1 0.19 D 1.50 1.70 0.059 0.067 E 1.50 1.70 0.059 0.067 E1 1.10 1.30 0.043 0.051 0.27 0.34 0.007 0.011 0.013 e 0.50 0.020 L1 0.19 0.007 L3 Figure 20. SOT-666 footprint Max. A L2 e Typ. Inches 0.10 0.30 0.004 0.10 0.012 0.004 Figure 21. SOT-666 marking 0.50 e3 0.62 2.60 x x x z y ww e3: ECOPACK (Leadfree) XXX: Marking Z: Manufacturing location Y: Year WW: week 0.99 0.30 11/14 Package information USBLC6-2 Table 4. SOT23-6L dimensions Dimensions Ref. A Min. E e b D e A2 θ Typ. Max. Inches Min. Typ. Max. A 0.90 A1 0 A2 0.90 1.30 0.035 0.051 b 0.35 0.50 0.014 0.020 c 0.09 0.20 0.004 0.008 D 2.80 3.05 0.11 0.118 E 1.50 1.75 0.059 0.069 e A1 c Millimeters 1.45 0.035 0.057 0.10 0.004 0 0.95 0.037 L H Figure 22. SOT23-6L footprint H 2.60 3.00 0.102 0.118 L 0.10 0.60 0.004 0.024 θ 0° 10° 0° 10° Figure 23. SOT23-6L marking 0.60 1.20 e3 3.50 12/14 2.30 0.95 1.10 x x x z y ww e3: ECOPACK (Leadfree) XXX: Marking Z: Manufacturing location Y: Year WW: week USBLC6-2 5 Ordering information Ordering information Table 5. 6 Ordering information Ordering code Marking Package Weight Base qty Delivery mode USBLC6-2SC6 UL26 SOT23-6L 16.7 mg 3000 Tape and reel USBLC6-2P6 F SOT-666 2.9 mg 3000 Tape and reel Revision history Table 6. Document revision history Date Revision 14-Mar-2005 1 First issue. 07-Jun-2005 2 Format change to figure 3; no content changed. 3 Added marking illustrations - Figures 21 and 23. Added ECOPACK statement. Updated operating junction temperature range in absolute ratings, page 2. Technical information section updated. Reformatted to current standards. 20-Mar-2008 Description of changes 13/14 USBLC6-2 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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