Standard Products
QCOTSTM UT8Q1024K8 SRAM
Data Sheet
January, 2003
FEATURES
25ns maximum (3.3 volt supply) address access time
Dual cavity package contains two (2) 512K x 8 industrystandard asynchronous SRAMs; the control architecture
allows operation as an 8-bit data width
TTL compatible inputs and output levels, three-state
bidirectional data bus
Typical radiation performance
- Total dose: 50krad(Si)
INTRODUCTION
The QCOTSTM UT8Q1024K8 Quantified Commercial Off-theShelf product is a high-performance 1M byte (8Mbit) CMOS
static RAM built with two individual 524,288 x 8 bit SRAMs
with a common output enable. Memory access and control is
provided by an active LOW chip enable (En), an active LOW
output enable (G). This device has a power-down feature that
reduces power consumption by more than 90% when deselected.
- SEL Immune >80 MeV-cm2/mg
- LETTH(0.25) = >10 MeV-cm2/mg
- Saturated Cross Section cm2 per bit, 5.0E-9
- <1E-8 errors/bit-day, Adams 90% geosynchronous
heavy ion
Writing to each memory is accomplished by taking one of the
chip enable (En) inputs LOW and write enable (Wn) inputs
LOW. Data on the I/O pins is then written into the location
specified on the address pins (A0 through A18). Reading from
the device is accomplished by taking one of the chip enable (En)
and output enable (G) LOW while forcing write enable (Wn)
HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
Only one SRAM can be read or written at a time.
Packaging options:
- 44-lead bottom brazed dual CFP (BBTFP) (4.6 grams)
Standard Microcircuit Drawing 5962-01532
- QML T and Q compliant part
The input/output pins are placed in a high impedance state when
the device is deselected (En HIGH), the outputs are disabled (G
HIGH), or during a write operation (En LOW and Wn LOW).
W1
E1
E0
A(18:0)
G
512K x 8
512K x 8
DQ(7:0)
Figure 1. UT8Q1024K8 SRAM Block Diagram
1
W0
DEVICE OPERATION
NC
NC
A0
A1
A2
A3
A4
E1
DQ0
DQ1
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VS S
DQ2
DQ3
W1
A5
A6
A7
A8
A9
W2
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Each die in the UT8Q1024K8 has three control inputs called
Enable (En), Write Enable (Wn), and Output Enable (G); 19
address inputs, A(18:0); and eight bidirectional data lines,
DQ(7:0). The device enable (En) controls device selection,
active, and standby modes. Asserting En enables the device,
causes IDD to rise to its active value, and decodes the 19 address
inputs to each memory die . Wn controls read and write
operations. During a read cycle, G must be asserted to enable
the outputs.
NC
E2
NC
A18
A17
A16
A15
G
DQ7
DQ6
VSS
VDD
DQ5
DQ4
A14
A13
A12
A11
A10
NC
NC
NC
Table 1. Device Operation Truth Table
Figure 2. 25ns SRAM Pinout (44)
Address
DQ(7:0)
Data Input/Output
En
Device Enable
Wn
WriteEnable
G
Output Enable
VDD
Power
V SS
Ground
Wn
En
I/O Mode
Mode
X1
X
1
3-state
Standby
X
0
0
Data in
Write
1
1
0
3-state
Read2
0
1
0
Data out
Read
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
PIN NAMES
A(18:0)
G
READ CYCLE
A combination of Wn greater than V IH (min) with En and G less
than V IL (max) defines a read cycle. Read access time is
measured from the latter of device enable, output enable, or valid
address to valid data output.
SRAM Read Cycle 1, the Address Access is initiated by a change
in address inputs while the chip is enabled with G asserted and
Wn deasserted. Valid data appears on data outputs DQ(7:0) after
the specified t AVQV is satisfied. Outputs remain active
throughout the entire cycle. As long as device enable and output
enable are active, the address inputs may change at a rate equal
to the minimum read cycle time (tAVAV).
Notes:
1. To avoid bus contention, on the DQ(7:0) bus, only one En can be driven low
simultaneously while G is low.
SRAM Read Cycle 2, the Chip Enable-controlled Access is
initiated by En going active while G remains asserted, Wn
remains deasserted, and the addresses remain stable for the
entire cycle. After the specified t ETQV is satisfied, the eight-bit
word addressed by A(18:0) is accessed and appears at the data
outputs DQ(7:0).
SRAM Read Cycle 3, the Output Enable-controlled Access is
initiated by G going active while En is asserted, Wn is
deasserted, and the addresses are stable. Read access time is
tGLQV unless tAVQV or tETQV have not been satisfied.
2
WRITE CYCLE
TYPICAL RADIATION HARDNESS
The UT8Q1024K8 SRAM incorporates features which allow
operation in a limited radiation environment.
A combination of Wn less than VIL(max) and En less than
VIL(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when eitherG is greater than V IH(min), or when Wn is less
than VIL (max).
Table 2. Typical Radiation Hardness
Design Specifications 1
Write Cycle 1, the Write Enable-controlled Access is defined
by a write terminated by Wn going high, with En still active.
The write pulse width is defined by tWLWH when the write is
initiated byWn, and by t ETWH when the write is initiated by En.
Unless the outputs have been previously placed in the highimpedance state byG, the user must wait t WLQZ before applying
data to the eight bidirectional pins DQ(7:0) to avoid bus
contention.
Total Dose
50
krad(Si) nominal
Heavy Ion
Error Rate 2
<1E-8
Errors/Bit-Day
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
Write Cycle 2, the Chip Enable-controlled Access is defined by
a write terminated by the former of En or Wn going inactive.
The write pulse width is defined by tWLEF when the write is
initiated by Wn, and by t ETEF when the write is initiated by the
En going active. For the Wn initiated write, unless the outputs
have been previously placed in the high-impedance state by G,
the user must wait tWLQZ before applying data to the eight
bidirectional pins DQ(7:0) to avoid bus contention.
3
ABSOLUTE MAXIMUM RATINGS 1
(Referenced to V SS )
SYMBOL
PARAMETER
LIMITS
V DD
DC supply voltage
-0.5 to 4.6V
V I/O
Voltage on any pin
-0.5 to 4.6V
TSTG
Storage temperature
-65 to +150°C
PD
Maximum power dissipation
TJ
Maximum junction temperature2
+150°C
Thermal resistance, junction-to-case3
10°C/W
DC input current
±10 mA
ΘJC
II
1.0W (per byte)
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. E xposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175 °C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
V DD
Positive supply voltage
3.0 to 3.6V
TC
Case temperature range
-40 to +125°C
V IN
DC input voltage
0V to V DD
4
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(-40°C to +125°C) (V DD = 3.3V + 0.3)
SYMBOL
PARAMETER
CONDITION
MIN
MAX
2.0
UNIT
VIH
High-level input voltage
(CMOS)
V
V IL
Low-level input voltage
(CMOS)
0.8
V
VOL1
Low-level output voltage
IOL = 8mA, VDD =3.0V
0.4
V
VOL2
Low-level output voltage
IOL = 200µA,VDD =3.0V
0.08
V
V OH1
High-level output voltage
IOH = -4mA,V DD =3.0V
V OH2
High-level output voltage
IOH = -200µA,V DD =3.0V
CIN 1
Input capacitance
ƒ = 1MHz @ 0V
20
pF
CIO 1
Bidirectional I/O capacitance
ƒ = 1MHz @ 0V
24
pF
I IN
Input leakage current
V SS < V IN < V DD, V DD = V DD (max)
-2
2
µA
IOZ
Three-state output leakage current
0V < V O < VDD
-2
2
µA
-90
90
mA
150
mA
220
mA
4
mA
2.4
V
VDD -0.10
V
V DD = V DD (max)
G = VDD (max)
I OS2, 3
I DD (OP)
Short-circuit output current
0V < V O < VDD
Supply current operating
@ 1MHz
Inputs: V IL = 0.8V,
V IH = 2.0V
IOUT = 0mA
V DD = V DD (max)
IDD1 (OP)
Supply current operating
@40MHz
Inputs: V IL = 0.8V,
V IH = 2.0V
IOUT = 0mA
V DD = V DD (max)
I DD2(SB)
Nominal standby supply current
@0MHz
Inputs: V IL = V SS
-40°C and 25°C
IOUT = 0mA
En = VDD - 0.5,
+125°C
V DD = V DD (max)
V IH = V DD - 0.5V
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 101 9 .
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
5
mA
25
AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)*
(-40°C to +125°C) (V DD = 3.3V + 0.3)
SYMBOL
PARAMETER
MIN
MAX
tAVAV 1
Read cycle time
tAVQV
Read access time
tAXQX 2
Output hold time
3
ns
tGLQX 2
G-controlled Output Enable time
0
ns
tGLQV
G-controlled Output Enable time (Read Cycle 3)
10
ns
tGHQZ 2
G-controlled output three-state time
10
ns
tETQX2,3
En-controlled Output Enable time
tETQV3
tEFQZ1,2,4
25
UNIT
ns
25
3
ns
ns
En-controlled access time
25
ns
En-controlled output three-state time
10
ns
Notes: * Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Functional test.
2. Three-state is defined as a 300mV change from steady-state output voltage.
3. The ET (enable true) notation refers to the falling edge of En. SEU immunity does not affect the read parameters.
4. The EF (enable false) notation refers to the rising edge of En. SEU immunity does not affect the read parameters.
High Z to Active Levels
Active to High Z Levels
VH - 300mV
VLOAD + 300mV
}
VLOAD
{
{
}
VLOAD - 300mV
VL + 300mV
Figure 3. 3-Volt SRAM Loading
6
t AVAV
A(18:0)
DQ(7:0)
Previous Valid Data
Valid Data
t AVQV
tAXQX
Assumptions:
1 . En andG < V IL (max) and Wn > V IH (min)
Figure 4a. SRAM Read Cycle 1: Address Access
A(18:0)
En
tETQV
DQ(7:0)
t EFQZ
t ETQX
DATA VALID
Assumptions:
1. G < V IL (max) and Wn > VIH (min)
Figure 4b. SRAM Read Cycle 2: Chip Enable-Controlled Access
tAVQV
A(18:0)
G
t GHQZ
t GLQX
DATA VALID
DQ(7:0)
Assumptions:
1 . En < V IL (max) andWn > V IH (min)
tGLQV
Figure 4c. SRAM Read Cycle 3: Output Enable-Controlled Access
7
AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)*
(-40°C to +125°C) (V DD = 3.3V + 0.3)
SYMBOL
PARAMETER
MIN
MAX
UNIT
tAVAV 1
Write cycle time
25
ns
tETWH
Device Enable to end of write
20
ns
tAVET
Address setup time for write (En - controlled)
0
ns
tAVWL
Address setup time for write (Wn - controlled)
0
ns
tWLWH
Write pulse width
20
ns
tWHAX
Address hold time for write (Wn - controlled)
2
ns
tEFAX
Address hold time for Device Enable (En - controlled)
2
ns
tWLQZ 2
Wn- controlled three-state time
tWHQX 2
Wn - controlled Output Enable time
10
ns
5
ns
Device Enable pulse width (En - controlled)
20
ns
tDVWH
Data setup time
15
ns
tWHDX 2
Data hold time
2
ns
tETEF
tWLEF
Device Enable controlled write pulse width
20
ns
tDVEF 2
Data setup time
15
ns
tEFDX
Data hold time
2
ns
tAVWH
Address valid to end of write
20
ns
tWHWL1
Write disable time
5
ns
Notes :
* Post-radiation performance guaranteed at 25 °C per MIL-STD-883 Method 1019.
1. Functional test performed with outputs disabled (G high).
2. Three-state is defined as 300mV change from steady-state output voltage.
8
A(18:0)
tAVAV 2
En
tAVWH
tETWH
tWHWL
Wn
t AVWL
tWLWH
tWHAX
Q(7:0)
t WLQZ
D(7:0)
t WHQX
APPLIED DATA
Assumptions:
1. G < VIL (max). If G > VIH (min) then Qn(8:0) will be
in three-state for the entire cycle.
2. G high for t AVAV cycle.
t DVWH
t WHDX
Figure 5a . SRAM Write Cycle 1: Write Enable - Controlled Access
t AVAV 3
A(18:0)
t ETEF
tAVET
tEFAX
En
or
tAVET
En
Wn
t ETEF
t EFAX
tWLEF
D(7:0)
APPLIED DATA
tWLQZ
tDVEF
Q(7:0)
tEFDX
Assumptions & Notes:
1. G < V IL (max). If G > V IH (min) then Q(7:0) will be in three-state for the entire cycle.
2. Either En scenario above can occur.
3. G high for t AVAV cycle.
Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access
9
DATA RETENTION MODE
VDD
50%
50%
VDR > 2.0V
tR
t EFR
En
Figure 7. Low VDD Data Retention Waveform
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation)
(1 Second Data Retention Test)
SYMBOL
PARAMETER
V DR
IDDR
1,2
tEFR1,3
tR1,3
MINIMUM
MAXIMUM
UNIT
2.0
--
V
Data retention current (per byte)
--
4.0
mA
Chip select to data retention time
0
ns
tAVAV
ns
V DD for data retention
Operation recovery time
Notes:
1. En = VDD - .2V, all other inputs = VDR or V SS.
2. Data retention current (I DDR ) Tc = 25 oC.
3. Not guaranteed or tested.
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation)
(10 Second Data Retention Test, TC=-40oC to +125o C)
SYMBOL
V DD 1
tEFR 2, 3
tR2, 3
PARAMETER
V DD for data retention
Chip select to data retention time
Operation recovery time
Notes:
1. Performed at VD D (min) and V D D (max).
2. En = VSS , all other inputs = VDR or V SS .
3. Not guaranteed or tested.
10
MINIMUM
MAXIMUM
UNIT
3.0
3.6
V
0
ns
tAVAV
ns
11
PACKAGING
1. All exposed metalized areas must be plated per MIL-PRF-38535.
2. The lid is electrically connected to V SS .
3. Index mark configuration is optional.
4. Total weight is approx. 4.6 g.
Figure 9. 44-lead bottom brazed dual CFP (BBTFP) package
12
ORDERING INFORMATION
1024K8 SRAM:
UT8Q1024K8 - * *
*
*
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)
Screening:
(P) = Prototype flow
(W) = Extended Industrial Temperature Range Flow (-40o C to +125o C)
Package Type:
(U) = 44-lead bottom brazed dual CFP (BBTFP)
Device Type:
- = 25ns access, 3.3V operation
Aeroflex UTMC Core Part Number
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (g old).
3. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25 ° C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed.
4. Extended Industrial Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -40°C to +125°C. Radiation neither
tested nor guaranteed.
13
1024K8 SRAM: SMD
5962 - 01532
** * * *
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)
Case Outline:
(Y) = 44-lead dual cavity CFP
Class Designator:
(T) = QML Class T
(Q) = QML Class Q
Device Type
01 = 25ns access time, 3.3V operation, Extended Industrial Temp (-40oC to +125 oC)
Drawing Number: 01532
Total Dose
(-) = None
(D) = 1E4 (10krad(Si))
(P) = 3E4 (30krad(Si)) (contact factory)
(L) = 5E4 (50krad(Si)) (contact factory)
Federal Stock Class Designator: No Options
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold).
3. Total dose radiation must be specified when ordering.
14
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