PRELIMINARY DATA SHEET MICRONAS Edition Sept. 25, 1998 6251-437-2PD VDP 31xxB Video Processor Family MICRONAS VDP 31xxB PRELIMINARY DATA SHEET Contents Page Section Title 5 6 1. 1.1. Introduction VDP Applications 7 7 7 7 7 7 7 7 7 9 10 10 11 11 11 11 11 11 12 12 13 13 13 14 15 15 15 16 17 17 17 17 18 18 18 18 19 19 19 19 2. 2.1. 2.1.1. 2.1.2. 2.1.3. 2.1.4. 2.1.5. 2.1.6. 2.1.7. 2.2. 2.3. 2.3.1. 2.3.2. 2.3.3. 2.3.4. 2.3.5. 2.3.6. 2.3.7. 2.3.8. 2.3.9. 2.4. 2.5. 2.6. 2.7. 2.8. 2.8.1. 2.8.2. 2.8.3. 2.8.4. 2.8.5. 2.8.6. 2.8.7. 2.8.8. 2.8.9. 2.8.10. 2.8.11. 2.8.12. 2.8.13. 2.8.14. 2.8.15. Functional Description Analog Front-End Input Selector Clamping Automatic Gain Control Analog-to-Digital Converters ADC Range Digitally Controlled Clock Oscillator Analog Video Output Adaptive Comb Filter Color Decoder IF-Compensation Demodulator Chrominance Filter Frequency Demodulator Burst Detection Color Killer Operation PAL Compensation /1-H Comb Filter Luminance Notch Filter Skew Filtering Horizontal Scaler Black-Line Detector Test Pattern Generator Video Sync Processing Display Part Luma Contrast Adjustment Black Level Expander Dynamic Peaking Digital Brightness Adjustment Soft Limiter Chroma Input Chroma Interpolation Chroma Transient Improvement Inverse Matrix RGB Processing OSD Color Lookup Table Picture Frame Generator Priority Codec Scan Velocity Modulation Display Phase Shifter 2 Micronas PRELIMINARY DATA SHEET VDP 31xxB Contents, continued Page Section Title 21 21 22 23 23 24 24 24 26 26 26 28 28 29 29 2.9. 2.9.1. 2.9.2. 2.9.3. 2.9.4. 2.9.5. 2.9.6. 2.10. 2.11. 2.11.1. 2.11.2. 2.11.3. 2.11.4. 2.12. 2.13. Analog Back End CRT Measurement and Control SCART Output Signal Average Beam Current Limiter Analog RGB Insertion Fast Blank Monitor Half Contrast Control IO Port Expander Synchronization and Deflection Deflection Processing Horizontal Phase Adjustment Vertical and East/West Deflection Protection Circuitry Reset Function Standby and Power-On 30 30 30 43 46 3. 3.1. 3.2. 3.2.1. 3.2.2. Serial Interface I2C-Bus Interface Control and Status Registers Scaler Adjustment Calculation of Vertical and East-West Deflection Coefficients 47 47 47 49 51 52 54 54 54 54 55 56 56 56 57 57 57 58 59 60 60 60 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.3. 4.6.4. 4.6.4.1. 4.6.4.2. 4.6.4.3. 4.6.4.4. 4.6.4.5. 4.6.4.6. 4.6.4.7. 4.6.4.8. 4.6.4.9. 4.6.4.10. 4.6.4.11. Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Pin Configuration Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Recommended Crystal Characteristics Characteristics 5 MHz Clock Output 20 MHz Clock Input/Output, External Clock Input (XTAL1) Reset Input, Test Input I2C-Bus Interface IO Port Expander Analog Video Inputs Analog Front-End and ADCs Picture Bus Input INTLC, Front Sync Output Main Sync Output Combined Sync Output Micronas 3 VDP 31xxB PRELIMINARY DATA SHEET Contents, continued Page Section Title 61 61 61 61 62 62 62 63 64 66 66 4.6.4.12. 4.6.4.13. 4.6.4.14. 4.6.4.15. 4.6.4.16. 4.6.4.17. 4.6.4.18. 4.6.4.19. 4.6.4.20. 4.6.4.21. 4.6.4.22. Horizontal Flyback Input Horizontal Drive Output Vertical Protection Input Vertical Safety Input Vertical and East/West Drive Output Sense A/D Converter Input Analog RGB and FB Inputs Half Contrast Switch Input Analog RGB Outputs, D/A Converters DAC Reference, Beam Current Safety Scan Velocity Modulation Output 67 5. Application Circuit 72 6. Data Sheet History 4 Micronas VDP 31xxB PRELIMINARY DATA SHEET VPC 3200A Video Processor and DDP 3300A Display and Deflection Processor. Video, Display, and Deflection Processor Release Notes: This data sheet describes functions and characteristics of the VDP 31xxB–C2. Revision bars indicate significant changes to the previous edition. Each member of the family contains the entire video, display, and deflection processing for 4:3 and 16:9 50/60 TV sets. Its performance and flexibility allow the user to standardize his product development. Hardware and software applications can profit from the modularity, as well as manufacturing, systems support, or maintenance. An overview of the VDP 31xxB video processor family is shown in Fig. 1–1. 1. Introduction VDP 3116B n VDP 3120B n n n n n n n n n n n n n n n n n n n n n n n n n n n n Tube Control n RGB Insertion VDP 3112B Prog. RGB Matrix n Scan Vel. Mod. VDP 3108B Color Trans. Impr. n Horizontal Scaler VDP 3104B 2H adapt. Comb VDP 31xxB Family 1H Combfilter The VDP 31xxB is a Video IC family of high-quality single-chip video processors. Modular design and a submicron technology allow the economic integration of features in all classes of TV sets. The VDP 31xxB family is based on functional blocks contained in the two chips: Fig. 1–1: VDP 31xxB family overview VRT Color Bus XREF CIN VIN1 VIN2 VIN3 VIN4 RGB/FB IN1 Analog Frontend 2H Adaptive Combfilter AGC, 2*8bit ADC Color Decoder Horizontal Scaler Display Processor NTSC, PAL, SECAM Panorama Mode RGB Matrix, CLUT, Scan Veloc. VOUT Analog Backend 3*10bit DAC, Tube Control, RGB Switch RGB/FB IN2 Half Contrast RGB OUT SVM 20.25 MHz Clock Gen. DCO I2C Sync & Deflection I2C H/V/EW Measurement ADC Sense Fig. 1–2: Block diagram of the VDP 3120B Micronas 5 VDP 31xxB PRELIMINARY DATA SHEET 1.1. VDP Applications RGB Processing As a member of the VDP 31xxB family, the VDP 3120B offers all video features necessary to design a state-ofthe-art TV set: – programmable RGB matrix – digital color bus interface – additional analog RGB / fast blank input Video Decoding – half-contrast switch – 4 composite inputs, 1 S-VHS input – picture frame generator – composite video & sync output – integrated high-quality A/D converters Deflection – adaptive 2H comb filter Y/C separator – scan velocity modulation output – 1H NTSC comb filter – high-performance H/V deflection – multistandard color decoder (1 crystal) – separate ADC for tube measurements – multistandard sync decoder – EHT compensation – black line detector Miscellaneous Video Processing – one 20.25 MHz crystal, few external components – horizontal scaling (0.25 to 4) – embedded RISC controller (80 MIPS) – panorama vision – I2C-Bus Interface – black level expander – dynamic peaking – single 5 V power supply – soft limiter (gamma correction) – submicron CMOS technology – color transient improvement – 64-pin PSDIP package Video 1 Video 2 TPU 3040 DRAM CCU 300x VDP 3120B RGB H/VDefl. MSP 3410 3 x Stereo DPL 3420 Dolby Surround RGB 1 RGB 2 Audio Fig. 1–3: Full-feature TV set with VDP 3120B 6 Micronas VDP 31xxB PRELIMINARY DATA SHEET 2.1.3. Automatic Gain Control 2. Functional Description 2.1. Analog Front-End This block provides the analog interfaces to all video inputs and mainly carries out analog-to digital conversion for the following digital video processing. A block diagram is given in Fig. 2–1. A digitally working automatic gain control adjusts the magnitude of the selected baseband by +6/–4.5 dB in 64 logarithmic steps to the optimal range of the ADC. The gain of the video input stage including the ADC is 213 steps/V with the AGC set to 0 dB. 2.1.4. Analog-to-Digital Converters Most of the functional blocks in the front-end are digitally controlled (clamping, AGC, and clock-DCO). The control loops are closed by the Fast Processor (‘FP’) embedded in the decoder. 2.1.1. Input Selector 2.1.5. ADC Range Up to five analog inputs can be connected. Four inputs are for input of composite video or S-VHS luma signal. These inputs are clamped to the sync back porch and are amplified by a variable gain amplifier. One input is for connection of S-VHS carrier-chrominance signal. This input is internally biased and has a fixed gain amplifier. 2.1.2. Clamping The composite video input signals are AC coupled to the IC. The clamping voltage is stored on the coupling capacitors and is generated by digitally controlled current sources. The clamping level is the back porch of the video signal. S-VHS chroma is also AC coupled. The input pin is internally biased to the center of the ADC input range. Analog Video Output 3 CVBS/Y VIN4 CVBS/Y VIN2 CVBS/Y/C VIN1 Chroma CIN The ADC input range for the various input signals and the digital representation is given in Table 2–1 and Fig. 2–2. The corresponding output signal levels of the VDP 31xxB are also shown. 2.1.6. Digitally Controlled Clock Oscillator The clock generation is also a part of the analog front end. The crystal oscillator is controlled digitally by the control processor; the clock frequency can be adjusted within ±150 ppm. 2.1.7. Analog Video Output The input signal of the Luma ADC is available at the analog video output pin. The signal at this pin must be buffered by a source follower. The output voltage is 2 V, thus the signal can be used to drive a 75 W line. The magnitude is adjusted with an AGC in 8 steps together with the main AGC. AGC +6/–4.5 dB clamp VIN3 ADC digital CVBS or Luma ADC digital Chroma gain input mux CVBS/Y Two ADCs are provided to digitize the input signals. Each converter runs with 20.25 MHz and has 8 bit resolution. An integrated bandgap circuit generates the required reference voltages for the converters. bias system clocks reference generation frequency DVCO ±150 ppm 20.25 MHz Fig. 2–1: Analog front-end Micronas 7 VDP 31xxB PRELIMINARY DATA SHEET Table 2–1: ADC input range for PAL input signal and corresponding signal ranges Signal CVBS Input Level [mVpp] –6 dB 0 dB 100% CVBS 667 1333 75% CVBS 500 video (luma) sync height ADC Range +4.5 dB [steps] [steps] 2238 252 – 1000 1679 213 – 350 700 1175 149 224 150 300 504 64 – 68 16 clamp level Chroma burst 300 64 – 100% Chroma 890 190 128±112 75% Chroma 670 143 128±84 128 128 bias level CVBS/Y 255 217 upper headroom = 38 steps = 1.4 dB = 25 IRE 228 32 0 black = clamp level burst 68 128 75% Chroma 192 video = 100 IRE 128 ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ headroom = 56 steps = 2.1 dB 100% Chroma ÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍ Chroma white 192 YCrCb Internal Range 80 sync = 41 IRE ÍÍÍÍÍÍÍÍÍ lower headroom = 4 steps = 0.2 dB 32 ÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍ Fig. 2–2: ADC ranges for CVBS/Luma and Chroma, PAL input signal 8 Micronas VDP 31xxB PRELIMINARY DATA SHEET The adaptive comb filter is used for high-quality luminance/chrominance separation for PAL or NTSC signals. The comb filter improves the luminance resolution (bandwidth) and reduces interferences like cross-luminance and cross-color artifacts. The adaptive algorithm can eliminate most of the mentioned errors without introducing new artifacts or noise. A block diagram of the comb filter is shown in Fig. 2–3. The filter uses two line delays to process the information of three adjacent video lines. To have a fixed phase relationship of the color subcarrier in the three channels, the system clock (20.25 MHz) is fractionally locked to the color subcarrier. This allows the processing of all color standards and substandards using a single crystal frequency. The CVBS signal in the three channels is filtered at the subcarrier frequency by a set of bandpass / notch filters. The output of the three channels is used by the adaption logic to select the weighting that is used to reconstruct the luminance/chrominance signal from the 4 bandpass/ notch filter signals. By using soft mixing of the 4 signals switching artifacts of the adaption algorithm are completely suppressed. The comb filter uses the middle line as reference, therefore, the comb filter delay is one line. If the comb filter is switched off, the delay lines are used to pass the luma/ chroma signals from the A/D converters to the luma/ chroma outputs. Thus, the comb filter delay is always one line. Various parameters of the comb filter are adjustable, hence giving to the user the ability to adjust his own desired picture quality. Bandpass Filter CVBS Input 1 H Line Delay 1 H Line Delay Bandpass/ Notch Filter Bandpass Filter Two parameters (KY, KC) set the global gain of luma and chroma comb separately; these values directly weigh the adaption algorithm output. In this way, it is possible to obtain a luma/chroma separation ranging from standard notch/bandpass to full comb decoding. The parameter KB allows to choose between the two proposed comb booster modes. This so-called feature widely improves vertical high to low frequency transitions areas, the typical example being a multiburst to dc change. For KB=0, this improvement is kept moderate, whereas, in case of KB=1, it is maximum, but the risk to increase the “hanging dots” amount for some given color transitions is higher. Using the default setting, the comb filter has separate luma and chroma decision algorithms; it is however possible to switch the chroma comb factor to the current luma adaption output by setting CC to 1. Another interesting feature is the programmable limitation of the luma comb amount; proper limitation, associated to adequate luma peaking, gives rise to an enhanced 2-D resolution homogeneity. This limitation is set by the parameter CLIM, ranging from 0 (no limitation) to 31 (max. limitation). The DAA parameter (1:off , 0:on) is used to disable/enable a very efficient built-in “rain effect” suppressor; many comb filters show this side effect which gives some vertical correlation to a 2-D uniform random area, due to the vertical filtering. This unnatural-looking phenomenon is mostly visible on tuner images, since they are always corrupted by some noise; and this looks like rain. Luma / Chroma Mixers Adaption Logic 2.2. Adaptive Comb Filter Luma Output Chroma Output Chroma Input Fig. 2–3: Block diagram of the adaptive comb filter Micronas 9 VDP 31xxB PRELIMINARY DATA SHEET 2.3. Color Decoder 2.3.1. IF-Compensation In this block, the standard luma/chroma separation and multi-standard color demodulation is carried out. The color demodulation uses an asynchronous clock, thus allowing a unified architecture for all color standards. With off-air or mistuned reception, any attenuation at higher frequencies or asymmetry around the color subcarrier is compensated. Four different settings of the IFcompensation are possible: – flat (no compensation) A block diagram of the color decoder is shown in Fig. 2–5. The luma as well as the chroma processing, is shown here. The color decoder provides also some special modes, e.g. wide band chroma format which is intended for S-VHS wide bandwidth chroma. – 6 dB /octave – 12 dB /octave – 10 dB/MHz If the adaptive comb filter is used for luma chroma separation, the color decoder uses the S-VHS mode processing. The output of the color decoder is YCrCb in a 4:2:2 format. The last setting gives a very large boost to high frequencies. It is provided for SECAM signals that are decoded using a SAW filter specified originally for the PAL standard. Fig. 2–4: Frequency response of chroma IF-compensation Notch Filter MUX Luma / CVBS 1 H Delay Luma Chroma / CrCb Cross-Switch MUX ACC Chroma IF Compensation DC-Reject MIXER Lowpass Filter Phase/Freq Demodulator Color-PLL / Color-ACC Fig. 2–5: Color decoder 10 Micronas VDP 31xxB PRELIMINARY DATA SHEET 2.3.2. Demodulator 2.3.4. Frequency Demodulator The entire signal (which might still contain luma) is now quadrature-mixed to the baseband. The mixing frequency is equal to the subcarrier for PAL and NTSC, thus achieving the chroma demodulation. For SECAM, the mixing frequency is 4.286 MHz giving the quadrature baseband components of the FM modulated chroma. After the mixer, a lowpass filter selects the chroma components; a downsampling stage converts the color difference signals to a multiplexed half rate data stream. The frequency demodulator for demodulating the SECAM signal is implemented as a CORDIC-structure. It calculates the phase and magnitude of the quadrature components by coordinate rotation. The subcarrier frequency in the demodulator is generated by direct digital synthesis; therefore, substandards such as PAL 3.58 or NTSC 4.43 can also be demodulated. 2.3.3. Chrominance Filter The demodulation is followed by a lowpass filter for the color difference signals for PAL/NTSC. SECAM requires a modified lowpass function with bell-filter characteristic. At the output of the lowpass filter, all luma information is eliminated. The lowpass filters are calculated in time multiplex for the two color signals. Three bandwidth settings (narrow, normal, broad) are available for each standard. For PAL/ NTSC, a wide band chroma filter can be selected. This filter is intended for high bandwidth chroma signals, e.g. a nonstandard wide bandwidth S-VHS signal. The phase output of the CORDIC processor is differentiated to obtain the demodulated frequency. After the deemphasis filter, the Dr and Db signals are scaled to standard CrCb amplitudes and fed to the crossoverswitch. 2.3.5. Burst Detection In the PAL/NTSC-system the burst is the reference for the color signal. The phase and magnitude outputs of the CORDIC are gated with the color key and used for controlling the phase-lock-loop (APC) of the demodulator and the automatic color control (ACC) in PAL/NTSC. The ACC has a control range of +30 ... –6 dB. For SECAM decoding, the frequency of the burst is measured. Thus, the current chroma carrier frequency can be identified and is used to control the SECAM processing. The burst measurements also control the color killer operation; they can be used for automatic standard detection as well. 2.3.6. Color Killer Operation The color killer uses the burst-phase / burst-frequency measurement to identify a PAL/NTSC or SECAM color signal. For PAL/NTSC, the color is switched off (killed) as long as the color subcarrier PLL is not locked. For SECAM, the killer is controlled by the toggle of the burst frequency. The burst amplitude measurement is used to switch-off the color if the burst amplitude is below a programmable threshold. Thus, color will be killed for very noisy signals. The color amplitude killer has a programmable hysteresis. 2.3.7. PAL Compensation / 1-H Comb Filter PAL/NTSC The color decoder uses one fully integrated delay line. Only active video is stored. The delay line application depends on the color standard: – NTSC: 1-H comb filter or color compensation – PAL: color compensation – SECAM: crossover-switch SECAM Fig. 2–6: Frequency response of chroma filters Micronas In the NTSC compensated mode, Fig. 2–7 c), the color signal is averaged for two adjacent lines. Thus, crosscolor distortion and chroma noise is reduced. In the NTSC combfilter mode, Fig. 2–7 d), the delay line is in the composite signal path, thus allowing reduction of 11 VDP 31xxB PRELIMINARY DATA SHEET cross-color components, as well as cross-luminance. The loss of vertical resolution in the luminance channel is compensated by adding the vertical detail signal with removed color information. CVBS Y Notch filter 8 Luma Y 8 Chroma Process. CrC b a) conventional CVBS Chroma 8 Chroma Process. CrC b b) S-VHS If a composite video signal is applied, the color information is suppressed by a programmable notch filter. The position of the filter center frequency depends on the subcarrier frequency for PAL/NTSC. For SECAM, the notch is directly controlled by the chroma carrier frequency. This considerably reduces the cross-luminance. The frequency responses for all three systems are shown in Fig. 2–10. 10 Y Notch filter 8 2.3.8. Luminance Notch Filter dB 0 –10 Chroma Process. CrC b 1H Delay c) compensated CVBS 8 –20 –30 Notch filter Y 1H Delay –40 MHz 0 2 4 6 8 10 6 8 10 PAL/NTSC notch filter CrC b Chroma Process. 10 dB 0 d) comb filter –10 Fig. 2–7: NTSC color decoding options –20 –30 CVBS 8 Y Notch filter –40 MHz 0 2 4 SECAM notch filter Chroma Process. CrC b 1H Delay a) conventional Luma Y 8 Chroma 8 Chroma Process. CrC b 1H Delay b) S-VHS Fig. 2–10: Frequency responses of the luma notch filter for PAL, NTSC, and SECAM 2.3.9. Skew Filtering The system clock is free-running and not locked to the TV line frequency. Therefore, the ADC sampling pattern is not orthogonal. The decoded YCrCb signals are converted to an orthogonal sampling raster by the skew filters, which are part of the scaler block. Fig. 2–8: PAL color decoding options The skew filters allow the application of a group delay to the input signals without introducing waveform or frequency response distortion. CVBS 8 Y Notch filter Chroma Process. 1H Delay Fig. 2–9: SECAM color decoding 12 MUX CrC b The amount of phase shift of this filter is controlled by the horizontal PLL1. The accuracy of the filters is 1/32 clocks for luminance and 1/4 clocks for chroma. Thus the 4:2:2 YCrCb data is in an orthogonal pixel format even in the case of nonstandard input signals such as VCR. Micronas VDP 31xxB PRELIMINARY DATA SHEET 2.4. Horizontal Scaler 2.5. Black-Line Detector The 4:2:2 YCrCb signal from the color decoder is processed by the horizontal scaler. The scaler block allows a linear or nonlinear horizontal scaling of the input video signal in the range of 0.25 to 4. Nonlinear scaling, also called “panorama vision”, provides a geometrical distortion of the input picture. It is used to fit a picture with 4:3 format on a 16:9 screen by stretching the picture geometry at the borders. Also, the inverse effect can be produced by the scaler. A summary of scaler modes is given in Table 2–2. In case of a letterbox format input video, e.g. Cinemascope, PAL+ etc., black areas at the upper and lower part of the picture are visible. It is suitable to remove or reduce these areas by a vertical zoom and/or shift operation. The scaler contains a programmable decimation filter, a 1-line FIFO memory, and a programmable interpolation filter. The scaler input filter is also used for pixel skew correction, see 2.3.9. The decimator/interpolator structure allows optimal use of the FIFO memory. The controlling of the scaler is done by the internal Fast Processor. Table 2–2: Scaler modes Mode Scale Factor Description Compression 4:3 → 16:9 0.75 linear 4:3 source displayed on a 16:9 tube, with side panels Panorama 4:3 → 16:9 nonlinear compr 4:3 source displayed on a 16:9 tube, Borders distorted Zoom 4:3 → 4:3 1.33 linear Letterbox source (PAL+) displayed on a 4:3 tube, vertical overscan with cropping of side panels Panorama 4:3 → 4:3 nonlinear zoom Letterbox source (PAL+) displayed on a 4:3 tube, vertical overscan, borders distorted, no cropping Micronas The VDP 31xxB supports this feature by a letterbox detector. The circuitry detects black video lines by measuring the signal amplitude during active video. For every field the number of black lines at the upper and lower part of the picture are measured, compared to the previous measurement and the minima are stored in the I2C-register BLKLIN. To adjust the picture amplitude, the external controller reads this register, calculates the vertical scaling coefficient and transfers the new settings, e.g. vertical sawtooth parameters, horizontal scaling coefficient etc., to the VDP. Letterbox signals containing logos on the left or right side of the black areas are processed as black lines, while subtitles, inserted in the black areas, are processed as non-black lines. Therefore the subtitles are visible on the screen. To suppress the subtitles, the vertical zoom coefficient is calculated by selecting the larger number of black lines only. Dark video scenes with a low contrast level compared to the letterbox area are indicated by the BLKPIC bit. 2.6. Test Pattern Generator The YCrCb outputs of the front-end can be switched to a test mode where YCrCb data are generated digitally in the VDP 31xxB. Test patterns include luma/chroma ramps, flat fields and a pseudo color bar pattern. 13 VDP 31xxB PRELIMINARY DATA SHEET For vertical sync separation, the sliced video signal is integrated. The FP uses the integrator value to derive vertical sync and field information. 2.7. Video Sync Processing Fig. 2–11 shows a block diagram of the front-end sync processing. To extract the sync information from the video signal, a linear phase lowpass filter eliminates all noise and video contents above 1 MHz. The sync is separated by a slicer; the sync phase is measured. A variable window can be selected to improve the noise immunity of the slicer. The phase comparator measures the falling edge of sync, as well as the integrated sync pulse. The information extracted by the video sync processing is multiplexed onto the hardware front sync signal (FSY) and is distributed to the rest of the video processing system. The format of the front sync signal is given in Fig. 2–12. The data for the vertical deflection, the sawtooth, and the East-West correction signal is calculated by the VDP 31xxB. The data is buffered in a FIFO and transferred to the back-end by a single wire interface. The sync phase error is filtered by a phase-locked loop that is computed by the FP. All timing in the front-end is derived from a counter that is part of this PLL, and it thus counts synchronously to the video signal. Frequency and phase characteristics of the analog video signal are derived from PLL1. The results are fed to the scaler unit for data interpolation and orthogonalization and to the clock synthesizer for line-locked clock generation. Horizontal and vertical syncs are latched with the line-locked clock. A separate hardware block measures the signal back porch and also allows gathering the maximum/minimum of the video signal. This information is processed by the FP and used for gain control and clamping. PLL1 lowpass 1 MHz & syncslicer horizontal sync separation phase comparator & lowpass counter front sync generator front-end timing clock synthesizer syncs front sync skew vblank field video input clock H/V syncs clamp & signal meas. clamping, colorkey, FIFO_write vertical sync separation Sawtooth Parabola Calculation FIFO vertical E/W sawtooth vertical serial data Fig. 2–11: Sync separation block diagram F1 input analog video FSY skew LSB F0 reserved (not in scale) skew not MSB used F V V: vertical sync 0 = off Parity 1 = on F: field # 0 = field 1 1 = field 2 F0 F1 Fig. 2–12: Front sync format 14 Micronas VDP 31xxB PRELIMINARY DATA SHEET 2.8. Display Part 2.8.2. Black Level Expander In the display part the conversion from digital YCrCb to analog RGB is carried out. A block diagram is shown in Figure 2–20. In the luminance processing path, contrast and brightness adjustments and a variety of features, such as black level expansion, dynamic peaking and soft limiting, are provided. In the chrominance path, the CrCb signals are converted to 20.25 MHz sampling rate and filtered by a color transient improvement circuit. The YCrCb signals are converted by a programmable matrix to RGB color space. The black level expander enhances the contrast of the picture. Therefore the luminance signal is modified with an adjustable, non-linear function. Dark areas of the picture are changed to black, while bright areas remain unchanged. The advantage of this black level expander is that the black expansion is performed only if it will be most noticeable to the viewer. The display processor provides separate control settings for two pictures, i.e. different coefficients for a ‘main’ and a ‘side’ picture. The digital OSD insertion circuit allows the insertion of a 5-bit OSD signal. The color space for this signal is controlled by a partially programmable color look-up table (CLUT) and contrast adjustment. The OSD signals and the display clock are synchronized to the horizontal flyback. For the display clock, a gate delay phase shifter is used. In the analog backend, three 10-bit digital-to-analog converters provide the analog output signals. 2.8.1. Luma Contrast Adjustment The contrast of the luminance signal can be adjusted by multiplication with a 6-bit contrast value. The contrast value corresponds to a gain factor from 0 to 2, where the value 32 is equivalent to a gain of 1. The contrast can be adjusted separately for main picture and side picture. The black level expander works adaptively. Depending on the measured amplitudes ‘Lmin’ and ‘Lmax’ of the lowpass-filtered luminance and an adjustable coefficient BTLT, a tilt point ‘Lt’ is established by Lt = Lmin + BTLT (Lmax – Lmin). Above this value there is no expansion, while all luminance values below this point are expanded according to: Lout = Lin + BAM (Lin – Lt) A second threshold, Ltr, can be programmed, above which there is no expansion. The characteristics of the black level expander are shown in Fig. 2–13 and Fig. 2–14. The tilt point Lt is a function of the dynamic range of the video signal. Thus, the black level expansion is only performed when the video signal has a large dynamic range. Otherwise, the expansion to black is zero. This allows the correction of the characteristics of the picture tube. Lmax a) Lt Lmin Lmax Lout Ltr b) Lt BAM BTLT Lt Lmin Ltr BTHR Lin Fig. 2–13: Characteristics of the black level expander Micronas Fig. 2–14: Black-level-expansion a) luminance input b) luminance input and output 15 VDP 31xxB PRELIMINARY DATA SHEET 2.8.3. Dynamic Peaking Especially with decoded composite signals and notch filter luminance separation, as input signals, it is necessary to improve the luminance frequency characteristics. With transparent, high-bandwidth signals, it is sometimes desirable to soften the image. In the VDP 31xxB, the luma response is improved by ‘dynamic’ peaking. The algorithm has been optimized regarding step and frequency response. It adapts to the amplitude of the high frequency part. Small AC amplitudes are processed, while large AC amplitudes stay nearly unmodified. The center frequency of the peaking filter is switchable from 2.5 MHz to 3.2 MHz. For S-VHS and for notch filter color decoding, the total system frequency responses for both PAL and NTSC are shown in figure 2–16. Transients, produced by the dynamic peaking when switching video source signals, can be suppressed via the priority bus. dB 20 15 10 5 0 The dynamic range can be adjusted from *14 to )14 dB for small high frequency signals. There is separate adjustment for signal overshoot and for signal undershoot. For large signals, the dynamic range is limited by a non-linear function that does not create any visible alias components. The peaking can be switched over to “softening” by inverting the peaking term by software. –5 –10 –15 –20 MHz 0 4 6 8 10 Fig. 2–15: Dynamic peaking frequency response dB dB 20 20 15 CF= 2.5 MHz 15 CF= 3.2 MHz 10 10 5 5 S-VHS 0 0 –5 –5 –10 –10 –15 –15 –20 MHz 0 2 4 6 8 –20 10 MHz 0 dB 2 4 6 8 10 dB 20 20 CF= 3.2 MHz 15 CF= 2.5 MHz 15 10 10 5 5 PAL/SECAM 0 0 –5 –5 –10 –10 –15 –15 –20 MHz 0 2 4 6 8 –20 10 0 2 4 6 8 10 MHz dB dB 20 20 CF= 3.2 MHz 15 CF= 2.5 MHz 15 10 10 5 5 NTSC 0 0 –5 –5 –10 –10 –15 –15 –20 2 0 2 4 6 8 10 MHz –20 MHz 0 2 4 6 8 10 Fig. 2–16: Total frequency response for peaking filter and S-VHS, PAL, NTSC 16 Micronas VDP 31xxB PRELIMINARY DATA SHEET signal itself. Therefore, the gain is adjustable from 16/16 to 1/16, when the slope value varies from 0 to 15. The tilt value can be adjusted from 0 to 511. 2.8.4. Digital Brightness Adjustment The DC-level of the luminance signal can be adjusted by adding an 8-bit number in the luminance signal path in front of the softlimiter. Part 2 has the same characteristics as part 1. The subtracting part is also relative to the input signal, so the total differential gain will become negative if the sum of slope 1 and slope 2 is greater than 16 and the input signal is above the both tilt values (see characteristics). With a contrast adjustment of 32 (gain+1) the signal can be shifted by "100%. After the brightness addition, the negative going signals are limited to zero. It is desirable to keep a small positive offset with the signal to prevent undershoots produced by the peaking from being cut. The digital brightness adjustment is separate for main and side picture. Finally, the output signal of the soft limiter will be clipped by a hard limiter adjustable from 256 to 511. 2.8.6. Chroma Input 2.8.5. Soft Limiter The chroma input signal is a multiplexed CR and CB signal in 8-bit binary offset code. It can be switched between normal and inverted signal and between two’s complement and binary offset code. The delay in respect to the luminance input can be adjusted in 5 steps within a range of "2 clock periods. The dynamic range of the processed luma signal must be limited to prevent the CRT from overload. An appropriate headroom for contrast, peaking and brightness can be adjusted by the TV manufacturer according to the CRT characteristics. All signals above this limit will be ‘soft’-clipped. A characteristic diagram of the soft limiter is shown in Fig. 2–17. The total limiter consists of three parts: 2.8.7. Chroma Interpolation A linear phase interpolator is used to convert the chroma sampling rate from 10.125 MHz (4:2:2) to 20.25 MHz (4:4:4). All further processing is carried out at the full sampling rate. Part 1 includes adjustable tilt point and gain. The gain before the tilt value is 1. Above the tilt value, a part (0...15/16) of the input signal is subtracted from the input Part 1 Output 511 Part 2 slope 1 [0...15] 0 2 4 6 8 10 12 14 400 300 200 Hard limiter 0 2 4 6 8 10 12 range= 256...511 14 slope 2 [0...15] Calculation Example for the Softlimiter Input Amplitude. (The real signal processing in the limiter is 2 bit more than described here) Y Input Black Level Contrast Dig. Brightness BLE Peaking 16...235 (ITUR) 16 (constant) 63 20 off off Limiter input signal: (Yin-Black Level)·Contr./32 + Brightn. 100 tilt 1 [ 0...511] (235–16) · 63/32 + 20 = 451 tilt 2 [0...511] 0 0 100 200 300 400 500 600 700 800 900 Limiter Input 1023 Fig. 2–17: Characteristic of soft limiter a and b and hard limiter Micronas 17 VDP 31xxB PRELIMINARY DATA SHEET 2.8.8. Chroma Transient Improvement 2.8.9. Inverse Matrix The intention of this block is to enhance the chroma resolution. A correction signal is calculated by differentiation of the color difference signals. The differentiation can be selected according to the signal bandwidth, e.g. for PAL/NTSC/SECAM or digital component signals, respectively. The amplitude of the correction signal is adjustable. Small noise amplitudes in the correction signal are suppressed by an adjustable coring circuit. To eliminate ‘wrong colors’, which are caused by over and undershoots at the chroma transition, the sharpened chroma signals are limited to a proper value automatically. A 6-multiplier matrix transcodes the Cr and Cb signals to R–Y, B–Y, and G–Y. The multipliers are also used to adjust color saturation in the range of 0 to 2. The coefficients are signed and have a resolution of 9 bits. There are separate matrix coefficients for main and side pictures. The matrix computes: a) R–Y+MR1*Cb)MR2*Cr G–Y+MG1*Cb)MG2*Cr B–Y+MB1*Cb)MB2*Cr The initialization values for the matrix are computed from the standard ITUR (CCIR) matrix: R G + B Cr in Cb in ǒ Ǔ 1 0 1.402 1 * 0.345 * 0.713 1 1.773 0 Y Cb Cr For a contrast setting of CTM+32, the matrix values are scaled by a factor of 64, see also table 3–1. t 2.8.10. RGB Processing b) Ampl. t After adding the post-processed luma, the digital RGB signals are limited to 10 bits. Three multipliers are used to digitally adjust the white drive. Using the same multipliers an average beam current limiter is implemented. See also section 2.9.1. ‘CRT Measurement and Control’. c) 2.8.11. OSD Color Lookup Table Cr out Cb out t a) Cr Cb input of DTI b) Cr Cb input)Correction signal c) sharpened and limited Cr Cb Fig. 2–18: Digital Color Transient Improvement The VDP 31xxB has five input lines for an OSD signal. This signal forms a 5-bit address for a color look-up table (CLUT). The CLUT is a memory with 32 words where each word holds a RGB value. Bits 0 to 3 (bit 4+0) form the addresses for the ROM part of the OSD, which generates full RGB signals (bit 0 to 2) and half-contrast RGB signals (bit 3). Bit 4 addresses the RAM part of the OSD with 16 freely programmable colors, addressable with bit 0 to 3. The programming is done via the I2C-bus. The amplitude of the CLUT output signals can be adjusted separately for R, G and B via the I2C-bus. The switchover between video RGB and OSD RGB is done via the Priority bus. 18 Micronas VDP 31xxB PRELIMINARY DATA SHEET 2.8.12. Picture Frame Generator 2.8.14. Scan Velocity Modulation When the picture does not fill the total screen (height or width too small) it is surrounded with black areas. These areas (and more) can be colored with the picture frame generator. This is done by switching over the RGB signal from the matrix to the signal from the OSD color look-up table. The RGB input signal of the SVM is converted to Y in a simple matrix. Then the Y signal is differentiated by a filter of the transfer function 1–Z–N, where N is programmable from 1 to 6. With a coring, some noise can be suppressed. This is followed by a gain adjustment and an adjustable limiter. The analog output signal is generated by an 8-bit D/A converter. The width of each area (left, right, upper, lower) can be adjusted separately. The generator starts on the right, respectively lower side of the screen and stops on the left, respectively upper side of the screen. This means, it runs during horizontal, respectively vertical flyback. The color of the complete border can be stored in the programmable OSD color look-up table in a separate address. The format is 3 4 bit RGB. The contrast can be adjusted separately. The signal delay can be adjusted by ±3.5 clocks in halfclock steps. For the gain and filter adjustment there are two parameter sets. The switching between these two sets is done with the same RGB switch signal that is used for switching between video-RGB and OSD-RGB for the RGB outputs. (See Fig. 2–19). 2.8.15. Display Phase Shifter The picture frame generator includes a priority master circuit. Its priority is programmable and the border is generated only if the priority is higher than the priority at the PRIO bus. Therefore the border can be underlay or overlay depending on the picture source. A phase shifter is used to partially compensate the phase differences between the video source and the flyback signal. By using the described clock system, this phase shifter works with an accuracy of approximately 1 ns. It has a range of 1 clock period which is equivalent to ±24.7 ns at 20.25 MHz. The large amount of phase shift (full clock periods) is realized in the front-end circuit. 2.8.13. Priority Codec The priority decoder has three input lines for up to eight priorities. The highest priority is all three lines at low level. A 5-bit information is attached to each priority (see table 3–1 ‘Priority Bus’). These bits are programmable via the I2C-bus and have the following meanings: – one of two contrast, brightness and matrix values for main and side picture – RGB from video signal or color look-up table – disable/enable black level expander – disable/enable peaking transient suppression when signal is switched – disable/enable analog fast blank input 1 – disable/enable analog fast blank input 2 R G B N1 Matrix and Shaping Modulation Notch N2 Differentiator 1–Z–Nx Coring Coring adjustment Gain1 Gain2 Gain adjustment RGB Switch Limit Delay Limiter Delay adjustment D/A Converter Output Fig. 2–19: SVM block diagram Micronas 19 dynamic peaking dig. Y in clock prio softlimiter 8 luma insert for CRTmeasurement 5 CLUT, Contrast black level expander Matrix R’ prio Cr 3 PRIO decoder select coefficients dig. Gout 10 G whitedrive B x beamcurr. lim. Matrix B’ Phase Shift 0...1 clock dig. Bout 10 B main picture Scan Velocity Modulation Micronas Matrix saturation SVMout PRELIMINARY DATA SHEET PRIO in Phase Shift 0...1 clock DTI (Cb) side picture 10 whitedrive G x beamcurr. lim. Matrix G’ Cb dig. Rout R DTI (Cr) Interpol 4:4:4 horizontal flyback whitedrive R x beamcurr. lim. Phase Shift 0...1 clock 8 dig. CrCb in display & clock control Picture Frame Generator Y dig. OSD in blanking for CRTmeasurement VDP 31xxB Fig. 2–20: Digital back-end 20 whitedrive measurement brightness + offset contrast VDP 31xxB PRELIMINARY DATA SHEET Cutoff and white drive current measurement are carried out during the vertical blanking interval. They always use the small bandwidth setting. The current range for the cutoff measurement is set by connecting a sense resistor to the MADC input. For the whitedrive measurement, the range is set by using another sense resistor and the range select switch 2 output pin (RSW2). During the active picture, the minimum and maximum beam current is measured. The measurement range can be set by using the range select switch 1 pin (RSW1) as shown in Fig. 2–21 and Fig. 2–22. The timing window of this measurement is programmable. The intention is to automatically detect letterbox transmission or to measure the actual beam current. All control loops are closed via the external control microprocessor. 2.9. Analog Back End The digital RGB signals are converted to analog RGBs using three video digital to analog converters (DAC) with 10-bit resolution. An analog brightness value is provided by three additional DACs. The adjustment range is 40% of the full RGB range. Controlling the whitedrive/analog brightness and also the external contrast and brightness adjustments is done via the Fast Processor, located in the front-end. Control of the cutoff DACs is via I2C-bus registers. Finally cutoff and blanking values are added to the RGB signals. Cutoff (dark current) is provided by three 9-bit DACs. The adjustment range is 60% of full scale RGB range. beam current The analog RGB-outputs are current outputs with current-sink characteristics. The maximum current drawn by the output stage is obtained with peak white RGB. An external half contrast signal can be used to reduce the output current of the RGB outputs to 50%. A D MADC SENSE RSW1 2.9.1. CRT Measurement and Control RSW2 The display processor is equipped with an 8-bit PDMADC for all measuring purposes. The ADC is connected to the sense input pin, the input range is 0 to 1.5V. The bandwidth of the PDM filter can be selected; it is 40/80 kHz for small/large bandwidth setting. The input impedance is more than 1 MΩ. R2 R3 R1 Fig. 2–21: MADC Range Switches CR + IBRM + WDRV·WDR CR + IBRM black ultra black white drive cutoff R R R CG + IBRM cutoff G CB + IBRM active measurement resistor R1øR2øR3 PICTURE MEAS. Lines R1 RSW1=on, RSW2=on PMSO G cutoff B B R1øR3 R1øR2øR3 RSW2 =on RSW1=on, RSW2=on PICTURE MEAS. TUBE MEASUREMENT TML PMST Fig. 2–22: MADC Measurement Timing Micronas 21 VDP 31xxB In each field two sets of measurements can be taken: a) The picture tube measurement returns results for PRELIMINARY DATA SHEET The vertical timing for the picture measurement is programmable, and may even be a single line. Also the signal bandwidth is switchable for the picture measurement. – cutoff R – cutoff G – cutoff B – white drive R or G or B (sequentially) Two horizontal windows are available for the picture measurement. The large window is active for the entire active line. Tube measurement is always carried out with the small window. Measurement windows for picture and tube measurement are shown in Figure 2–23. tube measurement picture meas. start b) The picture measurement returns data on – active picture maximum current active video field 1/ 2 – active picture minimum current The tube measurement is automatically started when the cutoff blue result register is read. Cutoff control for RGB requires one field only while a complete white-drive control requires three fields. If the measurement mode is set to ‘offset check’, a measurement cycle is run with the cutoff/whitedrive signals set to zero. This allows to compensate the MADC offset as well as input the leakage currents. During cutoff and whitedrive measurements, the average beam current limiter function (ref. 2.9.3.) is switched off and a programmable value is used for the brightness setting. The start line of the tube measurement can be programmed via I2C-bus, the first line used for the measurement, i.e. measurement of cutoff red, is 2 lines after the programmed start line. The picture measurement must be enabled by the control microprocessor after reading the min./max. result registers. If a ‘1’ is written into bit 2 in subaddress 25, the measurement runs for one field. For the next measurement a ‘1’ has to be written again. The measurement is always started at the beginning of active video. 22 ÍÍÍ ÍÍÍ ÍÍÍÍÍÍÍÍÍ picture meas. end small window for tube measurement (cutoff, white drive) large window for active picture Fig. 2–23: Windows for tube and picture measurements 2.9.2. SCART Output Signal The RGB output of the VDP 31xxB can also be used to drive a SCART output. In the case of the SCART signal, the parameter CLMPR (clamping reference) has to be set to 1. Then, during blanking, the RGB outputs are automatically set to 50% of the maximum brightness. The DC offset values can be adjusted with the cutoff parameters CR, CG, and CB. The amplitudes can be adjusted with the drive parameters WDR, WDG, and WDB. Micronas VDP 31xxB PRELIMINARY DATA SHEET 2.9.3. Average Beam Current Limiter 2.9.4. Analog RGB Insertion The average beam current limiter (BCL) uses the sense input for the beam current measurement. The BCL uses a different filter to average the beam current during the active picture. The filter bandwidth is approx. 2 kHz. The beam current limiter has an automatic offset adjustment that is active two lines before the first cutoff measurement line. The VDP 31xxB allows insertion of 2 external analog RGB signals. Each RGB signal is key-clamped and inserted into the main RGB by the fast blank switch. The selected external RGB input is virtually handled as a priority bus signal. Thus, it can be overlaid or underlaid to the digital picture. The external RGB signals can be adjusted independently as regards DC-level (brightness) and magnitude (contrast). The beam current limiter function is located in the frontend. The data exchange between the front-end and the back-end is done via a single-wire serial interface. The beam current limiter allows the setting of a threshold current. If the beam current is above the threshold, the excess current is low-pass filtered and used to attenuate the RGB outputs by adjusting the white-drive multipliers for the internal (digital) RGB signals, and the analog contrast multipliers for the analog RGB inputs, respectively. The lower limit of the attenuator is programmable, thus a minimum contrast can always be set. During the tube measurement, the ABL attenuation is switched off. After the white drive measurement line it takes 3 lines to switch back to BCL limited drives and brightness. beam current Typical characteristics of the ABL for different loop gains are shown in Fig. 2–24; for this example the tube has been assumed to have square law characteristics. Which analog RGB input is selected depends on the fast blank input signals and the programming of a number of I2C-bus register settings (see Table 2–3 and Fig. 2–25). Both fast blank inputs must be either active-low or active-high. All signals for analog RGB insertion (RIN1/2, GIN1/2, BIN1/2, FBLIN1/2, HCS) must be synchronized to the horizontal flyback, otherwise a horizontal jitter will be visible. The VDP 31xxB has no means for timing correction of the analog RGB input signals. Table 2–3: RGB Input Selection FBFOH1 = 0, FBFOH2 = 0, FBFOL1 = 0, FBFOL2 = 0 FBLIN1 FBLIN2 FBPOL FBPRIO RGB output 0 0 0 x Video 0 1 0 x RGB input 2 1 0 0 x RGB input 1 1 1 0 0 RGB input 1 1 1 0 1 RGB input 2 0 0 1 0 RGB input 1 0 0 1 1 RGB input 2 0 1 1 x RGB input 1 1 0 1 x RGB input 2 1 1 1 x Video drive Fig. 2–24: Beam current limiter characteristics: beam current output vs. drive BCL threshold: 1 Micronas 23 VDP 31xxB PRELIMINARY DATA SHEET 2.9.5. Fast Blank Monitor 2.9.6. Half Contrast Control The presence of external analog RGB sources can be detected by means of a fast blank monitor. The status of the selected fast blank input can be monitored via an I2C bus register. There is a 2 bit information, giving static and dynamic indication of a fast blank signal. The static bit is directly reading the fast blank input line, whereas the dynamic bit is reading the status of a flip-flop triggered by the negative edge of the fast blank signal. Insertion of transparent text pages or OSD onto the video picture is often difficult to read, especially if the video contrast is high. The VDP 31xxB allows contrast reduction of the video background by means of a half contrast input (HCS pin). This input can be supplied with a fast switching signal (similar to the fast blank input), typically defining a rectangular box in which the video picture is displayed with reduced contrast. The analog RGB inputs are still displayed with full contrast. With this monitor logic it is possible to detect if there is an external RGB source active and if it is a full screen insertion or only a box. The monitor logic is connected directly to the FBLIN1 or FBLIN2 pin. Selection is done via I2C bus register. FBFOH1 FBFOL1 FBPOL FBPRIO The HCS input is multiplexed with the PORT0 input/output on the same pin, selection is done via I2C-bus register. If the HCS input is selected, then the port function of this pin is disabled and writing data into PORT0 will have no effect. If the HCS input is not selected, the I2C-bus register bits HCSFOH and HCSPOL must be used to disable the half contrast function. HCSPOL FBLIN1 # HCS Fast Blank Monitor Fast Blank Selection FB int # HCS intern FBLIN2 # HCSEN HCSFOH Fig. 2–26: Half Contrast Switch Logic FBFOH2 FBFOL2 FBMON Fig. 2–25: Fast Blank Selection Logic 2.10. IO Port Expander The VDP 31xxB provides a general purpose IO port to control and monitor up to seven external signals. The port direction is programmable for each bit individually. Via I2C bus register it is possible to write or read each port pin. Because of the relatively low I2C bus speed, only slow or static signals can be handled. The port signals are multiplexed with other signals to minimize pin count. PORT0 is multiplexed with the HCS input signal, PORT1 is multiplexed with the FSY output signal, PORT[6:2] are multiplexed with the color bus input COLOR[4:0]. The pin configuration is programmable via I2C bus register. All register bits can be read back, the default configuration after reset is input on PORT[1:0] and COLOR[4:0] enabled. 24 Micronas VDP 31xxB PRELIMINARY DATA SHEET digital SVM in 8 8 bit DAC SVM 1.88mA analog SVM out 0.94mA 10 bit DAC Video 3.75mA int. brightness * white drive B 10 digital B in 10 cutoff G digital G in 9 bit DAC 1.5 mA 9 bit DAC 1.5 mA 10 bit DAC Video 3.75mA 9 bit DAC 2.2 mA blanking 750 µA 9 bit DAC 2.2 mA blanking 750 µA 9 bit DAC 2.2 mA blanking 750 µA analog R out analog G out analog B out white drive R 9 bit DAC 1.5 mA 9 bit DAC 1.5 mA ext. brightness * white drive B serial interface ext. brightness * white drive G ext. brightness * white drive R H blank & measurem. timing 9 bit DAC 1.5 mA ext. brightness key 9 bit U/I–DAC 3.75mA 9 bit U/I–DAC 3.75mA ext. contrast * white drive B * beam current lim. ext. contrast ext. contrast * white drive G * beam current lim. int . brightness ext. contrast * white drive R * beam current lim. white drive G white drive B 8 bit ADC measurm. 9 bit U/I–DAC 3.75mA clamp & mux clamp & mux clamp & mux 1 2 analog R in 1 2 analog G in 1 2 analog B in V measurement buffer cutoff R 10 bit DAC Video 3.75mA int. brightness * white drive G 10 9 bit DAC 1.5 mA cutoff B digital R in int. brightness * white drive R HCS FBL prio 1 2 fast blank in Sense Input I/O Fig. 2–27: Analog back-end Micronas 25 VDP 31xxB 2.11. Synchronization and Deflection The synchronization and deflection processing is distributed over front-end and back-end. The video clamping, horizontal and vertical sync separation and all video related timing information are processed in the front-end. Most of the processing that runs at the horizontal frequency is programmed on the internal Fast Processor (FP). Also the values for vertical and East/ West deflection are calculated by the FP software. The information extracted by the video sync processing is multiplexed onto the hardware front sync signal (FSY) and distributed internally to the rest of the video processing system. The data for the vertical deflection, the sawtooth and the East/West correction signal is calculated in the front end. The data is transferred to the back-end by a single wire interface. The display related synchronization, i.e. generation of horizontal and vertical drive and synchronization of horizontal and vertical drive to the video timing extracted in the front-end, are implemented in hardware in the backend. 2.11.1. Deflection Processing The deflection processing generates the signals for the horizontal and vertical drive (see Fig. 2–28). This block contains two phase-locked loops: – PLL2 generates the horizontal and vertical timing, e.g. blanking, clamping and composite sync. Phase and frequency are synchronized by the front sync signal. – PLL3 adjusts the phase of the horizontal drive pulse and compensates for the delay of the horizontal output stage. Phase and frequency are synchronized by the oscillator signal of PLL2. The horizontal drive circuitry uses a digital sine wave generator to produce the exact (subclock) timing for the drive pulse. The generator runs at 1 MHz; in the output 26 PRELIMINARY DATA SHEET stage the frequency is divided down to give drive-pulse period and width. In standby mode, the output stage is driven from an internal 1 MHz clock that is derived from the 5 MHz clock signal and a fixed drive pulse width is used. When the circuit is switched out of standby operation, the drive pulse width is programmable. The horizontal drive uses an open drain output transistor. The Main Sync (MSY) signal that is generated from PLL3 is a multiplex of all display-related data (Fig. 2–29). This signal is intended for use by other processors, e.g. a PIP processor can use this signal to adjust to a certain display position. 2.11.2. Horizontal Phase Adjustment This section describes a simple way to align PLL phases and the horizontal frame position. 1. The parameter NEWLIN in the front-end has to be adjusted. The minimum possible value is 34 (recommended for a standard 4:3 signal). 2. With HDRV, the duration of the horizontal drive pulse has to be adjusted. 3. With POFS2, the clamping pulse for the analog RGB input has to be adjusted to the correct position, e.g. the pedestal of the generator signal. 4. With POFS3, the horizontal position of the analog RGB signal (from SCART) has to be adjusted. 5. With HPOS, the digital RGB output signal (from VPC) has to be adjusted to the correct horizontal position. 6. With HBST and HBSO, the start and stop values for the horizontal blanking have to be adjusted. Note: The processing delay of the internal digital video path differs depending on the comb filter option of the VDP 31xxB. The versions with comb filter have an additional delay of 35 clock cycles. Therefore, the timing of the external analog RGB signals has to be adjusted (with POFS2 and POFS3) according to the actual hardware version of the VDP 31xxB. The hardware version can be read out via FP subaddress 0xF1. Micronas VDP 31xxB PRELIMINARY DATA SHEET H flyback PLL3 main sync generator MSY skew measure– ment phase comparator & lowpass blanking, clamping, etc. display timing front sync interface FSY phase comparator & lowpass 1:64 & output stage sinewave DAC & generator LPF DCO H drive Standby clock PLL2 DCO composite sync generator line counter vertical reset CSY V flyback clock & control E/W correction PWM 15 bit sawtooth PWM 15 bit E/W ouput vertical serial data VDATA V output Fig. 2–28: Deflection processing block diagram input analog video MSY (not in scale) M1 M2 timing reference for PICTURE bus – chroma multiplex sync – active picture data after xxx clocks M1 line [0] line [7] Parity M2 line not not not not not [8] used used used used used F V Parity V: Vert. blanking 0 = off 1 = on F: Field # 0 = Field 1 1 = Field 2 line: Field line # 1...N Fig. 2–29: Main sync format Micronas 27 VDP 31xxB PRELIMINARY DATA SHEET 2.11.3. Vertical and East/West Deflection 2.11.4. Protection Circuitry The calculations of the vertical and East/West deflection waveforms is done by the internal Fast Processor (FP). The algorithm uses a chain of accumulators to generate the required polynomial waveforms. To produce the deflection waveforms, the accumulators are initialized at the beginning of each field. The initialization values must be computed by the TV control processor and are written to the front-end once. The waveforms are described as polynomials in x, where x varies from 0 to 1 for one field. – Picture tube and drive stage protection is provided through the following measures: P: a + b(x–0.5) + c(x–0.5)2 + d(x–0.5)3 + e(x–0.5)4 The initialization values for the accumulators a0..a3 for vertical deflection and a0..a4 for East/West deflection are 12-bit values. The vertical waveform can be scaled according the average beam current. This is used to compensate the effects of electric high tension changes due to beam current variations. In order to get a faster vertical retrace timing, the output impedance of the vertical D/A-converter can be reduced by 50% during the retrace. – Vertical flyback protection input: this pin searches for a negative edge in every field, otherwise the RGB drive signals are blanked. – Drive shutoff during flyback: this feature can be selected by software. – Safety input pin: this input has two thresholds. Between zero and the lower threshold, normal functioning takes place. Between the lower and the higher threshold, the RGB signals are blanked. Above the higher threshold, the RGB signals are blanked and the horizontal drive is shut off. Both thresholds have a small hysteresis. – The main oscillator and the horizontal drive circuitry are run from a separate (standby) power supply and are already active while the TV set is powering up. Fig. 2–30 shows several vertical and East/West deflection waveforms. The polynomial coefficients are also stated. Vertical: a,b,c,d 0,1,0,0 0,1,1,0 0,1,0,1 East/West: a,b,c,d,e 0,0,1,0,0 0,0,0,0,1 0,0,1,1,1 Fig. 2–30: Vertical and East/West deflection waveforms 28 Micronas VDP 31xxB PRELIMINARY DATA SHEET 2.12. Reset Function In the standby mode the following functions are still available (see also 2.11.1.): Reset of most VDP 31xxB functions is performed by the RESET pin. When this pin becomes active, all internal registers and counters are lost. When the RESET pin is released, the internal reset is still active for 4 µs. After that time, the initialization of all required registers is performed by the internal Fast Processor. During this initialization procedure (see Fig. 2–31) it is not possible to access the VDP 31xxB via the serial interface (I2C). Access to other ICs via the serial bus is possible during that time. – 20.25 MHz crystal oscillator The 5 MHz clock divider and the 1 MHz standby clock divider are not affected by reset. The clock source for the horizontal output generator is switched to the standby clock during reset. Reset 4µs approx. 60µs – 5 MHz clock output (CLK5) – horizontal drive output (HOUT) The clock source for the horizontal output generator is switched to the standby clock which is derived from the 5 MHz clock. The duty cycle of HOUT is set to 50%. Protection modes with safety and horizontal flyback pins are not available. The VDP 31xxB has clock and voltage supervision circuits to generate a stable HOUT signal during power-on and standby. The HOUT signal is disabled until a proper CLK5 signal (5 MHz clock) is detected. When released, the HOUT generator runs with the standby clock. Coupling the HOUT generator to the deflection PLL has to be done by CCU using the EHPLL bit. Fig. 2–32 shows the signals during power-on and standby. Internal Reset Initialization VSTBY Fig. 2–31: External Reset XTAL 1 µs CLK5 2.13. Standby and Power-On Clock Release In standby mode the whole signal processing of the VDP 31xxB is disabled and only some basic functions are working. The standby mode is realized by switching off the supplies for analog front-end (VSUPF), analog backend (VSUPO) and digital circuitry (VSUPD). The standby supply (VSTBY) still has its nominal voltage. HOUT To disable all the analog and digital functions, it is necessary to bring the analog and digital supplies below 0.5 V. Only this guarantees that all the normal functions are disabled and the standby current for analog and digital supply is at its minimum. When switched off, the negative slope of the supply voltage VSUPD should not be larger than approximately 0.2 V/µs (see Recommended Operating Conditions). In the standby mode, all registers and counter values in the VDP 31xxB are lost, they will be re-initialized via the internal Fast Processor after analog and digital supplies are switched on again and the RESET pin is released. Micronas VSUPD standby mode RESET Fig. 2–32: Power-On, Standby On/Off Switching the HOUT signal into standby mode can be done by the CCU via the EHPLL bit or by the internal voltage supervision. The voltage supervision activates a power-down signal when the supply for the digital circuits (VSUPD) goes below X4.5 V for more than 50ns. This power down signal is extended by 50µs after VSUPD is back again. The power-down signal switches the clock source for the HOUT generation to the standby clock and sets the duty cycle to 50%. This is exactly what the EHPLL bit does. As the clocks from the deflection PLL and the standby clock are not in phase, the actual phase (High/Low) of the HOUT signal may be up to one PLL or standby clock (X1 µs) longer than a regular one when the clock source is changed. 29 VDP 31xxB PRELIMINARY DATA SHEET 3. Serial Interface 3.2. Control and Status Registers 3.1. I2C-Bus Interface Table 3–1 gives definitions of the VDP control and status registers. The number of bits indicated for each register in the table is the number of bits implemented in hardware, i.e. a 9-bit register must always be accessed using two data bytes but the 7 MSB will be ‘don’t care’ on write operations and ‘0’ on read operations. Write registers that can be read back are indicated in Table 3–1. Communication between the VDP and the external controller is done via I2C-bus. The VDP has two I2C-bus slave interfaces (for compatibility with VPC/DDP applications) – one in the front-end and one in the backend. Both I2C-bus interfaces use I2C clock synchronization to slow down the interface if required. Both I2C-bus interfaces use one level of subaddress: the I2C-bus chip address is used to address the IC and a subaddress selects one of the internal registers. The I2C-bus chip addresses are given below: Chip Address A6 A5 A4 A3 A2 A1 A0 R/W front-end 1 0 0 0 1 1 1 1/0 back-end 1 0 0 0 1 0 1 1/0 The registers of the VDP have 8 or 16-bit data size; 16-bit registers are accessed by reading/writing two 8-bit data words. Functions implemented by software in the on-chip control microprocessor (FP) are explained in Table 3–3. A hardware reset initializes all control registers to 0. The automatic chip initialization loads a selected set of registers with the default values given in Table 3–1. The register modes given in Table 3–1 are – w: – w/r: – r: – v: write only register write/read data register read data from VDP register is latched with vertical sync – h: register is latched with horizontal sync The mnemonics used in the Micronas VDP demo software are given in the last column. Figure 3–1 shows I2C-bus protocols for read and write operations of the interface; the read operation requires an extra start condition and repetition of the chip address with read command set. S 1000 111 W Ack 0111 1100 Ack 1 or 2 byte Data S 1000 111 W Ack 0111 1100 Ack S SDA S SCL 1 0 1000 111 Ack P R Ack P I2C write access subaddress 7c high byte Data Ack low byte Data Nak W R Ack Nak S P = = = = = = I2C read access subaddress 7c P 0 1 0 1 Start Stop Fig. 3–1: I2C-bus protocols 30 Micronas VDP 31xxB PRELIMINARY DATA SHEET Table 3–1: I2C control and status registers of front-end I2C Sub address Number of bits Mode Function Default Name FP INTERFACE h’35 8 r FP status bit [0] bit [1] bit [2] write request read request busy FPSTA h’36 16 w bit[8:0] bit[11:9] 9-bit FP read address reserved, set to zero FPRD h’37 16 w bit[8:0] bit[11:9] 9-bit FP write address reserved, set to zero FPWR h’38 16 w/r bit[11:0] FP data register, reading/writing to this register will autoincrement the FP read/ write address. Only 16 bit of data are transferred per I2C telegram. FPDAT BLACK LINE DETECTOR h’12 16 w/r read only register, do not write to this register! after reading, LOWLIN and UPLIN are reset to 127 to start a new measurement bit[6:0] number of lower black lines bit[7] always 0 bit[14:8] number of upper black lines bit[15] 0/1 normal/black picture BLKLIN LOWLIN UPLIN BLKPIC PIN CIRCUITS h’1F h’20 16 8 w/r w/r INTLC & PORT pins: bit[2:0] 0..7 output strength for INTLC & PORT Pins (7 = tristate, 6 = weak ... 0 = strong) bit[3] 0 reserved (set to 0) bit[4] 0/1 pushpull/tristate for INTLC Pin bit[5] 0/1 synchronization/no synchronization with horizontal MSY for signal INTLC bit[15:6] reserved (set to 0) SYNC GENERATOR CONTROL: bit[6:0] 0 reserved (set to 0) bit[7] 0/1 positive/negative polarity for INTLC signal 0 TRPAD SNCSTR 0 0 SNCDIS VASYSEL SYNMODE 0 INTLCINV PRIORITY BUS h’24 Micronas 8 w/r priority bus ID register and control bit [2:0] 0..7 priority ID, 0 highest bit [4:3] 0..3 pad driver strength, 0 (strong) to 3 (weak) bit [5] 0/1 reserved (set to 0) bit [6] 0/1 source for prio request: active video/clamp_to_1 bit [7] 0/1 disable/enable priority interface, if disabled frontend is disconnected from priority bus! PRIOMODE 0 0 0 0 PID PRIOSTR 0 PIDE PIDSRC 31 VDP 31xxB I2C Sub address Number of bits PRELIMINARY DATA SHEET Mode Function Default Name 1295 LINLEN SYNC GENERATOR h’21 h’29 h’22 16 16 16 w/r w/r w/r LINE LENGTH: bit[10:0] bit[15:11] LINE LENGTH register LINE LENGTH has to be set to 1295 for correct adjustment of vertical signals. reserved (set to 0) AVO STOP: bit[10:0] bit[11] 0/1 bit[13:12] 00 01 10 11 bit[14] 0/1 bit[15] 0/1 reserved (set to 0) disable/enable test pattern generator luma output mode: Y = rampe (240 ... 17) Y = 16 Y = 90 Y = 240 reserved (set to 0) chroma output: pseudo color bar/zero NEWLINE: bit[10:0] bit [15:11] 32 AVSTOP NEWLINE register This register defines the readout start of the next line in respect to the value of the sync counter. Value of this register must be greater than 31 for correct operation. reserved (set to 0) 0 0 0 COLBAREN LMODE 0 0 CMODE 50 NEWLIN Micronas VDP 31xxB PRELIMINARY DATA SHEET Table 3–2: Backend I2C-control and status registers I2C sub address Number of bits Mode Function Default Name PRIORITY BUS priority mask register, if bit[x] is set to 1 then the function is active for the respective signal priority h’75 9 wv bit [7:0] bit[x] 0/1: select contrast,brightness,matrix for main/side picture 0 PBCT h’71 9 wv bit [7:0] bit[x] 0/1: select main (video)/external (via CLUT) RGB 0 PBERGB h’7d 9 wv bit [7:0] bit[x] 0/1: enable/disable black level expander 0 PBBLE h’79 9 wv bit [7:0] bit[x] 0/1: disable/enable peaking transient suppression when signal is switched 0 PBPK h’4b 9 wv bit [7:0] bit[x] 0/1: disable/enable analog fast blank input 0 PBFB h’47 9 wv bit [2:0] bit [8] picture frame generator priority id enable prio id for picture frame generator 0 PFGID PFGEN LUMA CHANNEL h’61 9 wv bit [5:0] 0..63/32 main picture contrast 32 CTM h’65 9 wv bit [5:0] 0..63/32 side picture contrast 32 CTS h’51 9 wv bit [8:0] –256..255 main picture brightness 0 BRM h’55 9 wv bit [8:0] –256..255 side picture brightness 0 BRS h’59 9 wv black level expander: bit [3:0] 0..15 bit [8:4] 0...31 tilt coefficient amount 8 12 BTLT BAM black level expander: bit [8:0] 0..511 disable expansion, threshold value 200 BTHR 4 4 0 PKUN PKOV PKINV 3 COR 0 PFS 0 0 LSLSA LSLSB 255 1 LSLAL LSLM h’5d h’69 h’6d h’41 9 9 9 9 wv wv wv wv luma peaking filter, the gain at high frequencies and small signal amplitudes is: 1 + (k1+k2)/8 bit [3:0] 0..15 k1: peaking level undershoot bit [7:4] 0..15 k2: peaking level overshoot bit [8] 0/1 peaking value normal/inverted (peaking/softening) luma peaking filter, coring bit [4:0] 0..31 coring level bit [7:5] reserved bit [8] 0/1 peaking filter center frequency high/low luma soft limiter, slope A and B bit [3:0] slope segment A bit [7:4] slope segment B h’45 9 wv bit [7:0] bit [8] 0/1 h’49 9 wv bit [8:0] luma soft limiter segment B tilt point (unsigned) 300 LSLTB h’4d 9 wv bit [8:0] luma soft limiter segment A tilt point (unsigned) 250 LSLTA Micronas luma soft limiter absolute limit (unsigned) modulation off/on 33 VDP 31xxB I2C sub address Number of bits PRELIMINARY DATA SHEET Mode Function Default Name CHROMA CHANNEL h’14 h’66 8 9 w/r wv luma/chroma matching delay bit [2:0] –3...3 variable chroma delay bit [3] 0/1 chroma polarity signed / offset binary bit [4] 0/1 CB (U) sample first / CR (V) sample first bit [7:5] reserved, set to 0 0 1 0 0 LDB COB ENVU digital transient improvement bit [3:0] 0..15 coring value bit [7:4] 0..15 DTI gain bit [8] 0/1 narrow/wide bandwidth mode 1 5 1 DTICO DTIGA DTIMO INVERSE MATRIX h’7c h’74 9 9 wv wv main picture matrix coefficient R–Y = MR1M*CB + MR2M*CR bit [8:0] –256/128 ... 255/128 bit [8:0] –256/128 ... 255/128 0 86 MR1M, MR2M h’6c h’64 9 9 wv wv main picture matrix coefficient G–Y = MG1M*CB + MG2M*CR bit [8:0] –256/128 ... 255/128 bit [8:0] –256/128 ... 255/128 –22 –44 MG1M, MG2M h’5c h’54 9 9 wv wv main picture matrix coefficient B–Y = MB1M*CB + MB2M*CR bit [8:0] –256/128 ... 255/128 bit [8:0] –256/128 ... 255/128 113 0 MB1M, MB2M h’78 h’70 9 9 wv wv side picture matrix coefficient R–Y = MR1S*CB + MR2S*CR bit [8:0] –256/128 ... 255/128 bit [8:0] –256/128 ... 255/128 0 73 MR1S, MR2S h’68 h’60 9 9 wv wv side picture matrix coefficient G–Y = MG1S*CB + MG2S*CR bit [8:0] –256/128 ... 255/128 bit [8:0] –256/128 ... 255/128 –19 –37 MG1S, MG2S h’58 h’50 9 9 wv wv side picture matrix coefficient B–Y = MB1S*CB + MB2S*CR bit [8:0] –256/128 ... 255/128 bit [8:0] –256/128 ... 255/128 97 0 MB1S, MB2S 000h f00h 0f0h ff0h 00fh f0fh 0ffh fffh 7ffh 700h 070h 770h 007h 707h 077h 777h CLUT0 COLOR LOOK-UP TABLE h’00– h’0f h’11 34 16 16 wh wh color look-up table : 16 entries, 12 bit wide, The CLUT registers are initialized at power-up bit [3:0] 0..15 blue amplitude bit [7:4] 0..15 green amplitude bit [11:8] 0..15 red amplitude picture frame color 12 bit wide, bit [3:0] 0..15 blue amplitude bit [7:4] 0..15 green amplitude bit [11:8] 0..15 red amplitude 0 0 0 CLUT15 PFCB PFCG PFCR Micronas VDP 31xxB PRELIMINARY DATA SHEET I2C sub address Number of bits Mode h’4c 9 wv h’48 h’44 9 9 wv wv Function Default digital OSD insertion contrast for R (amplitude range: 0 to 255) bit [3:0] 0..13 R amplitude = CLUTn · (DRCT + 4) 14,15 invalid picture frame insertion contrast for R (ampl. range: 0 to 255) bit [7:4] 0..13 R amplitude = PFCR · (PFRCT + 4) 14,15 invalid digital OSD insertion contrast for G (amplitude range: 0 to 255) bit [3:0] 0..13 G amplitude = CLUTn · (DGCT + 4) 14,15 invalid picture frame insertion contrast for G (ampl. range: 0 to 255) bit [7:4] 0..13 G amplitude = PFCG · (PFGCT + 4) 14,15 invalid digital OSD insertion contrast for B (amplitude range: 0 to 255) bit [3:0] 0..13 B amplitude = CLUTn · (DBCT + 4) 14,15 invalid picture frame insertion contrast for B (ampl. range: 0 to 255) bit [7:4] 0..13 B amplitude = PFCB · (PFBCT + 4) 14,15 invalid Name 8 DRCT 8 PFRCT 8 DGCT 8 PFGCT 8 DBCT 8 PFBCT PICTURE FRAME GENERATOR h’4F 9 wv bit [8:0] horizontal picture frame begin code 0 = picture frame generator horizontally disabled code 1FF = full frame 0 PFGHB h’53 9 wv bit [8:0] horizontal picture frame end 0 PFGHE h’63 9 wv bit [8:0] vertical picture frame begin code 0 = picture frame generator vertically disabled 270 PFGVB h’6f 9 wv bit [8:0] vertical picture frame end 56 PFGVE video mode coefficients bit [5:0] gain1 bit [8:6] differentiator delay 1 (0= filter off, 1...6= delay) 60 4 SVG1 SVD1 text mode coefficients bit [5:0] gain 2 bit [8:6] differentiator delay 2 (0= filter off, 1...6= delay) 60 4 SVG2 SVD2 100 0 SVLIM 7 SVDEL 0 SVCOR enable and priority – see under ‘PRIORITY BUS’ picture frame color – see under ‘COLOR LOOK-UP TABLE’ SCAN VELOCITY MODULATION h’62 h’5e h’5a h’56 Micronas 9 9 9 9 wv wv wv wv limiter bit [6:0] bit [8:5] limit value not used, set to ”0” delay and coring bit [3:0] adjustable delay, in 1/2 display clock steps, (value 5 : delay of SVMOUT is the same as for RGBOUT bit [7:4] coring value bit [8] not used, set to ”0” 35 VDP 31xxB I2C sub address Number of bits PRELIMINARY DATA SHEET Mode Function Default Name DISPLAY CONTROLS h’52 h’4e h’4a 9 9 9 wv wv wv cutoff Red cutoff Green cutoff Blue 0 0 0 CR CG CB TUBE AND PICTURE MEASUREMENT h’7b h’6b h’7f h’25 h’13 9 9 9 8 16 8 wv wv wv w/r w/r r h’18 h’19 h’1a h’1d h’1c h’1b h’1e 8 r picture measurement start line bit [8:0] (TML+9)..511 first line of picture measurement 23 PMST picture measurement stop line bit [8:0] (PMST+1)..511 last line of picture measurement 308 PMSO tube measurement line bit [8:0] 0..511 start line for tube measurement tube and picture measurement control bit [0] 0/1 disable/enable tube measurement bit [1] 0/1 80/40 kHz bandwidth for picture measurement bit [2] 0/1 disable/enable picture measurement (writing a ’1’ starts one measurement cycle) bit [3] 0/1 large/small picture measurement window, will be disabled from bit[3] in address h’32 bit [4] 0/1 measure / offset check for adc bit [7:5] reserved white drive measurement control bit [9:0] 0..1023 RGB values for white drive beam current measurement bit [10] reserved bit [11] 0/1 RGB values for white drive beam current measurement disabled/enabled 15 0 TML PMC TMEN PMBW PMEN PMWIN OFSEN 512 WDRV 0 EWDM measurement result registers minimum in active picture maximum in active picture white drive cutoff/leakage red cutoff/leakage green cutoff/leakage blue, read pulse starts tube measurement – measurement adc status and fast blank input status – MRMIN MRMAX MRWDR MRCR MRCG MRCB PMS measurement status register bit [0] 0/1 tube measurement active / complete bit [2:1] white drive measurement cycle 00 red 01 green 10 blue 11 reserved bit [3] 0/1 picture measurement active / complete bit [4] 0/1 fast blank input low / high (static) bit [5] 1 fast blank input negative transition since last read (bit reset at read) bit [7:6] reserved 36 Micronas PRELIMINARY DATA SHEET I2C sub address Number of bits VDP 31xxB Mode Function Default Name wv vertical blanking start bit [8:0] 0..511 first line of vertical blanking 305 VBST vertical blanking stop bit [8:0] 0..511 last line of vertical blanking 25 VBSO 30 AVST 0 STIMP –141 POFS2 0 POFS3 TIMING h’67 h’77 h’73 h’5f 9 9 9 9 wv wv wv start of Black Level Expander measurement bit [8:0] 0..511 first line of measurement, stop with first line of vertical blanking bit [8:0] free running field period = (value)4) lines HORIZONTAL DEFLECTION h’7a 9 wv adjustable delay of PLL2, clamping, and blanking (relative to front sync) adjust clamping pulse for analog RGB input bit [8:0] –256..+255 " 8 µs h’76 9 wv adjustable delay of flyback, main sync, csync and analog RGB (relative to PLL2) adjust horizontal drive or csync bit [8:0] –256..+255 "8 µs h’7e 9 wv adjustable delay of main sync (relative to flyback) adjust horizontal position for digital picture bit [8:0] 20 steps+1 µs h’5b 9 w/r h’57 9 w/r h’6a h’6e h’72 9 9 9 wv wv wv h’15 16 w/r Micronas 120 HPOS start of horizontal blanking bit [8:0] 0..511 1 HBST end of horizontal blanking bit [8:0] 0..511 48 HBSO 2 1 2 PKP3 PKP2 PKI2 32 HDRV 0 0 EHPLL EFLB 0 1 DUBL EBL 0 DCRGB 0 SELFT 0 0 DVPR XDEFL 1 DISKA PLL2/3 filter coefficients, 1of5 bit code (n+ set bit number) bit [5:0] proportional coefficient PLL3, 2–n–1 bit [5:0] proportional coefficient PLL2, 2–n–1 bit [5:0] integral coefficient PLL2, 2–n–5 horizontal drive and vertical signal control register bit [5:0] 0..63 horizontal drive pulse duration in ms (internally limited to 4..61) bit [6] 0/1 disable/enable horizontal PLL2 and PLL3 bit [7] 0/1 1: disable horizontal drive pulse during flyback bit [8] 0/1 reserved, set to ’0’ bit [9] 0/1 enable/disable ultra black blanking bit [10] 0/1 0: all outputs blanked 1: normal mode bit [11] 0/1 enable/disable clamping for analog RGB input bit [12] 0/1 disable/enable vertical free running mode (FIELD is set to field2, no interlace) bit [13] 0/1 enable/disable vertical protection bit [14] 0/1 internal/external (under VPC control) start of vertical and E/W signal bit [15] 0/1 disable/enable phase shift of display clock 37 VDP 31xxB I2C sub address Number of bits PRELIMINARY DATA SHEET Mode Function Default Name OUTPUT PINS h’10 8 w/r output pin configuration bit [2:0] pin driver strength, MSY and CSY 7 = tristate 6 = minimum strength 0 = maximum strength bit [4:3] reserved (set to 0) bit [5] 0/1 disable/enable internal resistor for vertical and East/West drive output bit [7:6] function of CSY pin : 00 composite sync signal output 01 25 Hz output (field1/field2 signal) 10 no interlace (field 2), output = 0 11 1 MHz horizontal drive clock 0 PSTSY VEWXR CSYM MISCELLANEOUS h’32 h’31 h’34 8 8 16 w/r w/r w/r fast blank interface mode bit [0] 0 internal fast blank 1 from FBLIN1 pin 1 force internal fast blank 1 signal to high bit [1] 0/1 internal fast blank active high/low bit [2] 0/1 disable/enable clamping reference for RGB outputs bit [3] 1 full line MADC measurement window, disables bit [3] in address h’25 bit [4] 0/1 horizontal flyback input active high/low bit [6:5] reserved (set to 0) bit [7] 0 internal fast blank 1 from FBLIN1 pin 1 force internal fast blank 1 signal to low 0 fast blank interface mode 2 bit [0] 0 internal fast blank 2 from FBLIN2 pin 1 force internal fast blank 2 signal to high bit [1] 0 internal fast blank 2 from FBLIN2 pin 1 force internal fast blank 2 signal to low bit [2] fast blank input priority 0 FBLIN1 > FBLIN2 1 FBLIN1 < FBLIN2 bit [3] fast blank monitor input select 0 monitor connected to FBLIN1 pin 1 monitor connected to FBLIN2 pin bit [4] half contrast switch enable 0 PORT0 enable / HCS disable 1 PORT0 disable / HCS enable bit [5] 0 half contrast from HCS pin 1 force half contrast signal to high bit [6] 0/1 half contrast active high/low at HCS pin bit [7] reserved (set to 0) 0 IO Port bit [6:0] bit [7] 0 0 1 bit [14:8] 0 1 bit [15] 0 1 38 data to/from PORT[6:0] front sync output at PORT1 PORT1 input/output enable FSY output enable port direction switch PORT[bit–8] to input switch PORT[bit–8] to output port enable COLOR[4:0] enable / PORT[6:2] disable COLOR[4:0] disable / PORT[6:2] enable FBMOD FBFOH1 FBPOL CLMPR FLMW FLPOL FBFOL1 FBMOD2 FBFOH2 FBFOL2 FBPRIO FBMON HCSEN HCSFOH HCSPOL IOPORT IODATA FSYOEN IODIR IOEN Micronas VDP 31xxB PRELIMINARY DATA SHEET Table 3–3: Control Registers of the Fast Processor for control of front-end functions – default values are initialized at reset FP Subaddress Function Default Name Standard Selection h’20 Standard select: bit[2:0] standard 0 PAL B,G,H,I (50 Hz) 4.433618 1 NTSC M (60 Hz) 3.579545 2 SECAM (50 Hz) 4.286 3 NTSC44 (60 Hz) 4.433618 4 PAL M (60 Hz) 3.575611 5 PAL N (50 Hz) 3.582056 6 PAL 60 (60 Hz) 4.433618 7 NTSC COMB (60 Hz) 3.579545 bit[3] 0/1 standard modifier PAL modified to simple PAL NTSC modified to compensated NTSC SECAM modified to monochrome 625 NTSCC modified to monochrome 525 bit[4] reserved (set to 0) bit[5] 0/1 2-H comb filter off/on bit[6] 0/1 S-VHS mode off/on 0 sdt pal ntsc secam ntsc44 palm paln pal60 ntscc sdtmod comb svhs Option bits allow to suppress parts of the initialization, this can be used for color standard search: bit[7] bit[8] bit[9] bit[10] no hpll setup no vertical setup no acc setup 2-H comb filter set-up only bit[11] status bit, normally write 0. After the FP has switched to a new standard, this bit is set to 1 to indicate operation complete. Standard is automatically initialized when the insel register is written. sdtopt h’22 picture start position, this register sets the start point of active video, this can be used e.g. for panning. The setting is updated when ’sdt’ register is updated. 0 sfif h’23 luma/chroma delay adjust. The setting is updated when ’sdt’ register is updated. bit[5:0] reserved, set to zero bit[11:6] luma delay in clocks, allowed range is +1 ... –7 0 ldly Micronas 39 VDP 31xxB FP Subaddress PRELIMINARY DATA SHEET Function Default Name Standard Selection h’21 Input select: writing to this register will also initialize the standard bit[1:0] 00 01 10 11 bit[2] 0/1 bit[4:3] 00 01 10 11 bit[6:5] bit[7] bit[8] bit[10:9] 00 01 10 11 0/1 0/1 00 01 10 11 bit[11] luma selector VIN3 VIN2 VIN1 VIN4 chroma selector VIN1/CIN IF compensation off 6 dB/Okt 12 dB/Okt 10 dB/MHz only for SECAM chroma bandwidth selector narrow normal broad wide adaptive/fixed SECAM notch filter enable luma lowpass filter hpll speed no change terrestrial vcr mixed status bit, write 0, this bit is set to 1 to indicate operation complete. insel 00 vis 1 cis 00 ifc 01 cbw fntch lowp hpllmd Comb Filter h’27 comb filter control register bit[0] 0 comb coefficients are calculated for luma/chroma 1 comb coefficients for luma are used for luma and chroma bit[1] 0 luma comb strength depends on signal amplitude 1 luma comb strength is independent of amplitude bit[2] 0 reduced comb booster 1 max comb booster bit[4:3] 0..3 comb strength for chroma signal bit[6:5] 0..3 comb strength for luma signal bit[11:7] 0..31 overall limitation of the calculated comb coefficients 0 no limitation 31 max limitation (1/2) 0 cmb_uc cc 0 daa 1 kb 3 2 0 kc ky clim 25 kilvl Color Processing h’39 amplitude killer level (0:killer disabled) h’3a amplitude killer hysteresis 5 kilhy h’dc NTSC tint angle, ±512 = ±π/4 0 tint 40 Micronas VDP 31xxB PRELIMINARY DATA SHEET FP Subaddress Function Default Name DVCO h’f8 crystal oscillator center frequency adjust, –2048 ... 2047 h’f9 crystal oscillator center frequency adjustment value for line lock mode, true adjust value is DVCO – ADJUST. For factory crystal alignment, using standard video signal: set DVCO = 0, set lock mode, read crystal offset from ADJUST register and use negative value for initial center frequency adjustment via DVCO. h’f7 crystal oscillator line-locked mode, lock command/status write: 100 enable lock 0 disable lock read: 0 unlocked >2047 locked –720 read only dvco adjust 0 xlck 0 vfrc 1 dflw – asr read only nlpf FP Status Register h’12 general purpose control bits bit[2:0] reserved, do not change bit[3] vertical standard force bit[8:4] reserved, do not change bit[9] disable flywheel interlace bit[11:10] reserved, do not change to enable vertical free run mode set vfrc to 1 and dflw to 0 h’13 standard recognition status bit[0] 1 vertical lock bit[1] 1 horizontally locked bit[2] 1 no signal detected bit[3] 1 color amplitude killer active bit[4] 1 disable amplitude killer bit[5] 1 color ident killer active bit[6] 1 disable ident killer bit[7] 1 interlace detected bit[8] 1 no vertical sync detection bit[9] 1 spurious vertical sync detection bit[11:10] reserved h’cb number of lines per field, P/S: 312, N: 262 h’15 vertical field counter, incremented per field h’74 measured sync amplitude value, nominal: 768 (PAL), 732 (NTSC) read only sampl h’31 measured burst amplitude read only bampl h’f0 firmware version number bit[7:0] internal revision number bit[11:8] firmware release read only sw_version h’f1 hardware version number bit[7:0] internal hardware revision number bit[11:8] hardware id 0000 = VDP 3120B 1000 = VDP 3116B 0100 = VDP 3112B 1100 = VDP 3108B 1110 = VDP 3104B read only hw_version Micronas vcnt 41 VDP 31xxB FP Subaddress PRELIMINARY DATA SHEET Function Default Name Scaler Control Register h’40 scaler mode register bit[1:0] scaler mode 0 linear scaling mode 1 nonlinear scaling mode, ’panorama’ 2 nonlinear scaling mode, ’waterglass’ 3 reserved bit[10:2] reserved, set to 0 bit[11] scaler update 0 start scaler update command, when the registers are updated the bit is set to 1 h’41 luma offset register bit[6:0] luma offset 0..127 ITU-R output format: 57 CVBS output format: 4 this register is updated when the scaler mode register is written 57 yoffs h’42 active video length for 1-h FIFO bit[11:0] length in pixels this register is updated when the scaler mode register is written 1080 fflim h’43 scaler1 coefficient, this scaler is compressing the signal. For compression by a factor c the value c*1024 is required. bit[11:0] allowed values from 1024..4095 this register is updated when the scaler mode register is written h’44 scaler2 coefficient, this scaler is expanding the signal. For expansion by a factor c the value 1/c*1024 is required. bit[11:0] allowed values from 256..1024 this register is updated when the scaler mode register is written 0 scmode pano scinc1 1024 scinc2 1024 h’45 scaler1/2 nonlinear scaling coefficient this register is updated when the scaler mode register is written 0 scinc h’47 – h’4b scaler1 window controls, see table 5 12-bit registers for control of the nonlinear scaling this register is updated when the scaler mode register is written 0 scw1_0 – 4 h’4c – h’50 scaler2 window controls see table 5 12-bit registers for control of the nonlinear scaling this register is updated when the scaler mode register is written 0 scw2_0 – 4 42 Micronas VDP 31xxB PRELIMINARY DATA SHEET 3.2.1. Scaler Adjustment In case of linear scaling, most of the scaler registers need not be set. Only the scaler mode, active video length, and the fixed scaler increments (scinc1/scinc2) must be written. The adjustment of the scaler for nonlinear scaling modes should use the parameters given in Table 3–4. Table 3–4: Set-up values for nonlinear scaler modes Register Scaler Modes ‘waterglass’ border 35% ‘panorama’ border 30% center compression 3/4 5/6 4/3 6/5 scinc1 1643 1427 1024 1024 scinc2 1024 1024 376 611 scinc 90 56 85 56 fflim 945 985 921 983 scw1 – 0 110 115 83 94 scw1 – 1 156 166 147 153 scw1 – 2 317 327 314 339 scw1 – 3 363 378 378 398 scw1 – 4 473 493 461 492 scw2 – 0 110 115 122 118 scw2 – 1 156 166 186 177 scw2 – 2 384 374 354 363 scw2 – 3 430 425 418 422 scw2 – 4 540 540 540 540 Micronas 43 VDP 31xxB PRELIMINARY DATA SHEET Table 3–5: Control Registers of the Fast Processor for control of back-end functions – default values are initialized at reset FP Subaddress Function Default Name FP Display Control Register h’130 White Drive Red (0...1023) 700 WDR 1) h’131 White Drive Green (0...1023) 700 WDG 1) h’132 White Drive Blue 700 WDB 1) h’139 Internal Brightness, Picture (0...511), the center value is 256, the range allows for both increase and reduction of brightness. 256 IBR h’13c Internal Brightness, Measurement (0...511), the center value is 256, the brightness for measurement can be set to measure at higher cutoff current. The measurement brightness is independent of the drive values. 256 IBRM h’13a Analog Brightness for external RGB (0...511), the center value is 256, the range allows for both increase and reduction of brightness. 256 ABR h’13b Analog Contrast for external RGB (0...511) 350 ACT (0...1023) 1) The white drive values will become active only after writing the blue value WDB, latching of new values is indicated by setting the MSB of WDB. FP Display Control Register, BCL h’144 BCL threshold current, 0...2047 (max ADC output ~1152) h’142 BCL time constant 0...15 →13 ... 1700 msec h’143 BCL loop gain. 0..15 h’145 BCL minimum contrast 0...1023 h’105 Test register for BCL/EHT comp. function, register value: 0 normal operation 1 stop ADC offset compensation x>1 use x in place of input from Measurement ADC 1000 BCLTHR 15 BCLTM 0 BCLG 307 BCLMIN 0 BCLTST FP Display Control Register, Deflection h’103 interlace offset, –2048..2047 This value is added to the SAWTOOTH output during one field. 0 INTLC h’102 discharge sample count for deflection retrace, SAWTOOTH DAC output impedance is reduced for DSCC lines after vertical retrace. 7 DSCC h’11f vertical discharge value, SAWTOOTH output value during discharge operation, typically same as A0 init value for sawtooth. –1365 DSCV h’10b EHT (electronic high tension) compensation coefficient, 0...511 h’10a EHT time constant. 0..15 ––> 3.2..410 msec 44 0 15 EHT EHTTM Micronas VDP 31xxB PRELIMINARY DATA SHEET Control Registers, continued FP Subaddress Function Default Name FP Display Control Register, Vertical Sawtooth h’110 DC offset of SAWTOOTH output This offset is independent of EHT compensation. 0 OFS h’11b accu0 init value –1365 A0 h’11c accu1 init value 900 A1 h’11d accu2 init value 0 A2 h’11e accu3 init value 0 A3 FP Display Control Register, East-West Parabola h’12b accu0 init value –1121 A0 h’12c accu1 init value 219 A1 h’12d accu2 init value 479 A2 h’12e accu3 init value –1416 A3 h’12f accu4 init value 1052 A4 Micronas 45 VDP 31xxB PRELIMINARY DATA SHEET 3.2.2. Calculation of Vertical and East-West Deflection Coefficients In Table 3–6 the formula for the calculation of the deflection initialization parameters from the polynomial coefficients a,b,c,d,e is given for the vertical and East-West deflection. Let the polynomial be P : a ) b(x * 0.5) ) c(x * 0.5) 2 ) d(x * 0.5) 3 ) e(x * 0.5) 4 The initialization values for the accumulators a0..a3 for vertical deflection and a0..a4 for East-West deflection are 12-bit values. The coefficients that should be used to calculate the initialization values for different field frequencies are given below, the values must be scaled by 128, i.e. the value for a0 of the 50 Hz vertical deflection is a0 + (a * 128 * b * 1365.3 ) c * 682.7 * d * 682.7)ń128 Table 3–6: Tables for the Calculation of Initialization values for Vertical Sawtooth and East-West Parabola Vertical Deflection 50 Hz a a0 128 a1 b c East-West Deflection 50 Hz d –1365.3 +682.7 –682.7 a0 899.6 –904.3 +1363.4 a1 296.4 898.4 a2 585.9 a3 a2 a3 Vertical Deflection 60 Hz a a0 a1 a2 a3 128 a b c c d –341.3 1365.3 –85.3 341.3 111.9 –899.6 84.8 –454.5 586.8 –111.1 898.3 72.1 –1171.7 a4 e 756.5 d East-West Deflection 60 Hz –1365.3 +682.7 –682.7 a 1083.5 –1090.2 +1645.5 a0 429.9 –1305.8 a1 1023.5 a2 a3 a4 46 128 b 128 b c d e –341.3 1365.3 –85.3 341.3 134.6 –1083.5 102.2 –548.4 849.3 –161.2 1305.5 125.6 –2046.6 1584.8 Micronas VDP 31xxB PRELIMINARY DATA SHEET 4. Specifications 4.1. Outline Dimensions SPGS0016-4/3E 33 1 32 3.8 ±0.1 3 2.5 64 0.3 19.3 ±0.1 18 ±0.1 4.8 ±0.4 3.2 ±0.4 1.9 (1) 57.7 ±0.1 0.27 ±0.06 1.778 ±0.05 1.29 0.457 20.1 ±0.5 0.3 1 ±0.1 31 x 1.778 = 55.118 ±0.1 Fig. 4–1: 64-Pin Plastic Shrink Dual-Inline Package (PSDIP64) Weight approximately 9.0 g Dimensions in mm 4.2. Pin Connections and Short Descriptions NC = not connected; leave vacant LV = if not used, leave vacant X = obligatory; connect as described in circuit diagram Pin No. Pin Name Type Connection Short Description (if not used) 1 TEST IN GNDDF Test Pin, reserved for Test 2 RESQ IN X Reset Input, Active Low 3 SCL IN/OUT X I2C Bus Clock 4 SDA IN/OUT X I2C Bus Data 5 DSGND X Digital Shield GNDD 6 PORT0 HCS IN/OUT LV IO Port Expander 0 / Half Contrast Switch 7 PORT1 FSY IN/OUT LV IO Port Expander 1 / Front Sync Output 8 CSY OUT LV Composite Sync Output 9 MSY OUT LV Main Sync Output 10 INTLC OUT LV Interlace Control Output 11 VPROT IN GNDO Vertical Protection Input 12 SAFETY IN GNDO Safety Input 13 HFLB IN HOUT Horizontal Flyback Input Micronas 47 VDP 31xxB Pin No. Pin Name PRELIMINARY DATA SHEET Type Connection Short Description (if not used) 48 14 GNDDF X Ground, Digital Circuitry Front-end 15 VSUPD X Supply Voltage, Digital Circuitry 16 GNDDO X Ground, Digital Circuitry Back-end 17 PR0 IN/OUT LV Picture Bus Priority Control (LSB) 18 PR1 IN/OUT LV Picture Bus Priority Control 19 PR2 IN/OUT LV Picture Bus Priority Control (MSB) 20 COLOR4 PORT2 IN/OUT GNDDF Picture Bus Color Address 4 / IO Port Expander 2 21 COLOR3 PORT3 IN/OUT GNDDF Picture Bus Color Address 3 / IO Port Expander 3 22 COLOR2 PORT4 IN/OUT GNDDF Picture Bus Color Address 2 / IO Port Expander 4 23 COLOR1 PORT5 IN/OUT GNDDF Picture Bus Color Address 1 / IO Port Expander 5 24 COLOR0 PORT6 IN/OUT GNDDF Picture Bus Color Address 0 / IO Port Expander 6 25 DSGND X Digital Shield GNDD 26 RSW2 OUT GNDO Range Switch2 for Measurement ADC 27 RSW1 OUT GNDO Range Switch1 for Measurement ADC 28 SENSE IN GNDO Sense ADC Input 29 GNDM X Ground, MADC Input 30 GNDV OUT LV Ground, Vertical Outputs 31 VERT OUT LV Vertical Sawtooth Output 32 EW OUT LV Vertical Parabola Output 33 XREF IN X Reference Input for RGB DACs 34 SVMOUT OUT VSUPO Scan Velocity Modulation Output 35 GNDO X Ground, Analog Back-end 36 VSUPO X Supply Voltage, Analog Back-end 37 ROUT OUT VSUPO Analog Red Output 38 GOUT OUT VSUPO Analog Green Output 39 BOUT OUT VSUPO Analog Blue Output 40 VRD IN X DAC Reference 41 RIN IN GNDO Analog Red Input 42 GIN IN GNDO Analog Green Input Micronas VDP 31xxB PRELIMINARY DATA SHEET Pin No. Pin Name Type Connection Short Description (if not used) 43 BIN IN GNDO Analog Blue Input 44 FBLIN IN GNDO Fast Blank Input 45 RIN2 IN GNDO Analog Red Input 2 46 GIN2 IN GNDO Analog Green Input 2 47 BIN2 IN GNDO Analog Blue Input 2 48 FBLIN2 IN GNDO Fast Blank Input 2 49 CLK20 OUT LV 20 MHz System Clock Output 50 HOUT OUT X Horizontal Drive Output 51 XTAL1 IN X Analog Crystal Input 52 XTAL2 OUT X Analog Crystal Output 53 VSTBY X Standby Supply Voltage 54 CLK5 LV 5 MHz Clock Output 55 GNDF X Ground, Analog Front-end 56 ISGND IN GNDF Signal Ground for Analog Input 57 VRT IN X Reference Voltage Top, Video ADC 58 VSUPF X Supply Voltage, Analog Front-end 59 VOUT OUT LV Analog Video Output 60 CIN IN VRT Analog Chroma Input 61 VIN1 IN VRT Analog Video 1 Input 62 VIN2 IN VRT Analog Video 2 Input 63 VIN3 IN VRT Analog Video 3 Input 64 VIN4 IN VRT Analog Video 4 Input OUT 4.3. Pin Descriptions Pin 1 – Test Input, TEST (Fig. 4–3) This pin enables factory test modes. For normal operation it must be connected to ground. Pin 4 – I2C Bus Data, SDA (Fig. 4–12) This pin connects to the I2C bus data line. Pin 5 – Ground (Digital Shield), DSGND Pin 2 – Reset Input, RESQ (Fig. 4–3) A low level on this pin resets the VDP 31xxB. Pin 3 – I2C Bus Clock, SCL (Fig. 4–12) This pin connects to the I2C bus clock line. Micronas Pin 6, 7, 20–24 – IO Port Expander, PORT[6:0] (Fig. 4–13) These pins provide an I2C programmable I/O port, which can be used to read and write slow external signals. 49 VDP 31xxB Pin 6 – Half Contrast Switch Input, HCS (Fig. 4–16) Via this input pin the output level of the analog RGB output pins can be reduced by 3dB. Pin 7 – Front Sync Output, FSY (Fig. 4–13) This pin supplies the front sync information Pin 8 – Composite Sync Output, CSY (Fig. 4–13) This output supplies a standard composite sync signal that is compatible to the analog RGB output signals. Pin 9 – Main Sync Output, MSY (Fig. 4–13) This pin supplies the main sync information. Pin 10 – Interlace Output, INTLC (Fig. 4–13) This pin supplies the interlace information, 0 indicates first field, 1 indicates second field. Pin 11 – Vertical Protection Input, VPROT (Fig. 4–14) The vertical protection circuitry prevents the picture tube from burn-in in the event of a malfunction of the vertical deflection stage. During vertical blanking, a signal level of 2.5V is sensed. If a negative edge cannot be detected, the RGB output signals are blanked. Pin 12 – Safety Input, SAFETY (Fig. 4–14) This is a three-level input. Low level means normal function. At the medium level RGB signals are blanked and at high level RGB signals are blanked and horizontal drive is shut off. Pin 13 – Horizontal Flyback Input, HFLB (Fig. 4–14) Via this pin the horizontal flyback pulse is supplied to the VDP 31xxB. Pin 14 – Ground (Digital Circuitry Front-end), GNDDF Pin 15 – Supply Voltage (Digital Circuitry), VSUPD Pin 16 – Ground (Digital Circuitry Back-end), GNDDO Pin 17, 18, 19 – Picture Bus Priority, PR[2:0] (Fig. 4–5) The Picture Bus Priority lines carry the digital priority selection signals. The priority interface allows digital switching of up to 8 sources to the backend processor. Switching for different sources is prioritized and can be done from pixel to pixel. Pin 20...24 – Picture Bus Color Address, COLOR[4:0] (Fig. 4–16) The Picture Bus COLOR lines carry the digital RGB color data. They are used as address for the color lookup table. Pin 25 – Ground (Digital Shield), DSGND. 50 PRELIMINARY DATA SHEET Pin 26, 27 – Range Switch for Measurement ADC, RSW1, RSW2 (Fig. 4–19) These pins are open drain pull-down outputs. RSW1 is switched off during cutoff and whitedrive measurement. RSW2 is switched off during cutoff measurement only. Pin 28 – Measurement ADC Input, SENSE (Fig. 4–15) This is the input of the analog digital converter for the picture and tube measurement. Pin 29 – Ground (Measurement ADC Reference Input), GNDM This is the ground reference for the measurement A/D converter. Pin 30 – Ground (Vertical Sawtooth Output), GNDV (Fig. 4–20) This is the ground reference for the vertical outputs. Pin 31 – Vertical Sawtooth Output, VERT (Fig. 4–20) This pin supplies the drive signal for the vertical output stage. The drive signal is generated with 15-bit precision by the Fast Processor in the front-end. The analog voltage is generated by a 4-bit current-DAC with external resistor and uses digital noise shaping. Pin 32 – East-West Parabola Output, EW (Fig. 4–20) This pin supplies the parabola signal for the East-West correction. The drive signal is generated with 15 bit precision by the Fast Processor in the front-end. The analog voltage is generated by a 4-bit current-DAC with external resistor and uses digital noise shaping. Pin 33 – DAC Current Reference, XREF (Fig. 4–21) External reference resistor for DAC output currents, typical 10 kΩ to adjust the output current of the D/A converters (see recommended operating conditions). This resistor has to be connected to analog ground as closely as possible to the pin. Pin 34 – Scan Velocity Modulation Output, SVMOUT (Fig. 4–17) This output delivers the analog SVM signal. The D/A converter is a current sink like the RGB D/A converters. At zero signal the output current is 50% of the maximum output current. Pin 35 – Ground (Analog Back-end), GNDO Pin 36 – Supply Voltage (Analog Back-end), VSUPO Pin 37, 38, 39 – Analog RGB Outputs, ROUT, GOUT, BOUT (Fig. 4–17) This are the analog Red/Green/Blue outputs of the backend. The outputs sink a current of max. 8mA. Pin 40 – DAC Reference Decoupling, VRD (Fig. 4–21) Via this pin the DAC reference voltage is decoupled by an external capacitance. The DAC output currents depend on this voltage, therefore a pull-down transistor can be used to shut off all beam currents. A decoupling capacitor of 3.3µF//100nF is required. Micronas VDP 31xxB PRELIMINARY DATA SHEET Pin 44, 48 – Fast Blank Inputs, FBLIN1/2 (Fig. 4–15) These pins are used to switch the RGB outputs to the external analog RGB inputs. Pin 49 – Main Clock Output, CLK20 (Fig. 4–4) This is the 20.25MHz main system clock, that is used by all circuits in a high-end VDP system. All external timing is derived from this clock. Pin 50 – Horizontal Drive Output, HOUT (Fig. 4–18) This open drain output supplies the the drive pulse for the horizontal output stage. The polarity and gating with the flyback pulse are selectable by software. Pin 51, 52 – Crystal Input and Output, XTAL1, XTAL2 (Fig. 4–7) These pins are connected to an 20.25 MHz crystal oscillator is digitally tuned by integrated shunt capacitances. The Clk20 and Clk5 clock signals are derived from this oscillator. An external clock can be fed into XTAL1. In this case clock frequency adjustment must be switched off. Pin 53 – Standby Supply Voltage, VSTBY In standby mode, only the clock oscillator and the horizontal drive circuitry are active. Pin 54 – CCU 5 MHz Clock Output, CLK5 (Fig. 4–10) This pin provides a clock frequency for the TV microcontroller, e.g. a CCU3000 controller. Pin 55 – Ground (Analog Front-end), GNDF Pin 56 – Ground (Analog Signal Input), ISGND (Fig. 4–8) This is the high quality ground reference for the video input signals. Pin 57 – Reference Voltage Top, VRT (Fig. 4–8) Via this pin, the reference voltage for the A/D converters is decoupled. The pin is connected with 10 mF/47 nF to the Signal Ground Pin. Pin 58 – Supply Voltage (Analog Front-end), VSUPF Micronas Pin 59 – Analog Video Output, VOUT (Fig. 4–6) The analog video signal that is selected for the main (luma, cvbs) adc is output at this pin. An emitter follower is required at this pin. Pin 60 – Analog Chroma Input, CIN (Fig. 4–9) This pin is connected to the S-VHS chroma signal. A resistive divider is used to bias the input signal to the middle of the converter input range. CIN can only be connected to the chroma (Video 2) A/D converter. The signal must be AC-coupled. Pin 61...64 – Analog Video Input 1–4, VIN1–4 (Fig. 4–11) These are the analog video inputs. A CVBS or S-VHS luma signal is converted using the luma (Video 1) AD converter. The input signal must be AC-coupled. 4.4. Pin Configuration TEST 1 64 VIN4 RESQ 2 63 VIN3 SCL 3 62 VIN2 SDA 4 61 VIN1 DSGND 5 60 CIN PORT0/HCS 6 59 VOUT PORT1/FSY 7 58 VSUPF CSY 8 57 VRT MSY 9 56 ISGND INTLC 10 55 GNDF VPROT 11 54 CLK5 SAFETY 12 53 VSTBY HFLB 13 52 XTAL2 GNDDF 14 VSUPD 15 GNDDO 16 PR0 17 PR1 18 VDP 31xxB Pin 41, 42, 43, 45, 46, 47 – Analog RGB Inputs, RIN1/2, GIN1/2, BIN1/2 (Fig. 4–15) These pins are used to insert an external analog RGB signal, e.g. from a SCART connector which can by switched to the analog RGB outputs with the fast blank signal. The analog backend provides separate brightness and contrast settings for the external analog RGB signals. 51 XTAL1 50 HOUT 49 CLK20 48 FBLIN2 47 BIN2 PR2 19 46 GIN2 COLOR4/PORT2 20 45 RIN2 COLOR3/PORT3 21 44 FBLIN COLOR2/PORT4 22 43 BIN COLOR1/PORT5 23 42 GIN COLOR0/PORT6 24 41 RIN DSGND 25 40 VRD RSW2 26 39 BOUT RSW1 27 38 GOUT SENSE 28 37 ROUT GNDM 29 36 VSUPO GNDV 30 35 GNDO VERT 31 34 SVMOUT EW 32 33 XREF Fig. 4–2: 64-pin PSDIP package 51 VDP 31xxB PRELIMINARY DATA SHEET 4.5. Pin Circuits VSUPD VSUPF – + P VRT Vref ISGND GNDD Fig. 4–8: Pins VRT , ISGND Fig. 4–3: Input pins RESQ, TEST VSUPD P VSUPF P To ADC N N GNDD Fig. 4–4: Output pin CLK20 GNDF Fig. 4–9: Chroma input CIN VSUPD VSTBY P P N N N GNDF GNDD Fig. 4–10: Output pin CLK5 Fig. 4–5: Input/Output pins PR[2:0] Vin’s VSUPF VSUPF – + P VOUT VREF To ADC N GNDF Fig. 4–6: Output pin VOUT GNDF Fig. 4–11: Input pins VIN1–VIN4 VSTBY P P 0.5M N N f ECLK GNDD GNDF Fig. 4–7: Input/Output pins XTAL1, XTAL2 52 Fig. 4–12: Pins SDA, SCL Micronas VDP 31xxB PRELIMINARY DATA SHEET VSUPD VSUPO P N N BIAS N GNDD GNDO Fig. 4–13: Output pins FSY, MSY, CSY, INTLC, PORT[6:0] Fig. 4–17: Analog output pins ROUT, GOUT, BOUT, SVMOUT VSTDBY VSUPD N GNDD P P N N BIAS Fig. 4–18: Output pin HOUT GNDD VSUPO Fig. 4–14: Input pins SAFETY, VPROT, HFLB N GNDM VSUPO Fig. 4–19: Output pins RSW1, RSW2 P P N N BIAS VSUPO GNDO Fig. 4–15: Input pins FBLIN1/2, RIN1/2, BIN1/2, GIN1/2, SENSE P P GNDV Fig. 4–20: Output pins VERT, EW VSUPD VSUPO P VRD N GNDD Fig. 4–16: Input pins PORT[6:0] Micronas + – int. ref. voltage COLOR[4:0], ref. current XREF GNDO HCS, Fig. 4–21: Input pins XREF, VRD 53 VDP 31xxB PRELIMINARY DATA SHEET 4.6. Electrical Characteristics 4.6.1. Absolute Maximum Ratings Symbol Parameter Pin No. Min. Max. Unit TA Ambient Operating Temperature – 0 65 °C TS Storage Temperature – –40 125 °C VSUP Supply Voltage, all Supply Inputs –0.3 6 V VI Input Voltage, all Inputs –0.3 VSUP+0.3 V VO Output Voltage, all Outputs –0.3 VSUP+0.3 V Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 4.6.2. Recommended Operating Conditions Symbol Parameter Pin Name Min. Typ. Max. Unit TA Ambient Operating Temperature – 0 – 65 °C VSUP Supply Voltages, all Supply Pins 4.75 5.0 5.25 V fXTAL Clock Frequency XTAL1/2 – 20.25 – MHz Rxref RGB – DAC Current defining Resistor XREF 9.5 10 10.5 kW NSVDD Negative Slope of VDD (power down) VSUPD 0.2 V/µs 4.6.3. Recommended Crystal Characteristics 54 Symbol Parameter Min. Typ. Max. Unit TA Operating Ambient Temperature 0 – 65 °C fP Parallel Resonance Frequency with Load Capacitance CL = 13 pF – 20.250000 – MHz DfP/fP Accuracy of Adjustment – – $20 ppm DfP/fP Frequency Temperature Drift – – $30 ppm RR Series Resistance – – 25 W C0 Shunt Capacitance 3 – 7 pF C1 Motional Capacitance 20 – 30 fF Micronas VDP 31xxB PRELIMINARY DATA SHEET Recommended Crystal Characteristics, continued Symbol Parameter Min. Typ. Max. Unit – 3.3 – pF Load Capacitance Recommendation CLext External Load Capacitance 1) from pins to Ground (pin names: Xtal1 Xtal2) DCO Characteristics 2) 1) CICLoadmin Effective Load Capacitance @ min. DCO-Position, Code 0, 3.6 4.3 5 pF CICLoadrng Effective Load Capacitance Range, DCO Codes from 0..255 11.7 12.7 13.7 pF Remarks on defining the External Load Capacitance: External capacitors at each crystal pin to ground are required. They are necessary to tune the effective load capacitance of the PCBs to the required load capacitance CL of the crystal. The higher the capacitors, the lower the clock frequency results. The nominal free running frequency should match fp MHz. Due to different layouts of customer PCBs the matching capacitor size should be determined in the application. The suggested value is a figure based on experience with various PCB layouts. 720 Tuning condition: Code DVCO Register = –720 2) Remarks on Pulling Range of DCO: The pulling range of the DCO is a function of the used crystal and effective load capacitance of the IC (CICLoad +CLoadBoard). The resulting frequency fL with an effective load capacitance of CLeff = CICLoad + CLoadBoard is 1 + 0.5 * [ C1 / (C0 + CLeff ) ] fL = fP * ––––––––––––––––––––––– 1 + 0.5 * [ C1 / (C0 + CL ) ] 4.6.4. Characteristics at TA = 0 to 65 °C, VSUPD/F/O = 4.75 to 5.25 V, f = 20.25 MHz for min./max. values at TC = 60 °C, VSUPD/F/O = 5 V, f = 20.25 MHz for typical values Symbol Parameter Pin Name Min. Typ. Max. Unit IVSUPF Current Consumption VSUPF – 38 – mA IVSUPD Current Consumption VSUPD – 123 – mA IVSUPO Current Consumption VSUPO – 64 – mA IVSTDBY Current Consumption VSTDBY – 3.3 – mA PTOT Total Power Dissipation – 1145 1200 W IL Input / Output Leakage Current –1 – 1 mA Micronas All I/O Pins 55 VDP 31xxB PRELIMINARY DATA SHEET 4.6.4.1. 5 MHz Clock Output Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions VOL Output Low Voltage CLK5 – – 0.4 V IOL = 0.4 mA VOH Output High Voltage 4.0 – VSTDBY V –IOL = 0.9 mA tOT Output Transition Time – 50 ns CLOAD = 30 pF – 4.6.4.2. 20 MHz Clock Input/Output, External Clock Input (XTAL1) (see Fig. 4–22) Symbol Parameter Pin Name Unit Test Conditions VDCAV DC Average CLK20 V CLOAD = 30 pF VPP VOUT Peak to Peak 1.3 1.6 – V CLOAD = 30 pF tOT Output Transition Time – – 18 ns CLOAD = 30 pF VIT Input Trigger Level 2.1 2.5 2.9 V only for test purposes fF FMain Clock Frequency 10 20.25 24 MHz VFMIDC FMain Clock Input DC Voltage 1.0 – 3.5 V VFMIAC FM Clock Input AC Voltage (p–p) 0.8 – 2.5 V tFMIH tFMIL FM Clock Input High/Low Ratio 0.9 1.0 1.1 tFMIHL FM Clock Input High to Low Transition Time – – 0.15 fFM tFMILH FM Clock Input Low to High Transition Time – – 0.15 fFM tFMILH XTAL 1 Min. Typ. Max. VSUP/2 – 0.3 VSUP/2 VSUP/2 + 0.3 tFMIHL tFMIH tFMI L VFMIDC VFMIAC 0V DVSS Fig. 4–22: Main clock input 4.6.4.3. Reset Input, Test Input 56 Symbol Parameter Pin Name Min. Typ. Max. Unit VIL Input Low Voltage RESQ TEST – – 1.5 V VIH Input High Voltage 3.0 – – V Test Conditions Micronas VDP 31xxB PRELIMINARY DATA SHEET 4.6.4.4. I2C Bus Interface Symbol Parameter Pin Name Min. Typ. Max. Unit VIL Input Low Voltage SDA, SCL – – 1.5 V VIH Input High Voltage 3.0 – – V VOL Output Low Voltage – – 0.4 0.6 V V VIH Input Capacitance – – 4 pF tF Signal Fall Time – – 300 ns CL = 400 pF tR Signal Rise Time – – 300 ns CL = 400 pF fSCL Clock Frequency 0 – 400 kHz tLOW Low Period of SCL 1.3 – – ms tHIGH High Period of SCL 0.6 – – ms tSU Data Data Set Up Time to SCL high 100 – – ns tHD Data DATA Hold Time to SCL low 0 – 0.9 ms SCL SDA Test Conditions Il = 3 mA Il = 6 mA 4.6.4.5. IO Port Expander Symbol Parameter Pin Name Min. Typ. Max. Unit VIL Input Low Voltage PORT[6:0] – – 0.8 V VIH Input High Voltage 1.5 – – V VOL Output Low Voltage – 0.2 0.4 V IOL = 1.6 mA, strength 6 VOH Output High Voltage V –IOL = 1.6mA, strength 6 tOD Output Transition Time – – 35 ns CLOAD = 70pF IOL Output Current –10 – 10 mA driver imp. = 0 Test Conditions VSUPD – 0.4 – VSUPD Test Conditions 4.6.4.6. Analog Video Inputs Symbol Parameter Pin Name Min. Typ. Max. Unit VVIN Analog Input Voltage VIN1 VIN2 VIN3 VIN4 CIN 0 – 3.5 V CCP Input Coupling Capacitor Video Inputs VIN1 VIN2 VIN3 VIN4 – 680 – nF CCP Input Coupling Capacitor Chroma Input CIN – 1 – nF Micronas 57 VDP 31xxB PRELIMINARY DATA SHEET 4.6.4.7. Analog Front-End and ADCs Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions VVRT Reference Voltage Top VRT 2.5 2.6 2.8 V 10 mF/10 nF, 1 GW Probe RVIN Input Resistance 1 MW Code Clamp – DAC = 0 CVIN Input Capacitance VIN1 VIN2 VIN3 VIN4 VVIN Full Scale Input Voltage 1.8 2.0 2.2 VPP min. AGC Gain VVIN Full Scale Input Voltage 0.5 0.6 0.7 VPP max. AGC Gain AGC AGC Step Width dB DNLAGC AGC Differential Non-Linearity 6-Bit Resolution = 64 Steps fsig MHz, i = 1 MHz –2 dBr of max. AGC-Gain VVINCL Input Clamping Level, CVBS QCL Clamping DAC Resolution –16 ICL–LSB Input Clamping Current per Step 0.7 DNLICL Clamping DAC Differential NonLinearity CICL Clamping-Capacity Luma – Path 4.5 pF 0.166 ±0.5 1.0 LSB V Binary Level = 64 LSB min. AGC Gain 15 steps 1.3 mA 5 Bit – I-DAC, bipolar VVIN = 1.5 15V ±0.5 LSB 220 – nF 1.4 2.0 2.6 kW 1.0 Coupling-Cap. @ Inputs Chroma – Path RCIN Input Resistance SVHS Chroma CIN VIN1 VCIN Full Scale Input Voltage, Chroma 1.08 1.2 1.32 VPP VCINDC Input Bias Level, SVHS Chroma – 1.5 – V Binary Code for Open Chroma Input 128 Dynamic Characteristics for all Video Paths (Luma + Chroma) BW Bandwidth XTALK Crosstalk, any Two Video Inputs THD Total Harmonic Distortion SINAD Signal to Noise and Distortion Ratio INL Integral Non-Linearity, DNL 12.5 MHz –2 dBr input signal level –56 dB 1 MHz, –2 dBr signal level 50 dB 1 MHz, 5 harmonics, –2 dBr signal level 45 dB 1 MHz, all outputs, –2 dBr signal level ±1 LSB Code Density, DC-ramp DC ramp Differential Non-Linearity ±0.8 LSB DG Differential Gain ±3 % DP Differential Phase 1.5 deg 58 VIN1 VIN2 VIN3 VIN4 CIN 10 –12 dBr, 4.4 MHz signal on DCramp Micronas VDP 31xxB PRELIMINARY DATA SHEET Analog Front-End and ADCs, continued Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions VOUT 1.7 2.0 2.3 VPP VVIN = 1 VPP, AGC = 0 dB dB 3 Bit Resolution = 7 Steps 3 MSB’s of main AGC Analog Video Output VOUT Output Voltage AGCVOUT AGC Step Width, VOUT DNLAGC AGC Differential Non-Linearity VOUTDC DC-Level 1 V clamped to back porch BW VOUT Bandwidth 10 MHz Input: –2 dBr of main ADC range, CL ≤ 10 pF THD VOUT Total Harmonic Distortion –45 –40 dB Input: –2 dBr of main ADC range, CL ≤ 10 pF 1 MHz, 5 Harmonics CLVOUT Load Capacitance – – 10 pF ILVOUT Output Current – – ±0.1 mA 1.333 ±0.5 LSB 4.6.4.8. Picture Bus Input (see Fig. 4–23) Symbol Parameter Pin Name Min. Typ. Max. Unit VIL Input Low Voltage – – 0.8 V VIH Input High Voltage PR[2:0] COLCOL OR[4:0] 1.5 – – V tIS Input Setup Time 7 – – ns tIH Input Hold Time 5 – – ns Test Conditions Main Clock tIS tIH Data Inputs Fig. 4–23: Picture bus input timing Micronas 59 VDP 31xxB PRELIMINARY DATA SHEET 4.6.4.9. INTLC, Front Sync Output Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions VOL Output Low Voltage INTLC FSY – 0.2 0.4 V IOL = 1.6 mA, strength 6 VOH Output High Voltage VSUPD – 0.4 – VSUPD V –IOL = 1.6mA, strength 6 tOH Output Hold Time 6 14 ns CLOAD = 70pF tOD Output Delay Time – – 35 ns CLOAD = 70pF IOL Output Current –10 – 10 mA driver imp. = 0 4.6.4.10. Main Sync Output Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions VOL Output Low Voltage MSY – 0.2 0.4 V IOL = 1.6 mA, strength 6 VOH Output High Voltage VSUPD – 0.4 – VSUPD V –IOL = 1.6mA, strength 6 tOH Output Hold Time 6 14 ns CLOAD = 70pF tOD Output Delay Time – – 35 ns CLOAD = 70pF IOL Output Current –10 – 10 mA driver imp. = 0 4.6.4.11. Combined Sync Output Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions VOL Output Low Voltage CSY – – 0.4 V IOL = 1.6 mA strength 6 VOH Output High Voltage VSUPD – 0.4 – VSUPD V –IOL = 1.6 mA strength 6 tOT Output Transition Time – 10 20 ns CLOAD = 30 pF IOL Output Current –10 – 10 mA driver imp. = 0 60 Micronas VDP 31xxB PRELIMINARY DATA SHEET 4.6.4.12. Horizontal Flyback Input Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions VIL Input Low Voltage HFLB – – 1.8 V VIH Input High Voltage 2.6 – – V VIHST Input Hysteresis 0.1 – – V PSRRHF Power Supply Rejection Ratio of Trigger Level 0 dB f = 20 MHz PSRRMF Power Supply Rejection Ratio of Trigger Level –20 dB f < 15 kHz PSRRLF Power Supply Rejection Ratio of Trigger Level –40 dB f < 100 Hz tPID Internal Delay 12 ns slew rate 500 mV/ns swing 1 VPP 4.6.4.13. Horizontal Drive Output Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions VOL Output Low Voltage HOUT – – 0.4 V IOL = 10 mA VOH Output High Voltage (Open Drain Stage) – – 5 V external pull-up resistor tOF Output Fall Time – 8 20 ns CLOAD = 30pF IOL Output Low Current – – 10 mA 4.6.4.14. Vertical Protection Input Symbol Parameter Pin Name Min. Typ. Max. Unit VIL Input Low Voltage VPROT – – 1.8 V VIH Input High Voltage 2.6 – – V VIHST Input Hysteresis 0.1 – – V Test Conditions 4.6.4.15. Vertical Safety Input Symbol Parameter Pin Name Min. Typ. Max. Unit VILA Input Low Voltage A SAFETY – – 1.8 V VIHA Input High Voltage A 2.6 – – V VILB Input Low Voltage B – – 3.1 V VIHB Input High Voltage B 3.9 – – V VIHST Input Hysteresis A and B 0.1 – – V tPID Internal Delay 100 ns Micronas Test Conditions 61 VDP 31xxB PRELIMINARY DATA SHEET 4.6.4.16. Vertical and East/West Drive Output Symbol Parameter Pin Name Min. Typ. VOL Output Voltage LOW EW VERT VOH Output Voltage HIGH 2.82 3 Idacn Full scale DAC Output Current 415 PSRR Power Supply Rejection Ratio Max. Unit Test Conditions V Rload = 6800 Rxref = 10 kW 3.2 V Rload = 6800 Rxref = 10 kW 440 465 µA Vo = 0 V Rxref = 10 kW 20 – – dB 0 4.6.4.17. Sense A/D Converter Input Symbol Parameter Pin Name Min. Typ. Max. Unit VI Input Voltage Range SENSE 0 – Vsup V VI255 Input Voltage for code 255 1.4 1.54 1.7 V Read cutoff blue register C0 Digital Output for zero Input 16 LSB Offset check, read cutoff blue register RI Input Impedance 1 – – MW – – 50 W Test Conditions Range Switch Outputs RON Output On Resistance RSW1 RSW2 IMax Maximum Current – – 15 mA ILEAK Leakage Current – – 600 nA CIN Input Capacitance – – 4 pF IOL = 10 mA RSW High Impedance 4.6.4.18. Analog RGB and FB Inputs (continued on next page) Symbol Parameter Pin Name Min. Typ. Max. Unit VRGBIN External RGB Inputs Voltage Range –0.3 – 1.1 V VRGBIN nominal RGB Input Voltage peak-to-peak RIN GIN BIN RIN2 GIN2 BIN2 0.5 0.7 1.0 VPP VRGBIN RGB Inputs Voltage for Maximum Output Current 0.44 Contrast setting: 511 RGB Inputs Voltage for Maximum Output Current 0.7 Contrast setting: 323 RGB Inputs Voltage for Maximum Output Current 1.1 Contrast setting: 204 62 Test Conditions SCART Spec: 0.7 V ±3 dB Micronas VDP 31xxB PRELIMINARY DATA SHEET Analog RGB and FB Inputs, continued Symbol Parameter Pin Name CRGBIN External RGB Input Coupling Capacitor RIN GIN BIN RIN2 GIN2 BIN2 Clamp Pulse Width Min. Typ. Max. 15 µs Input Capacitance IIL Input Leakage Current VCLIP RGB Input Voltage for Clipping Current – – 13 pF –0.5 – 0.5 mA VCLAMP Clamp Level at Input 40 VINOFF Offset Level at Input VINOFF Offset Level Match at Input RCLAMP Clamping-ON-Resistance VFBLOFF FBLIN Low Level VFBLON FBLIN High Level VFBLTRIG Fast Blanking Trigger Level typical 0.7 tPID Delay Fast Blanking to RGBOUT from midst of FBLIN-transition to 90% of RGBOUT-transition 8 2 Difference of Internal Delay to External RGBin Delay Test Conditions nF 3.1 CIN FBLIN FBLIN2 Unit 60 Clamping OFF, VIN –0.3..3 V V 80 mV Clamping ON –10 10 mV Extrapolated from VIN = 100 mV and 200 mV –10 10 mV Extrapolated from VIN = 100 mV and 200 mV 140 – Ω – – 0.5 V 0.9 – – V 15 ns +5 ns –5 Switch-Over-Glitch 0.5 Internal RGB = 3.75 mA Full Scale Int. Brightness = 0 External Brightness = 1.5 mA (Full Scale) RGBin = 0 VFBLOFF = 0.4 V VFBLON = 1.0 V Rise and fall time = 2 ns pAs Switch from 3.75 mA (int) to 1.5 mA (ext) Test Conditions 4.6.4.19. Half Contrast Switch Input Symbol Parameter Pin Name Min. Typ. Max. Unit VIL Input Low Voltage HCS – – 0.8 V VIH Input High Voltage 1.5 – – V tHCS Delay HCS to RGBOUT from 50% of HCS-transition to 90% of RGBOUT-transition 80 120 ns Micronas Internal RGB = 3.75 mA VHCSL = 0.4 V VHCSH = 1.0 V Rise and fall time = 2 ns 63 VDP 31xxB PRELIMINARY DATA SHEET 4.6.4.20. Analog RGB Outputs, D/A Converters Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions – 10 – bit 3.6 3.75 3.9 mA Rref = 10 kΩ 1.74 1.87 2.0 mA Rref = 10 kΩ, IOUT = 3.75 mA Differential Nonlinearity 0.5 LSB Integral Nonlinearity 1 LSB Internal RGB Signal D/A Converter Characteristics Resolution IOUT Full Scale Output Current IOUTHC Half Contrast Output Current ROUT GOUT BOUT Glitch Pulse Charge 0.5 pAs Ramp signal, 25 Ω output termination tT Rise and Fall Time 3 ns 10% to 90%, 90% to 10% tRHC Half Contrast Rise Time 50 75 ns 60% to 90% IOUT = 3.75mA tFHC Half Contrast Fall Time 25 40 ns 90% to 60% IOUT = 3.75mA –50 dB 2/2.5 MHz full scale dB Signal: 1MHz full scale Bandwidth: 10MHz Intermodulation Signal to Noise +50 DRGB Matching R–G, R–B, G–B –2 2 % DRGBHC Half Contrast Matching R–G, R–B, G–B –5 5 % –46 dB –50 –50 –50 dB dB dB R/B/G Crosstalk one channel talks two channels talk RGB Input Crosstalk from external RGB one channel talks two channels talk three channels talk Passive channel: IOUT =1.88 mA Crosstalk-Signal: 1.25 MHz, 3.75 3 75 mAPP Internal RGB Brightness D/A Converter Characteristics Resolution ROUT GOUT BOUT 9 39.2 40 bits IBR Full Scale Output Current relative 40.8 IBR Full Scale Output Current absolute IBR differential nonlinearity 0.5 LSB IBR integral nonlinearity 1 LSB IBR Match R–G, R–B, G–B –2 2 % IBR Match to digital RGB R–R, G–G, B–B –2 2 % 1.5 % Ref to max. digital RGB mA External RGB Voltage/Current Converter Characteristics Resolution IEXOUT Full Scale Output Current relative Full Scale Output Current absolute 64 ROUT GOUT BOUT 9 96 100 3.75 bits 104 % Ref. to max. Digital RGB VIN = 0.7 VPP, contrast = 323 mA Same as Digital RGB Micronas VDP 31xxB PRELIMINARY DATA SHEET Analog RGB Outputs, D/A Converters, continued Symbol CR Parameter Pin Name Contrast Adjust Range ROUT GOUT BOUT Max. Unit Test Conditions –2 2 % Measured at RGB Outputs VIN = 0.7 V, contrast = 323 –3 3 % Measured at RGB Outputs VIN = 0.7 V, contrast = 323 R/B/G Input Crosstalk one channel talks two channels talk –46 dB Passive channel: VIN = 0.7V, contrast = 323 RGB Input Crosstalk from Internal RGB one channel talks two channels talk three channels talk –50 dB Crosstalk signal: 1.25 MHz, 3.75 mAPP RGB Input Noise and Distortion –50 dB VIN = 0.7 VPP at 1 MHz contrast = 323 Bandwidth: 10 MHz – MHz VIN = 0.7 VPP, contrast = 323 dB dB Input signal 1 MHz Input signal 6 MHz VIN = 0.7 VPP contrast = 323 VIN = 0.44 V Gain Match R–G, R–B, G–B Gain Match to RGB–DACs R–R, G–G, B–B VRGBO Min. Typ. 16:511 RGB Input Bandwidth –3dB 10 RGB Input THD –50 –40 15 Differential Nonlinearity of Contrast Adjust 1.0 LSB Integral nonlinearity of Contrast Adjust 7 LSB 0.3 V Referred to VSUPO 100 Ω Ref. to VSUPO –1.2 V Ref. to VSUPO Sum of max. Current of RGB–DACs and max. Current of Int. Brightness DACs is 2% degraded RGB Output Voltage –1.0 RGB Output Load Resistance VOUTC RGB Output Compliance –1.5 –1.3 External RGB Brightness D/A Converter Characteristics Resolution IEXBR Full Scale Output Current relative ROUT GOUT BOUT 9 39.2 Full Scale Output Current absolute Micronas 40 bits 40.8 1.5 % Ref to max. digital RGB mA Differential Nonlinearity 0.5 LSB Integral Nonlinearity 1 LSB Matching R–G, R–B, G–B –2 2 % Matching to digital RGB R–R, G–G, B–B –2 2 % 65 VDP 31xxB PRELIMINARY DATA SHEET Analog RGB Outputs, D/A Converters, continued Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions RGB Output Cutoff D/A Converter Characteristics Resolution ROUT GOUT BOUT 9 58.8 60 bits ICUT Full Scale Output Current relative 61.2 ICUT Full Scale Output Current absolute ICUT Differential nonlinearity 0.5 LSB ICUT Integral nonlinearity 1 LSB ICUT Match to digital RGB R–R, G–G, B–B 2 % 2.25 –2 % Ref to max. digital RGB mA RGB Output Ultrablack D/A Converter Characteristics Resolution IUB Full Scale Output Current relative ROUT GOUT BOUT 1 19.6 Full Scale Output Current absolute 20 bits 20.4 0.75 *2 Match to digital RGB R–R, G–G, B–B % Ref to max. digital RGB mA 2 % 4.6.4.21. DAC Reference, Beam Current Safety Symbol VDACREF VXREF Parameter Pin Name Min. Typ. Max. Unit Test Conditions DAC-Reference Voltage VRD/BCS 2.38 2.50 2.67 V DAC-Reference Output resistance VRD/BCS 18 25 32 kW DAC-Reference Voltage Bias Current Generation XREF 2.25 2.34 2.43 V Rref = 10 kΩ, Min. Typ. Max. Unit Test Conditions 4.6.4.22. Scan Velocity Modulation Output Symbol Parameter Pin Name SVM D/A Converter Characteristics Resolution IOUT Full Scale Output Current IOUT SVMOUT 8 2.25 mA Differential Nonlinearity 0.5 LSB IOUT Integral Nonlinearity 1 LSB IOUT Glitch Pulse Charge 0.5 pAs Ramp, output line is terminated on both ends with 50 Ohms IOUT Rise and Fall Time 3 nsec 10% to 90%, 90% to 10% 66 1.55 1.875 bit Micronas PRELIMINARY DATA SHEET VDP 31xxB 5. Application Circuit Micronas 67 VDP 31xxB 68 PRELIMINARY DATA SHEET Micronas PRELIMINARY DATA SHEET Micronas VDP 31xxB 69 VDP 31xxB 70 PRELIMINARY DATA SHEET Micronas PRELIMINARY DATA SHEET Micronas VDP 31xxB 71 VDP 31xxB PRELIMINARY DATA SHEET 6. Data Sheet History 1. Preliminary data sheet: “VDP 31xxB Video Processor Family”, Edition May 15, 1997, 6251-437-1PD. First release of the preliminary data sheet. 2. Preliminary data sheet: “VDP 31xxB Video Processor Family”, Edition Sept. 25, 1998, 6251-437-2PD. Second release of the preliminary data sheet. Major changes: – section 4.1.: package outline dimensions changed – section 4.6.: missing values have been defined – section 5.: application circuit diagram corrected Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: [email protected] Internet: www.micronas.com Printed in Germany Order No. 6251-437-2PD 72 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. Micronas