STMICROELECTRONICS VND830SP-E

VND830SP-E
DOUBLE CHANNEL HIGH SIDE DRIVER
Table 1. General Features
Type
VND830SP-E
Figure 1. Package
RDS(on)
Iout
VCC
60mΩ (*)
6A (*)
36V
(*) Per each channel
n CMOS COMPATIBLE INPUTS
n OPEN DRAIN STATUS OUTPUTS
n ON STATE OPEN LOAD DETECTION
n OFF STATE OPEN LOAD DETECTION
n SHORTED LOAD PROTECTION
n UNDERVOLTAGE AND OVERVOLTAGE
10
SHUTDOWN
1
PowerSO-10™
n LOSS OF GROUND PROTECTION
n VERY LOW STAND-BY CURRENT
n REVERSE BATTERY PROTECTION (**)
■
IN COMPLIANCE WITH THE 2002/95/EC
EUROPEAN DIRECTIVE
DESCRIPTION
The VND830SP-E is a monolithic device made by
using
STMicroelectronics
VIPower
M0-3
Technology, intended for driving any kind of load
with one side connected to ground. Active V CC pin
voltage clamp protects the device against low
energy
spikes
(see
ISO7637
transient
compatibility table).
Active current limitation combined with thermal
shutdown and automatic restart protects the
device against overload.The device detects open
load condition both in on and off state. Output
shorted to VCC is detected in the off state. Device
automatically turns off in case of ground pin
disconnection.
Table 2. Order Codes
Package
PowerSO-10™
Tube
VND830SP-E
Tape and Reel
VND830SPTR-E
Note: (**) See application schematic at page 9
Rev. 1
October 2004
1/20
VND830SP-E
Figure 2. Block Diagram
VCC
VCC
CLAMP
OVERVOLTAGE
UNDERVOLTAGE
GND
CLAMP 1
OUTPUT1
INPUT1
DRIVER 1
CLAMP 2
STATUS1
CURRENT LIMITER 1
OVERTEMP. 1
DRIVER 2
LOGIC
OUTPUT2
OPENLOAD ON 1
CURRENT LIMITER 2
INPUT2
OPENLOAD OFF 1
OPENLOAD ON 2
STATUS2
OPENLOAD OFF 2
OVERTEMP. 2
Table 3. Absolute Maximum Ratings
Symbol
VCC
Parameter
DC Supply Voltage
Value
Unit
41
V
- VCC
Reverse DC Supply Voltage
- 0.3
V
- IGND
DC Reverse Ground Pin Current
- 200
mA
Internally Limited
A
-6
A
DC Input Current
+/- 10
mA
DC Status Current
+/- 10
mA
4000
V
4000
V
5000
V
5000
V
(L=1.8mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC;
IL=9A)
100
mJ
Power Dissipation TC=25°C
73.5
W
Internally Limited
°C
IOUT
- IOUT
IIN
ISTAT
DC Output Current
Reverse DC Output Current
Electrostatic Discharge
R=1.5KΩ; C=100pF)
(Human
Body
Model:
- INPUT
VESD
- STATUS
- OUTPUT
- VCC
Maximum Switching Energy
EMAX
Ptot
Tj
Junction Operating Temperature
Tc
Case Operating Temperature
- 40 to 150
°C
Storage Temperature
- 55 to 150
°C
Tstg
2/20
VND830SP-E
Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins
5
4
3
6
7
8
9
10
GROUND
INPUT 1
STATUS 1
STATUS 2
INPUT 2
OUTPUT 1
OUTPUT 1
N.C.
OUTPUT 2
OUTPUT 2
2
1
11
VCC
Connection / Pin Status
Floating
X
To Ground
N.C.
X
X
Output
X
Input
X
Through 10KΩ resistor
Figure 4. Current and Voltage Conventions
IS
VF1 (*)
IIN1
IOUT1
ISTAT1
VIN1
OUTPUT 1
STATUS 1
VSTAT1
VCC
VCC
INPUT 1
VOUT1
IIN2
INPUT 2
IOUT2
VIN2 ISTAT2
OUTPUT 2
STATUS 2
VSTAT2
VOUT2
GND
IGND
(*) VFn = VCCn - VOUTn during reverse battery condition
Table 4. Thermal Data
Symbol
Rthj-case
Rthj-amb
Parameter
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Value
1.7
51.7 (1)
37 (2)
Unit
°C/W
°C/W
Note: 1. When mounted on a standard single-sided FR-4 board with 0.5cm 2 of Cu (at least 35µm thick). Horizontal mounting and no artificial
air flow.
Note: 2. When mounted on a standard single-sided FR-4 board with 6cm2 of Cu (at least 35µm thick). Horizontal mounting and no artificial
air flow.
3/20
VND830SP-E
ELECTRICAL CHARACTERISTICS
(8V<VCC<36V; -40°C < Tj < 150°C, unless otherwise specified)
(Per each channel)
Table 5. Power Output
Symbol
Parameter
VCC (**)
Min.
Typ.
Max.
Unit
Operating Supply Voltage
5.5
13
36
V
VUSD (**)
Undervoltage Shut-down
3
4
5.5
V
VOV (**)
Overvoltage Shut-down
36
RON
IS (**)
Test Conditions
On State Resistance
IOUT =2A; Tj=25°C
IOUT =2A; VCC> 8V
Off State; VCC=13V; VIN=VOUT=0V
Supply Current
Off State; VCC=13V; Tj =25°C;
VIN=VOUT =0V
On State; VCC=13V
V
60
mΩ
120
mΩ
12
40
µA
12
25
µA
5
7
mA
0
50
µA
-75
0
µA
IL(off1)
Off State Output Current
VIN=VOUT=0V; VCC=36V; Tj=125°C
IL(off2)
Off State Output Current
VIN=0V; VOUT =3.5V
IL(off3)
Off State Output Current
VIN=VOUT=0V; VCC=13V; Tj =125°C
5
µA
IL(off4)
Off State Output Current
VIN=VOUT=0V; VCC=13V; Tj =25°C
3
µA
Note: (**) Per device.
Table 6. Protection (see note 1)
Symbol
Parameter
TTSD
Min.
Typ.
Max.
Unit
Shut-down Temperature
150
175
200
°C
TR
Reset Temperature
135
Thyst
Thermal Hysteresis
7
tSDL
Status Delay in Overload
Conditions
Ilim
Current limitation
Vdemag
Turn-off Output Clamp
Voltage
Test Conditions
°C
15
Tj>TTSD
VCC=13V
6
9
5.5V < VCC < 36V
IOUT =2A; L= 6mH
VCC-41 VCC-48
°C
20
µs
15
A
15
A
VCC-55
V
Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be
used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration
and number of activation cycles
Table 7. VCC - Output Diode
Symbol
VF
4/20
Parameter
Forward on Voltage
Test Conditions
-IOUT=1.3A; Tj=150°C
Min
Typ
Max
0.6
Unit
V
VND830SP-E
ELECTRICAL CHARACTERISTICS (continued)
Table 8. Status Pin
Symbol
VSTAT
ILSTAT
CSTAT
VSCL
Parameter
Test Conditions
Status Low Output Voltage ISTAT = 1.6 mA
Status Leakage Current
Normal Operation; VSTAT= 5V
Status Pin Input
Normal Operation; VSTAT= 5V
Capacitance
ISTAT = 1mA
Status Clamp Voltage
ISTAT = - 1mA
Min
6
Typ
6.8
Max
0.5
10
Unit
V
µA
100
pF
8
-0.7
V
V
Table 9. Switching (V CC=13V)
Symbol
Parameter
td(on)
Turn-on Delay Time
td(off)
Turn-off Delay Time
Test Conditions
RL=6.5Ω from VIN rising edge to
VOUT=1.3V
RL=6.5Ω from VIN falling edge to
VOUT=11.7V
dVOUT /dt(on) Turn-on Voltage Slope
RL=6.5Ω from VOUT=1.3V to
VOUT=10.4V
dVOUT /dt(off) Turn-off Voltage Slope
RL=6.5Ω from VOUT=11.7V to
VOUT=1.3V
Min
Typ
Max
Unit
30
µs
30
µs
See
relative
diagram
See
relative
diagram
V/µs
V/µs
Table 10. Openload Detection
Symbol
IOL
tDOL(on)
VOL
TDOL(off)
Parameter
Openload ON State
Detection Threshold
Openload ON State
Detection Delay
Openload OFF State
Voltage Detection
Threshold
Openload Detection Delay
at Turn Off
Test Conditions
VIN=5V
Min
Typ
Max
Unit
50
100
200
mA
200
µs
3.5
V
1000
µs
Max
1.25
Unit
V
µA
V
µA
V
V
IOUT=0A
VIN=0V
1.5
2.5
Table 11. Logic Input
Symbol
VIL
IIL
VIH
IIH
VI(hyst)
VICL
Parameter
Input Low Level
Low Level Input Current
Input High Level
High Level Input Current
Input Hysteresis Voltage
Input Clamp Voltage
Test Conditions
VIN = 1.25V
Min
Typ
1
3.25
VIN = 3.25V
IIN = 1mA
IIN = -1mA
10
0.5
6
6.8
-0.7
8
V
5/20
VND830SP-E
Figure 5.
OPEN LOAD STATUS TIMING (with external pull-up)
VOUT > VOL
OVER TEMP STATUS TIMING
IOUT< IOL
Tj > TTSD
VINn
VINn
VSTATn
VSTATn
tSDL
tDOL(off)
tSDL
tDOL(on)
Table 12. Truth Table
CONDITIONS
INPUT
OUTPUT
SENSE
Normal Operation
L
H
L
H
H
H
Current Limitation
L
H
H
L
X
X
H
(Tj < TTSD) H
(Tj > TTSD) L
Overtemperature
L
H
L
L
H
L
Undervoltage
L
H
L
L
X
X
Overvoltage
L
H
L
L
H
H
Output Voltage > VOL
L
H
H
H
L
H
Output Current < IOL
L
H
L
H
H
L
6/20
VND830SP-E
Figure 6. Switching Time Waveforms
VOUTn
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
10%
t
VINn
td(on)
td(off)
t
Table 13. Electrical Transient Requirements On V CC Pin
ISO T/R 7637/1
Test Pulse
I
1
2
3a
3b
4
5
-25 V
+25 V
-25 V
+25 V
-4 V
+26.5 V
ISO T/R 7637/1
Test Pulse
1
2
3a
3b
4
5
CLASS
C
E
I
C
C
C
C
C
C
II
TEST LEVELS
III
IV
-50 V
+50 V
-50 V
+50 V
-5 V
+46.5 V
-75 V
+75 V
-100 V
+75 V
-6 V
+66.5 V
-100 V
+100 V
-150 V
+100 V
-7 V
+86.5 V
TEST LEVELS RESULTS
II
III
C
C
C
C
C
C
C
C
C
C
E
E
Delays and
Impedance
2 ms 10 Ω
0.2 ms 10 Ω
0.1 µs 50 Ω
0.1 µs 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
IV
C
C
C
C
C
E
CONTENTS
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device is not performed as designed after exposure and cannot be
returned to proper operation without replacing the device.
7/20
VND830SP-E
Figure 7. Waveforms
NORMAL OPERATION
INPUTn
OUTPUT VOLTAGEn
STATUSn
UNDERVOLTAGE
VUSDhyst
VCC
VUSD
INPUTn
OUTPUT VOLTAGEn
STATUSn
undefined
OVERVOLTAGE
VCC<VOV
VCC>VOV
VCC
INPUTn
OUTPUT VOLTAGEn
STATUSn
OPEN LOAD with external pull-up
INPUTn
VOUT >VOL
OUTPUT VOLTAGEn
VOL
STATUSn
OPEN LOAD without external pull-up
INPUTn
OUTPUT VOLTAGEn
STATUSn
OVERTEMPERATURE
Tj
TTSD
TR
INPUTn
OUTPUT CURRENTn
STATUSn
8/20
VND830SP-E
Figure 8. Application Schematic
+5V +5V
+5V
VCC
Rprot
STATUS1
Dld
µC
Rprot
INPUT1
OUTPUT1
Rprot
STATUS2
Rprot
INPUT2
OUTPUT2
GND
RGND
VGND
GND PROTECTION
REVERSE BATTERY
NETWORK
AGAINST
Solution 1: Resistor in the ground line (RGND only). This
can be used with any type of load.
The following is an indication on how to dimension the
RGND resistor.
1) RGND ≤ 600mV / IS(on)max.
2) RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can
be found in the absolute maximum rating section of the
device’s datasheet.
Power Dissipation in RGND (when VCC<0: during reverse
battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different
HSD. Please note that the value of this resistor should be
calculated with formula (1) where IS(on)max becomes the
sum of the maximum on-state currents of the different
devices.
Please note that if the microprocessor ground is not
common with the device ground then the RGND will
produce a shift (IS(on)max * RGND) in the input thresholds
and the status output values. This shift will vary
depending on how many devices are ON in the case of
several high side drivers sharing the same RGND.
If the calculated power dissipation leads to a large
resistor or several devices have to share the same
resistor then the ST suggests to utilize Solution 2 (see
below).
DGND
Solution 2: A diode (DGND) in the ground line.
A resistor (RGND=1kΩ) should be inserted in parallel to
DGND if the device will be driving an inductive load.
This small signal diode can be safely shared amongst
several different HSD. Also in this case, the presence of
the ground network will produce a shift (j600mV) in the
input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
shares the same diode/resistor network.
Series resistor in INPUT and STATUS lines are also
required to prevent that, during battery voltage transient,
the current exceeds the Absolute Maximum Rating.
Safest configuration for unused INPUT and STATUS pin
is to leave them unconnected.
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the
load dump peak voltage exceeds VCC max DC rating.
The same applies if the device will be subject to
transients on the VCC line that are greater than the ones
shown in the ISO T/R 7637/1 table.
9/20
VND830SP-E
µC I/Os PROTECTION:
supply the microprocessor.
The external resistor has to be selected according to the
following requirements:
1) no false open load indication when load is connected:
in this case we have to avoid VOUT to be higher than
VOlmin; this results in the following condition
VOUT=(VPU/(RL+RPU))RL<VOlmin.
2) no misdetection when load is disconnected: in this
case the VOUT has to be higher than VOLmax; this
results in the following condition RPU<(VPU–VOLmax)/
IL(off2).
Because Is(OFF) may significantly increase if Vout is
pulled high (up to several mA), the pull-up resistor RPU
should be connected to a supply that is switched OFF
when the module is in standby.
The values of VOLmin, VOLmax and IL(off2) are available in
If a ground protection network is used and negative
transient are present on the VCC line, the control pins will
be pulled negative. ST suggests to insert a resistor (Rprot)
in line to prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between
the leakage current of µC and the current required by the
HSD I/Os (Input levels compatibility) with the latch-up
limit of µC I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 65kΩ.
Recommended Rprot value is 10kΩ.
OPEN LOAD DETECTION IN OFF STATE
Off state open load detection requires an external pull-up
resistor (RPU) connected between OUTPUT pin and a
positive supply voltage (VPU) like the +5V line used to
the Electrical Characteristics section.
Figure 9. Open Load detection in off state
V batt.
VPU
VCC
RPU
INPUT
DRIVER
+
LOGIC
IL(off2)
OUT
+
R
STATUS
VOL
GROUND
10/20
RL
VND830SP-E
Figure 13. High Level Input Current
Figure 10. Off State Output Current
IL(off1) (uA)
Iih (uA)
2.5
5
2.25
4.5
Off state
Vcc=36V
Vin=Vout=0V
2
1.75
Vin=3.25V
4
3.5
1.5
3
1.25
2.5
1
2
0.75
1.5
0.5
1
0.25
0.5
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
125
150
175
125
150
175
Tc (°C)
Figure 14. Status Leakage Current
Figure 11. Input Clamp Voltage
Vicl (V)
Ilstat (uA)
8
0.05
7.8
Iin=1mA
7.6
0.04
7.4
Vstat=5V
7.2
0.03
7
6.8
0.02
6.6
6.4
0.01
6.2
6
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
Tc (°C)
Figure 12. Status Low Output Voltage
Figure 15. Status Clamp Voltage
Vstat (V)
Vscl (V)
0.8
8
7.8
0.7
Istat=1mA
Istat=1.6mA
7.6
0.6
7.4
0.5
7.2
0.4
7
6.8
0.3
6.6
0.2
6.4
0.1
6.2
0
6
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
-50
-25
0
25
50
75
100
Tc (°C)
11/20
VND830SP-E
Figure 16. On State Resistance Vs Tcase
Figure 19. On State Resistance Vs VCC
Ron (mOhm)
Ron (mOhm)
160
120
Tc=150°C
110
140
Iout=2A
Vcc=8V; 13V & 36V
120
100
90
80
100
70
60
80
Tc=25°C
50
60
40
40
Tc= - 40°C
30
20
Iout=5A
20
10
0
0
-50
-25
0
25
50
75
100
125
150
175
5
10
15
20
Tc (°C)
Figure 17. Openload On State Detection
Threshold
30
35
40
Figure 20. Openload Off State Detection
Threshold
Iol (mA)
Vol (V)
150
5
140
4.5
Vin=0V
Vcc=13V
Vin=5V
130
4
120
3.5
110
3
100
2.5
90
2
80
1.5
70
1
60
0.5
0
50
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
Tc (ºC)
50
75
100
125
150
175
100
125
150
175
Tc (°C)
Figure 18. Input High Level
Figure 21. Input Low Level
Vih (V)
Vil (V)
3.6
2.6
3.4
2.4
3.2
2.2
3
2
2.8
1.8
2.6
1.6
2.4
1.4
2.2
1.2
2
1
-50
-25
0
25
50
75
Tc (°C)
12/20
25
Vcc (V)
100
125
150
175
-50
-25
0
25
50
75
Tc (°C)
VND830SP-E
Figure 22. Input Hysteresis Voltage
Figure 25. Overvoltage Shutdown
Vhyst (V)
Vov (V)
1.5
50
1.4
48
1.3
46
1.2
44
1.1
42
1
40
0.9
38
0.8
36
0.7
34
0.6
32
0.5
30
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
100
125
150
175
150
175
Figure 26. Turn-off Voltage Slope
dVout/dt(on) (V/ms)
dVout/dt(off) (V/ms)
800
600
550
Vcc=13V
Rl=6.5Ohm
600
75
Tc (°C)
Figure 23. Turn-on Voltage Slope
700
50
Vcc=13V
Rl=6.5Ohm
500
500
450
400
400
300
350
200
300
100
250
0
200
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
-50
-25
0
25
50
75
100
125
Tc (ºC)
Figure 24. ILIM Vs Tcase
Ilim (A)
20
18
Vcc=13V
16
14
12
10
8
6
4
2
0
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
13/20
VND830SP-E
Figure 27. Maximum turn off current versus load inductance
ILMAX (A)
100
10
A
B
C
1
0.1
1
10
100
L(mH )
A = Single Pulse at TJstart=150ºC
B= Repetitive pulse at T Jstart=100ºC
C= Repetitive Pulse at T Jstart=125ºC
Conditions:
VCC=13.5V
Values are generated with R L=0Ω
In case of repetitive pulses, Tjstart (at beginning of
each demagnetization) of every pulse must not
exceed the temperature specified above for
curves B and C.
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
14/20
VND830SP-E
PowerSO-10™ Thermal Data
Figure 28. PowerSO-10™ PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm,
Cu thickness=35µm, Copper areas: from minimum pad lay-out to 8cm2).
Figure 29. Rthj-amb Vs PCB copper area in open box free air condition
RTHj_amb (°C/W)
55
Tj-Tamb=50°C
50
45
40
35
30
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
15/20
VND830SP-E
Figure 30. PowerSO-10 Thermal Impedance Junction Ambient Single Pulse
ZTH (°C/W)
1000
100
Footprint
6 cm2
10
1
0.1
0.01
0.0001
0.001
0.01
0.1
1
Time (s)
Figure 31. Thermal fitting model of a double
channel HSD in PowerSO-10
10
100
1000
Pulse calculation formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where
δ = tp ⁄ T
Table 14. Thermal Parameter
Tj_1
C1
C2
C3
C4
C5
C6
R1
R2
R3
R4
R5
R6
Pd1
Tj_2
C1
C2
R1
R2
Pd2
T_amb
16/20
Area/island (cm2)
R1 (°C/W)
R2 (°C/W)
R3( °C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
Footprint
0.05
0.3
0.3
0.8
12
37
0.001
5.00E-03
0.02
0.3
0.75
3
6
22
5
VND830SP-E
PACKAGE MECHANICAL
Table 15. PowerSO-10™ Mechanical Data
millimeters
Symbol
Min
A
A (*)
A1
B
B (*)
C
C (*)
D
D1
E
E2
E2 (*)
E4
E4 (*)
e
F
F (*)
H
H (*)
h
L
L (*)
a
α (*)
Typ
Max
3.35
3.4
0.00
0.40
0.37
0.35
0.23
9.40
7.40
9.30
7.20
7.30
5.90
5.90
3.65
3.6
0.10
0.60
0.53
0.55
0.32
9.60
7.60
9.50
7.60
7.50
6.10
6.30
1.27
1.25
1.20
13.80
13.85
1.35
1.40
14.40
14.35
0.50
1.20
0.80
0º
2º
1.80
1.10
8º
8º
Note: (*) Muar only POA P013P
Figure 32. PowerSO-10™ Package Dimensions
B
0.10 A B
10
H
E
E2
E4
1
SEATING
PLANE
e
B
DETAIL "A"
h
A
C
0.25
D
= D1 =
=
=
SEATING
PLANE
A
F
A1
A1
L
DETAIL "A"
α
P095A
17/20
VND830SP-E
Figure 33. PowerSO-10™ Suggested Pad Layout And Tube Shipment (No Suffix)
CASABLANCA
14.6 - 14.9
MUAR
B
10.8 - 11
C
6.30
C
A
A
B
0.67 - 0.73
1
9.5
2
3
4
5
10
9
8
7
6
0.54 - 0.6
All dimensions are in mm.
1.27
Base Q.ty Bulk Q.ty Tube length (± 0.5)
A
B
C (± 0.1)
Casablanca
50
1000
532
10.4 16.4
0.8
Muar
50
1000
532
4.9 17.2
0.8
Figure 34. Tape And Reel Shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
600
600
330
1.5
13
20.2
24.4
60
30.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
24
4
24
1.5
1.5
11.5
6.5
2
End
All dimensions are in mm.
Start
Top
No components
Components
No components
cover
tape
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
18/20
500mm min
VND830SP-E
REVISION HISTORY
Date
Oct. 2004
Revision
1
- First Issue.
Description of Changes
19/20
VND830SP-E
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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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20/20