VN610SP-E SINGLE CHANNEL HIGH SIDE DRIVER Table 1. General Features Type VN610SP-E ■ OUTPUT Figure 1. Package RDS(on) Iout VCC 10 mΩ 45 A 36 V CURRENT: 45 A CMOS COMPATIBLE INPUT ■ PROPORTIONAL LOAD CURRENT SENSE ■ ■ UNDERVOLTAGE AND OVERVOLTAGEn SHUT-DOWN ■ OVERVOLTAGE CLAMP 10 1 THERMAL SHUT DOWN ■ CURRENT LIMITATION ■ VERY LOW STAND-BY POWER DISSIPATION ■ PROTECTION AGAINST: n LOSS OF GROUND AND LOSS OF VCC ■ REVERSE BATTERY PROTECTION (*) ■ IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE ■ PowerSO-10™ DESCRIPTION The VN610SP-E is a monolithic device made using STMicroelectronics VIPower M0-3 technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active V CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio). Active current limitation combined with thermal shut-down and automatic restart protect the device against overload. Device automatically turns off in case of ground pin disconnection. Table 2. Order Codes Package PowerSO-10™ Tube VN610SP-E Tape and Reel VN610SPTR-E Note: (*) See application schematic at page 9 Rev. 1 October 2004 1/18 VN610SP-E Figure 2. Block Diagram VCC OVERVOLTAGE VCC CLAMP UNDERVOLTAGE PwCLAMP DRIVER OUTPUT GND ILIM VDSLIM LOGIC IOUT INPUT CURRENT SENSE K OVERTEMP. Table 3. Absolute Maximum Ratings Symbol Parameter Value Unit 41 V VCC DC supply voltage -VCC Reverse DC supply voltage -0.3 V - IGND DC reverse ground pin current -200 mA Internally limited A -50 A +/- 10 mA IOUT - IOUT IIN DC output current Reverse DC output current DC input current -3 V +15 V 4000 V 2000 V 5000 V 5000 V (L=0.05mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IL=75A) 193 mJ Ptot Power dissipation at TC<25°C 139 W Tj Junction operating temperature Internally limited °C Tc Case operating temperature -40 to 150 °C Storage temperature -55 to 150 °C VCSENSE Current sense maximum voltage Electrostatic Discharge (Human Body Model: R=1.5KΩ; C=100pF) VESD - INPUT - CURRENT SENSE - OUTPUT - VCC Maximum Switching Energy EMAX TSTG 2/18 VN610SP-E Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins GROUND INPUT C.SENSE N.C. N.C. 6 7 8 9 5 4 3 10 1 OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT 2 11 VCC Connection / Pin Floating Current Sense N.C. X Through 1KΩresistor To Ground Output X Input X X Through 10KΩ resistor Figure 4. Current and Voltage Conventions IS VCC VF VCC IOUT OUTPUT IIN VOUT INPUT VIN ISENSE CURRENT SENSE VSENSE GND IGND Table 4. Thermal Data Symbol Rthj-case Parameter Thermal resistance junction-case (MAX) Rthj-amb Thermal resistance junction-ambient (MAX) Value 0.9 50.9 (1) 36(2) Unit °C/W °C/W °C/W Note: (1) When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35µm thick). Note: (2) When mounted on a standard single-sided FR-4 board with 6 cm 2 of Cu (at least 35µm thick). 3/18 VN610SP-E ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C<Tj<150°C; unless otherwise specified) (Per each channel) Table 5. Power Symbol Parameter VCC Min. Typ. Max. Unit Operating supply voltage 5.5 13 36 V VUSD Undervoltage shutdown 3 4 5.5 V VOV Overvoltage shutdown RON Vclamp On state resistance Test Conditions (See Note 1) 36 IOUT=15A; Tj=25°C 10 mΩ IOUT=15A; Tj=150°C 20 mΩ IOUT=9A; VCC=6V 35 mΩ 48 55 V 10 25 µA 10 20 µA 5 mA 0 50 µA -75 0 µA Clamp Voltage ICC=20 mA (see note 1) Supply current Off State; VCC=13V; VIN=VOUT=0V; Tj=25°C 41 Off State; VCC=13V; VIN=VOUT=0V IS V On State; VCC=13V; VIN=5V; IOUT=0A RSENSE=3.9K IL(off1) Off State Output Current VIN=VOUT=0V IL(off2) Off State Output Current VIN=0V; VOUT =3.5V IL(off3) Off State Output Current VIN=VOUT=0V; VCC=13V; Tj =125°C 5 µA IL(off4) Off State Output Current VIN=VOUT=0V; VCC=13V; Tj =25°C 3 µA Max. Unit Note: 1. Vclamp and VOV are correlated. Typical difference is 5V. Table 6. Protection (see note 2) Symbol Ilim TTSD TR THYST VDEMAG VON Parameter DC Short circuit current Test Conditions VCC=13V 45 75 150 temperature Thermal reset temperature 175 120 A 120 A 200 °C 135 Thermal hysteresis Output voltage drop limitation Typ. 5.5V<VCC<36V Thermal shutdown Turn-off output voltage clamp Min. IOUT =2A; VIN=0; L=6mH °C 7 15 VCC-41 VCC-48 IOUT =1.5A; Tj= -40°C...+150°C °C VCC-55 50 V mV Note: 2. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles Table 7. VCC - Output Diode Symbol VF 4/18 Parameter Forward on Voltage Test Conditions -IOUT=8A; Tj=150°C Min Typ Max 0.6 Unit V VN610SP-E ELECTRICAL CHARACTERISTICS (continued) Table 8. Current Sense (9V≤VCC≤16V) (See Figure 5) Symbol K1 dK1/K1 K2 dK2/K2 K3 dK3/K3 Parameter IOUT /ISENSE Current Sense Ratio Drift IOUT /ISENSE Current Sense Ratio Drift IOUT /ISENSE Current Sense Ratio Drift Test Conditions IOUT =1.5A; VSENSE=0.5V; Tj= -40°C...150°C IOUT =1.5A; VSENSE=0.5V; Tj= -40°C...150°C IOUT =15A; VSENSE=4V; Tj=-40°C Tj=25°C...150°C IOUT =15A; VSENSE=4V; Tj=-40°C Tj=25°C...150°C IOUT =45A; VSENSE=4V; Tj=-40°C Tj=25°C...150°C IOUT =45A; VSENSE=4V; Tj=-40°C Tj=25°C...150°C Min Typ Max 3300 4400 6000 -10 +10 4200 4900 6000 4400 4900 5750 -6 +6 4200 4900 5500 4400 4900 5250 -6 Unit % % +6 % Vcc=6...16V; IOUT=0A; VSENSE=0V; Tj=40°C...150°C ISENSE0 VSENSE VSENSEH Analog sense current Off State; VIN=0V 0 5 µA On State; VIN=5V 0 3.5 10 µA V Max analog sense VCC=5.5V; IOUT =7.5A; RSENSE=10KΩ output voltage VCC >8V; IOUT=15A; RSENSE=10KΩ 5 Analog sense output voltage in overtemperature VCC=13V; RSENSE=3.9KΩ condition Analog sense output RVSENSEH impedance in overtemperature condition Current sense delay tDSENSE reponse VCC=13V; Tj>TTSD; Output Open V 5.5 V 400 Ω to 90% ISENSE (see note 3) 500 µs Max Unit µs µs Note: 3. Current sense signal delay after positive input slope. Table 9. Switching (V CC=13V) Symbol td(on) td(off) Parameter Turn-on delay time Turn-off delay time (dVOUT/dt)on Turn-on voltage slope Test Conditions RL=0.87Ω RL=0.87Ω RL=0.87Ω Min Typ 50 50 See relative V/µs diagram See (dVOUT/dt)off Turn-off voltage slope RL=0.87Ω relative V/µs diagram 5/18 VN610SP-E Table 10. Logic Input Symbol VIL IIL VIH IIH VI(hyst) VICL Parameter Test Conditions Input low level voltage Low level input current VIN=1.25V Input high level voltage High level input current VIN=3.25V Input hysteresis voltage IIN=1mA Input clamp voltage IIN=-1mA Min Typ Max 1.25 1 3.25 10 0.5 6 6.8 8 Unit V µA V µA V V -0.7 V Figure 5. IOUT/ISENSE 6500 6000 max.Tj=-40°C 5500 max.Tj=25...150°C 5000 min.Tj=25...150°C typical value 4500 4000 min.Tj=-40°C 3500 3000 0 5 10 15 20 25 30 35 40 45 50 IOUT Table 11. Truth Table CONDITIONS Normal operation Overtemperature Undervoltage Overvoltage Short circuit to GND Short circuit to VCC Negative output voltage clamp 6/18 INPUT OUTPUT SENSE L L H H 0 Nominal L L 0 H L VSENSEH L L 0 H L 0 L L 0 H L 0 L L 0 H L (Tj<TTSD) 0 H L (Tj>TTSD) VSENSEH L H 0 H H < Nominal L L 0 VN610SP-E Figure 6. Switching Characteristics (Resistive load RL=0.87Ω) VOUT 90% 80% dVOUT/dt(off) dVOUT/dt(on) 10% tr tf t ISENSE 90% t tDSENSE INPUT td(on) td(off) t Table 12. Electrical Transient Requirements On V CC Pin ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E I II TEST LEVELS III IV -25 V +25 V -25 V +25 V -4 V +26.5 V -50 V +50 V -50 V +50 V -5 V +46.5 V -75 V +75 V -100 V +75 V -6 V +66.5 V -100 V +100 V -150 V +100 V -7 V +86.5 V I C C C C C C TEST LEVELS RESULTS II III C C C C C C C C C C E E Delays and Impedance 2 ms 10 Ω 0.2 ms 10 Ω 0.1 µs 50 Ω 0.1 µs 50 Ω 100 ms, 0.01 Ω 400 ms, 2 Ω IV C C C C C E CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 7/18 VN610SP-E Figure 7. Waveforms NORMAL OPERATION INPUT LOAD CURRENT SENSE CURRENT UNDERVOLTAGE VCC VUSDhyst VUSD INPUT LOAD CURRENT SENSE CURRENT OVERVOLTAGE VOV VCC VOVhyst VCC > VUSD INPUT LOAD CURRENT SENSE SHORT TO GROUND INPUT LOAD CURRENT LOAD VOLTAGE SENSE CURRENT SHORT TO VCC INPUT LOAD VOLTAGE LOAD CURRENT SENSE CURRENT <Nominal <Nominal OVERTEMPERATURE Tj TTSD TR INPUT LOAD CURRENT SENSE CURRENT ISENSE=V SENSEH/(RSENSE+RSENSEH ) 8/18 VN610SP-E Figure 8. Application Schematic +5V VCC Rprot INPUT Dld µC Rprot OUTPUT CURRENT SENSE RSENSE GND VGND GND PROTECTION REVERSE BATTERY NETWORK AGAINST Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND ≤ 600mV / (IS(on)max). 2) RGND ≥ (−VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device’s datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggests to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device will be driving an inductive load. RGND DGND This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT line is also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT pin is to leave it unconnected, while unused SENSE pin has to be connected to Ground pin. LOAD DUMP PROTECTION Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table. µC I/Os PROTECTION: If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the µC I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os. -VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V 5kΩ ≤ Rprot ≤ 65kΩ. Recommended Rprot value is 10kΩ. 9/18 VN610SP-E Figure 9. Off State Output Current Figure 10. High Level Input Current Iih (uA) IL(off1) (µA) 9 5 4.5 8 Vin=3.25V Off state Vcc=36V Vin=Vout=0V 7 4 3.5 6 3 5 2.5 4 2 3 1.5 2 1 1 0.5 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 Figure 11. Input Low Level 75 100 125 150 175 100 125 150 175 150 175 Figure 13. Input High Level Vil (V) Vih (V) 2.6 3.6 2.4 3.4 2.2 3.2 2 3 1.8 2.8 1.6 2.6 1.4 2.4 1.2 2.2 1 2 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (°C) 50 75 Tc (°C) Figure 12. Input Clamp Voltage Figure 14. Input Hysteresis Voltage Vhyst (V) Vicl (V) 1.5 8 1.4 7.8 Iin=1mA 7.6 1.3 7.4 1.2 7.2 1.1 7 1 6.8 0.9 6.6 0.8 6.4 0.7 6.2 0.6 0.5 6 -50 -25 0 25 50 75 Tc (°C) 10/18 50 Tc (°C) Tc (°C) 100 125 150 175 -50 -25 0 25 50 75 Tc (°C) 100 125 VN610SP-E Figure 15. Overvoltage Shutdown Figure 18. ILIM Vs Tcase Vov (V) Ilim (A) 50 160 48 140 Vcc=13V 46 120 44 100 42 40 80 38 60 36 40 34 20 32 30 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (°C) 100 125 150 175 150 175 Figure 19. Turn-off Voltage Slope dVout/dt(on) (V/ms) dVout/dt(off) (V/ms) 700 900 800 Vcc=13V Rl=0.87Ohm 600 75 Tc (ºC) Figure 16. Turn-on Voltage Slope 650 50 Vcc=13V Rl=0.87Ohm 700 550 600 500 500 450 400 400 300 350 200 300 100 250 -50 -25 0 25 50 75 100 125 150 175 0 -50 Tc (ºC) Figure 17. On State Resistance Vs Tcase -25 0 25 50 75 100 125 Figure 20. On State Resistance Vs VCC Ron (mOhm) Ron (mOhm) 25 25 22.5 22.5 Iout=15A Iout=15A Vcc=8V; 36V 20 20 Tc= 125ºC 17.5 17.5 15 15 12.5 12.5 10 10 7.5 7.5 5 5 2.5 2.5 0 Tc= 25ºC Tc= - 40ºC 0 -50 -25 0 25 50 75 Tc (ºC) 100 125 150 175 5 10 15 20 25 30 35 40 Vcc (V) 11/18 VN610SP-E Figure 21. Maximum turn off current versus load inductance ILMAX (A) 1000 100 A C 10 1 0.01 0.1 A = Single Pulse at TJstart=150ºC B= Repetitive pulse at T Jstart=100ºC C= Repetitive Pulse at T Jstart=125ºC Conditions: VCC=13.5V B 1 L(mH ) 10 100 Values are generated with R L=0Ω In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. VIN, IL Demagnetization Demagnetization Demagnetization t 12/18 VN610SP-E PowerSO-10™ Thermal Data Figure 22. PowerSO-10™ PC Board Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35µm, Copper areas: from minimum pad lay-out to 8cm2). Figure 23. Rthj-amb Vs PCB copper area in open box free air condition RTHj_amb (°C/W) 55 Tj-Tamb=50°C 50 45 40 35 30 0 2 4 6 8 10 PCB Cu heatsink area (cm^2) 13/18 VN610SP-E Figure 24. PowerSO-10 Thermal Impedance Junction Ambient Single Pulse ZTH (°C/W) 100 Footprint 6 cm2 10 1 0.1 0.01 0.0001 0.0 01 0.01 0.1 1 Time (s) Figure 25. Thermal fitting model of a double channel HSD in PowerSO-10 10 100 1000 Pulse calculation formula Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ ) where δ = tp ⁄ T Table 13. Thermal Parameter Tj_1 C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 Pd1 Tj_2 C1 C2 R1 R2 Pd2 T_amb 14/18 Area/island (cm2) R1 (°C/W) R2 (°C/W) R3( °C/W) R4 (°C/W) R5 (°C/W) R6 (°C/W) C1 (W.s/°C) C2 (W.s/°C) C3 (W.s/°C) C4 (W.s/°C) C5 (W.s/°C) C6 (W.s/°C) Footprint 0.05 0.3 0.3 0.8 12 37 0.001 5.00E-03 0.02 0.3 0.75 3 6 22 5 VN610SP-E PACKAGE MECHANICAL Table 14. PowerSO-10™ Mechanical Data millimeters Symbol Min A A (*) A1 B B (*) C C (*) D D1 E E2 E2 (*) E4 E4 (*) e F F (*) H H (*) h L L (*) a α (*) Typ Max 3.35 3.4 0.00 0.40 0.37 0.35 0.23 9.40 7.40 9.30 7.20 7.30 5.90 5.90 3.65 3.6 0.10 0.60 0.53 0.55 0.32 9.60 7.60 9.50 7.60 7.50 6.10 6.30 1.27 1.25 1.20 13.80 13.85 1.35 1.40 14.40 14.35 0.50 1.20 0.80 0º 2º 1.80 1.10 8º 8º Note: (*) Muar only POA P013P Figure 26. PowerSO-10™ Package Dimensions B 0.10 A B 10 H E E2 E4 1 SEATING PLANE e B DETAIL "A" h A C 0.25 D = D1 = = = SEATING PLANE A F A1 A1 L DETAIL "A" α P095A 15/18 VN610SP-E Figure 27. PowerSO-10™ Suggested Pad Layout and Tube Shipment (no suffix) CASABLANCA 14.6 - 14.9 MUAR B 10.8 - 11 C 6.30 C A A B 0.67 - 0.73 1 9.5 2 3 4 5 10 9 8 7 6 0.54 - 0.6 All dimensions are in mm. 1.27 Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) Casablanca 50 1000 532 10.4 16.4 0.8 Muar 50 1000 532 4.9 17.2 0.8 Figure 28. Tape And Reel Shipment (suffix “TR”) REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (± 0.1) P D (± 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) 24 4 24 1.5 1.5 11.5 6.5 2 End All dimensions are in mm. Start Top No components Components No components cover tape 500mm min Empty components pockets saled with cover tape. User direction of feed 16/18 500mm min VN610SP-E REVISION HISTORY Date Oct. 2004 Revision 1 - First Issue. Description of Changes 17/18 VN610SP-E Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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