VN920SP-E HIGH SIDE DRIVER Table 1. General Features Type VN920SP-E Figure 1. Package RDS(on) IOUT VCC 15mΩ 30 A 36 V CMOS COMPATIBLE INPUT PROPORTIONAL LOAD CURRENT SENSE ■ SHORTED LOAD PROTECTION ■ UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN ■ OVERVOLTAGE CLAMP ■ THERMAL SHUTDOWN ■ CURRENT LIMITATION ■ ■ 10 1 PowerSO-10™ PROTECTION AGAINST LOSS OF GROUND AND LOSS VCC ■ VERY LOW STAND-BY POWER DISSIPATION ■ Active current limitation combined with thermal shutdown and automatic restart protect the device against overload. The device integrates an analog current sense output which delivers a current proportional to the load current. Device automatically turns off in case of ground pin disconnection. REVERSE BATTERY PROTECTION (*) ■ IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE ■ DESCRIPTION The VN920SP-E is a monolithic device designed in STMicroelectronics VIPower M0-3 Technology, intended for driving any kind of load with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Table 2. Order Codes Package PowerSO-10 Tube VN920SP-E Tape and Reel VN920SPTR-E Note: (*) See application schematic at page 9. Rev. 1 October 2004 1/18 VN920SP-E Figure 2. Block Diagram VCC OVERVOLTAGE DETECTION VCC CLAMP UNDERVOLTAGE DETECTION GND Power CLAMP DRIVER OUTPUT LOGIC INPUT CURRENT LIMITER VDS LIMITER IOUT CURRENT SENSE K OVERTEMPERATURE DETECTION Table 3. Absolute Maximum Ratings Symbol VCC - VCC - IGND IOUT - IOUT IIN VCSENSE Parameter DC Supply Voltage Reverse DC Supply Voltage DC Reverse Ground Pin Current DC Output Current Reverse DC Output Current DC Input Current Current Sense Maximum Voltage Value 41 - 0.3 - 200 Internally Limited - 40 +/- 10 -3 Unit V V mA A A mA V +15 V - INPUT 4000 V - CURRENT SENSE 2000 V - OUTPUT 5000 V - VCC Maximum Switching Energy 5000 V 362 mJ 96.1 Internally limited - 40 to 150 - 55 to 150 W °C °C °C Electrostatic Discharge (Human Body Model: R=1.5KΩ; C=100pF) VESD EMAX Ptot Tj Tc TSTG 2/18 (L=0.25mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IL=45A) Power Dissipation TC≤25°C Junction Operating Temperature Case Operating Temperature Storage Temperature VN920SP-E Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins GROUND INPUT C.SENSE N.C. N.C. 6 7 8 9 5 4 3 10 1 OUTPUT OUTPUT N.C. OUTPUT OUTPUT 2 11 VCC Connection / Pin Current Sense Floating To Ground Through 1KΩ resistor N.C. X X Output X Input X Through 10KΩ resistor Figure 4. Current and Voltage Conventions IS VCC VF VCC IOUT OUTPUT IIN VOUT INPUT VIN ISENSE CURRENT SENSE VSENSE GND IGND Table 4. Thermal Data Symbol Rthj-case Rthj-amb (1) (2) Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max Max Value 1.3 51.3 (1) 37 (2) Unit °C/W °C/W When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35µm thick). When mounted on a standard single-sided FR-4 board with 6 cm2 of Cu (at least 35µm thick). 3/18 VN920SP-E ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C<Tj<150°C unless otherwise specified) Table 5. Power Symbol VCC VUSD VOV RON Vclamp IS IL(off1) IL(off2) IL(off3) IL(off4) Parameter Operating Supply Voltage Undervoltage Shut-down Overvoltage Shut-down IOUT=10A; Tj =25°C 15 Unit V V V mΩ IOUT=10A 30 mΩ Clamp Voltage IOUT=3A; VCC=6V ICC=20mA (See note 1) Off State; VCC=13V; VIN=VOUT=0V 48 50 55 mΩ V 10 25 µA Supply Current Off State; VCC=13V; Tj=25°C; VIN=VOUT=0V 10 20 µA 5 mA 50 0 5 3 µA µA µA µA Typ 50 50 See relative diagram See relative diagram Max Unit µs µs Typ Max Unit 1.25 V On State Resistance Off Off Off Off State State State State Output Current Output Current Output Current Output Current Test Conditions On State; VCC=13V; VIN=5V; IOUT=0; RSENSE=3.9KΩ VIN=VOUT=0V VIN=0V; VOUT=3.5V VIN=VOUT=0V; VCC=13V; Tj =125°C VIN=VOUT=0V; VCC=13V; Tj =25°C Min 5.5 3 36 41 Typ 13 4 0 -75 Max 36 5.5 Note: 1. Vclamp and VOV are correlated. Typical difference is 5V. Table 6. Switching (VCC =13V) Symbol td(on) td(off) Parameter Turn-on Delay Time Turn-off Delay Time Test Conditions RL=1.3Ω (see figure 2) RL=1.3Ω (see figure 2) dVOUT/ dt(on) Turn-on Voltage Slope RL=1.3Ω (see figure 2) dVOUT/ dt(off) Turn-off Voltage Slope RL=1.3Ω (see figure 2) Min V/µs V/µs Table 7. Logic Input Symbol Parameter VIL Input Low Level IIL Low Level Input Current VIH Input High Level IIH High Level Input Current VI(hyst) Input Hysteresis Voltage VICL 4/18 Input Clamp Voltage Test Conditions VIN=1.25V Min 1 µA 3.25 V VIN=3.25V 10 0.5 IIN=1mA IIN=-1mA 6 µA V 6.8 -0.7 8 V V VN920SP-E ELECTRICAL CHARACTERISTICS (continued) Table 8. VCC - Output Diode Symbol VF Parameter Forward on Voltage Test Conditions Min. Typ. -IOUT=5.3A; Tj=150°C Max. Unit 0.6 V Max 200 Table 9. Protections (see note 2) Symbol TTSD TR Thyst Parameter Shut-down Temperature Reset Temperature Thermal Hysteresis Ilim DC Short Circuit Current Vdemag VON Turn-off Output Clamp Voltage Output Voltage Drop Limitation Test Conditions VCC=13V Min 150 135 7 30 Typ 175 15 45 5V<VCC<36V IOUT=2A; VIN=0V; L=6mH VCC-41 IOUT=1A; Tj=-40°C....+150°C VCC-48 75 Unit °C °C °C A 75 A VCC-55 V 50 mV Note: 2. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. Table 10. Current Sense (9V≤VCC≤16V) (See Fig. 5) Symbol K1 dK1/K1 K2 dK2/K2 K3 dK3/K3 ISENSEO VSENSE VSENSEH RVSENSEH tDSENSE Parameter IOUT/ISENSE Current Sense Ratio Drift IOUT/ISENSE Current Sense Ratio Drift IOUT/ISENSE Current Sense Ratio Drift Analog Sense Leakage Current Test Conditions IOUT=1A; VSENSE=0.5V; Tj= -40°C...150°C IOUT=1A; VSENSE=0.5V; Tj= -40°C...+150°C IOUT=10A; VSENSE=4V; Tj=-40°C Tj=25°C...150°C IOUT=10A; VSENSE=4V; Tj=-40°C...+150°C IOUT=30A; VSENSE=4V; Tj=-40°C Tj=25°C...150°C IOUT=30A; VSENSE=4V; Tj=-40°C...+150°C VCC=6...16V; IOUT=0A;VSENSE=0V; Tj=-40°C...+150°C Max Analog Sense Output VCC=5.5V; IOUT=5A; RSENSE=10KΩ Voltage VCC>8V; IOUT=10A; RSENSE=10KΩ Sense Voltage in Overtemperature VCC=13V; RSENSE=3.9KΩ conditions Analog sense output impedance in VCC=13V; Tj>TTSD; Output Open overtemperature condition Current sense delay to 90% ISENSE (see note 3) response Min Typ Max 3300 4400 6000 -10 +10 4200 4900 6000 4400 4900 5750 -8 +8 4200 4900 5500 4400 4900 5250 Unit % % -6 +6 % 0 10 µA 2 V 4 V 5.5 V 400 Ω 500 µs Note: 3. Current sense signal delay after positive input slope 5/18 VN920SP-E Figure 5. IOUT/ISENSE versus IOUT IOUT/ISENSE 6500 6000 max.Tj=-40°C 5500 max.Tj=25...150°C 5000 typical value min.Tj=25...150°C 4500 min.Tj=-40°C 4000 3500 3000 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 IOUT (A) Figure 6. Switching Characteristics (Resistive load RL=1.3Ω) VOUT 90% 80% dVOUT/dt(off) dVOUT/dt(on) tr 10% tf t ISENSE 90% INPUT t tDSENSE td(on) td(off) t 6/18 32 VN920SP-E Table 11. Truth Table CONDITIONS Normal operation Overtemperature Undervoltage Overvoltage Short circuit to GND Short circuit to VCC Negative output voltage clamp INPUT OUTPUT SENSE L L H L H L 0 Nominal H L L L VSENSEH 0 H L L L 0 0 H L L L 0 0 H L (Tj<TTSD) 0 H L L H (Tj>TTSD) VSENSEH 0 H L H L 0 < Nominal 0 Table 12. Electrical Transient Requirements On VCC Pin TEST LEVELS ISO T/R 7637/1 Test Pulse I II III IV 1 2 3a 3b 4 5 -25 V +25 V -25 V +25 V -4 V +26.5 V -50 V +50 V -50 V +50 V -5 V +46.5 V -75 V +75 V -100 V +75 V -6 V +66.5 V -100 V +100 V -150 V +100 V -7 V +86.5 V ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E Delays and Impedance 2 ms 10 Ω 0.2 ms 10 Ω 0.1 µs 50 Ω 0.1 µs 50 Ω 100 ms, 0.01 Ω 400 ms, 2 Ω I TEST LEVELS RESULTS II III IV C C C C C C C C C C C E C C C C C E C C C C C E CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 7/18 VN920SP-E Figure 7. Waveforms NORMAL OPERATION INPUT LOAD CURRENT SENSE UNDERVOLTAGE VCC VUSDhyst VUSD INPUT LOAD CURRENT SENSE OVERVOLTAGE VOV VCC VCC > VUSD VOVhyst INPUT LOAD CURRENT SENSE SHORT TO GROUND INPUT LOAD CURRENT LOAD VOLTAGE SENSE SHORT TO VCC INPUT LOAD VOLTAGE LOAD CURRENT SENSE <Nominal <Nominal OVERTEMPERATURE Tj TTSD TR INPUT LOAD CURRENT SENSE 8/18 ISENSE= VSENSEH RSENSE VN920SP-E Figure 8. Application Schematic +5V VCC Rprot INPUT Dld µC Rprot OUTPUT CURRENT SENSE RSENSE GND VGND GND PROTECTION REVERSE BATTERY NETWORK AGAINST Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND ≤ 600mV / (IS(on)max). 2) RGND ≥ (−VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device’s datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggests to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device will be driving an inductive load. RGND DGND This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT line is also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT pin is to leave it unconnected, while unused SENSE pin has to be connected to Ground pin. LOAD DUMP PROTECTION Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table. µC I/Os PROTECTION: If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the µC I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os. -VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V 5kΩ ≤ Rprot ≤ 65kΩ. Recommended Rprot value is 10kΩ. 9/18 VN920SP-E Figure 9. Off State Output Current Figure 10. High Level Input Current Iih (uA) IL(off1) (uA) 9 5 8 4.5 Vin=3.25V 4 7 3.5 6 3 5 2.5 4 2 3 1.5 2 1 1 0.5 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 11. Input Clamp Voltage Figure 13. On State Resistance Vs VCC Ron (mOhm) Vicl (V) 30 8 Tc= 150ºC 27.5 7.8 Iin=1mA 25 7.6 22.5 7.4 20 7.2 17.5 7 15 Tc= 25ºC 12.5 6.8 Tc= - 40ºC 10 6.6 7.5 6.4 5 6.2 IOUT=10A 2.5 0 6 -50 -25 0 25 50 75 100 125 150 5 175 10 15 20 25 30 35 40 Vcc (V) Tc (°C) Figure 14. Input High Level Figure 12. On State Resistance Vs Tcase Vih (V) Ron (mOhm) 3.6 30 27.5 3.4 Iout=10A 25 Vcc=8V; 36V 3.2 22.5 3 20 17.5 2.8 15 2.6 12.5 2.4 10 2.2 7.5 2 5 -25 0 25 50 75 Tc (ºC) 10/18 100 125 150 175 -50 -25 0 25 50 75 Tc (°C) 100 125 150 175 VN920SP-E Figure 15. Input Low Level Figure 18. Input Hysteresis Voltage Vil (V) Vhyst (V) 2.6 1.5 1.4 2.4 1.3 2.2 1.2 2 1.1 1 1.8 0.9 1.6 0.8 1.4 0.7 1.2 0.6 1 0.5 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (°C) 50 75 100 125 150 175 Tc (°C) Figure 16. Turn-on Voltage Slope Figure 19. Turn-off Voltage Slope dVout/dt(on) (V/ms) dVout/dt(off) (V/ms) 700 550 500 650 Vcc=13V Rl=1.3Ohm 450 Vcc=13V Rl=1.3Ohm 600 400 550 350 500 300 450 250 200 400 150 350 100 300 50 0 250 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 100 125 150 175 Tc (°C) Tc (ºC) Figure 17. Overvoltage Shutdown Figure 20. ILIM Vs Tcase Vov (V) Ilim (A) 50 100 48 90 46 80 44 70 42 60 40 50 38 40 36 30 34 20 32 10 Vcc=13V 30 0 -50 -25 0 25 50 75 Tc (°C) 100 125 150 175 -50 -25 0 25 50 75 Tc (°C) 11/18 VN920SP-E Figure 21. Maximum turn off current versus load inductance ILMAX (A) 100 A B C 10 1 0.01 0.1 A = Single Pulse at TJstart=150ºC B= Repetitive pulse at TJstart=100ºC C= Repetitive Pulse at TJstart=125ºC Conditions: VCC=13.5V 1 L(mH ) 10 100 Values are generated with RL=0Ω In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. VIN, IL Demagnetization Demagnetization Demagnetization t 12/18 VN920SP-E PowerSO-10™ Thermal Data Figure 22. PowerSO-10™ PC Board Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35µm, Copper areas: from minimum pad lay-out to 8cm2). Figure 23. Rthj-amb Vs PCB copper area in open box free air condition RTHj_amb (°C/W) 55 Tj-Tamb=50°C 50 45 40 35 30 0 2 4 6 8 10 PCB Cu heatsink area (cm^2) 13/18 VN920SP-E Figure 24. PowerSO-10 Thermal Impedance Junction Ambient Single Pulse ZTH (°C/W) 100 0.5 cm2 6 cm2 10 1 0.1 0.01 0.0001 0.001 0.01 0.1 1 10 100 1000 Time (s) Figure 25. Thermal fitting model of a single channel HSD in PowerSO-10 Pulse calculation formula THδ where = R TH ⋅ δ + Z THtp ( 1 – δ ) δ = tp ⁄ T Table 13. Thermal Parameter Tj C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 Pd T_amb 14/18 Area/island (cm2) R1 (°C/W) R2 (°C/W) R3( °C/W) R4 (°C/W) R5 (°C/W) R6 (°C/W) C1 (W.s/°C) C2 (W.s/°C) C3 (W.s/°C) C4 (W.s/°C) C5 (W.s/°C) C6 (W.s/°C) Footprint 0.02 0.1 0.2 0.8 12 37 0.0015 7.00E-03 0.015 0.3 0.75 3 6 22 5 VN920SP-E PACKAGE MECHANICAL Table 14. PowerSO-10™ Mechanical Data millimeters Symbol Min A A (*) A1 B B (*) C C (*) D D1 E E2 E2 (*) E4 E4 (*) e F F (*) H H (*) h L L (*) a α (*) Typ Max 3.35 3.4 0.00 0.40 0.37 0.35 0.23 9.40 7.40 9.30 7.20 7.30 5.90 5.90 3.65 3.6 0.10 0.60 0.53 0.55 0.32 9.60 7.60 9.50 7.60 7.50 6.10 6.30 1.27 1.25 1.20 13.80 13.85 1.35 1.40 14.40 14.35 0.50 1.20 0.80 0º 2º 1.80 1.10 8º 8º Note: (*) Muar only POA P013P Figure 26. PowerSO-10™ Package Dimensions B 0.10 A B 10 H E E2 E4 1 SEATING PLANE e B DETAIL "A" h A C 0.25 D = D1 = = = SEATING PLANE A F A1 A1 L DETAIL "A" α P095A 15/18 VN920SP-E Figure 27. PowerSO-10™ Suggested Pad Layout And Tube Shipment (No Suffix) CASABLANCA 14.6 - 14.9 MUAR B 10.8 - 11 C 6.30 C A A B 0.67 - 0.73 1 9.5 2 3 4 5 10 9 8 7 0.54 - 0.6 All dimensions are in mm. 1.27 6 Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) Casablanca 50 1000 532 10.4 16.4 0.8 Muar 50 1000 532 4.9 17.2 0.8 Figure 28. Tape And Reel Shipment (suffix “TR”) REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (± 0.1) P D (± 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) 24 4 24 1.5 1.5 11.5 6.5 2 End All dimensions are in mm. Start Top No components Components No components cover tape 500mm min Empty components pockets saled with cover tape. User direction of feed 16/18 500mm min VN920SP-E REVISION HISTORY Table 15. Revision History Date Revision Oct. 2004 1 Description of Changes - First Issue. 17/18 VN920SP-E Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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