VNQ810-E QUAD CHANNEL HIGH SIDE DRIVER Table 1. General Features Type VNQ810-E Figure 1. Package RDS(on) Iout VCC 160mΩ (*) 3.5A (*) 36V ) s ( ct (*) Per each channel CMOS COMPATIBLE INPUTS ■ OPEN DRAIN STATUS OUTPUTS ■ ON STATE OPEN LOAD DETECTION ■ OFF STATE OPEN LOAD DETECTION ■ SHORTED LOAD PROTECTION ■ UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN ■ PROTECTION AGAINST LOSS OF GROUND ■ VERY LOW STAND-BY CURRENT ■ REVERSE BATTERY PROTECTION (**) ■ IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE ■ ) (s u d o r P e t e l o s b O t c u DESCRIPTION The VNQ810-E is a quad HSD formed by assembling two VND810-E chips in the same SO28 package. The VNQ810-E is a monolithic device made by using STMicroelectronics VIPower M0-3 Technology, intended for driving any kind of load with one side connected to ground. Active V CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). od r P e SO-28 (DOUBLE ISLAND) Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The device detects open load condition both in on and off state. Output shorted to VCC is detected in the off state. Device automatically turns off in case of ground pin disconnection. t e l o s b O Table 2. Order Codes Package SO-28 Tube VNQ810-E Tape and Reel VNQ810TR-E Note: (**) See application schematic at page 9 Rev. 1 October 2004 1/20 VNQ810-E Figure 2. Block Diagram VCC VCC CLAMP OVERVOLTAGE UNDERVOLTAGE GND CLAMP 1 OUTPUT1 INPUT1 DRIVER 1 CLAMP 2 STATUS1 CURRENT LIMITER 1 ) s ( ct DRIVER 2 LOGIC OVERTEMP. 1 OUTPUT2 OPENLOAD ON 1 u d o CURRENT LIMITER 2 INPUT2 OPENLOAD OFF 1 OPENLOAD ON 2 r P e STATUS2 OPENLOAD OFF 2 t e l o OVERTEMP. 2 Table 3. Absolute Maximum Ratings Symbol )- s ( t c DC Supply Voltage VCC Value Unit 41 V - VCC Reverse DC Supply Voltage - 0.3 V - Ignd DC Reverse Ground Pin Current - 200 mA IOUT DC Output Current Pr Internally Limited A -6 A DC Input Current +/- 10 mA DC Status Current +/- 10 mA 4000 V 4000 V 5000 V 5000 V 23 mJ 6.25 W Internally Limited °C - 55 to 150 °C u d o - IOUT ISTAT o s b VESD Reverse DC Output Current e t e l IIN O Parameter s b O Electrostatic Discharge R=1.5KΩ; C=100pF) (Human Body Model: - INPUT - STATUS - OUTPUT - VCC Maximum Switching Energy EMAX Ptot Tj Tstg 2/20 (L=1.38mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IL=5A) Power dissipation (per island) at Tlead=25°C Junction Operating Temperature Storage Temperature VNQ810-E Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins VCC1,2 1 OUTPUT1 INPUT1 OUTPUT1 STATUS1 OUTPUT1 STATUS2 OUTPUT2 INPUT2 OUTPUT2 VCC1,2 OUTPUT2 VCC3,4 OUTPUT3 GND 3,4 OUTPUT3 INPUT3 OUTPUT3 STATUS3 OUTPUT4 STATUS4 OUTPUT4 INPUT4 OUTPUT4 14 VCC3,4 Connection / Pin Status Floating X To Ground N.C. X X IS3,4 )- VCC3,4 IIN1 s ( t c ISTAT1 du VSTAT1 VIN2 o r P VSTAT2 s b O ISTAT2 IIN3 ISTAT3 VIN3 e t e ol IIN2 VSTAT3 IIN4 VIN4 ISTAT4 VSTAT4 ) s ( ct u d o VCC3,4 15 Figure 4. Current and Voltage Conventions VIN1 VCC1,2 28 GND 1,2 r P e Output X Input X Through 10KΩ resistor t e l o s b O VCC3,4 IS1,2 VCC1,2 VF1 (*) INPUT1 VCC1,2 IOUT1 STATUS1 OUTPUT1 VOUT1 IOUT2 INPUT2 OUTPUT2 STATUS2 VOUT2 IOUT3 INPUT3 OUTPUT3 STATUS3 VOUT3 IOUT4 INPUT4 OUTPUT4 STATUS4 GND3,4 VOUT4 GND1,2 IGND3,4 IGND1,2 (*) VFn = VCCn - VOUTn during reverse battery condition Table 4. Thermal Data (Per island) Symbol Parameter Rthj-lead Thermal Resistance Junction-lead per chip Rthj-amb Thermal resistance Junction-ambient (one chip ON) Rthj-amb Thermal resistance Junction-ambient (two chips ON) Value Unit 20 °C/W 60 (1) 44 (2) °C/W (1) (2) °C/W 46 31 Note: 1. When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35µm thick) connected to all VCC pins.Horizontal mounting and no artificial air flow Note: 2. When mounted on a standard single-sided FR-4 board with 6cm 2 of Cu (at least 35µm thick) connected to all VCC pins.Horizontal mounting and no artificial air flow 3/20 VNQ810-E ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C< Tj <150°C, unless otherwise specified) (Per each channel) Table 5. Power Output Symbol Parameter VCC (**) Test Conditions Min. Typ. Max. Unit Operating Supply Voltage 5.5 13 36 V VUSD (**) Undervoltage Shut-down 3 4 5.5 V VOV (**) Overvoltage Shut-down 36 On State Resistance RON IS (**) IOUT=1A; Tj=25°C 160 IOUT=1A; VCC>8V 320 mΩ 40 ct µA 25 µA 7 mA 0 50 µA -75 0 µA 12 Off State; VCC=13V; VIN=VOUT=0V Off State; VCC=13V; VIN=VOUT=0V; Supply Current V du 12 Tj =25°C On State; VCC=13V; VIN=5V; IOUT=0A o r P 5 e t e ol mΩ (s) IL(off1) Off State Output Current VIN=VOUT=0V IL(off2) Off State Output Current VIN=0V; VOUT =3.5V IL(off3) Off State Output Current VIN=VOUT=0V; VCC=13V; Tj =125°C 5 µA IL(off4) Off State Output Current VIN=VOUT=0V; VCC=13V; Tj =25°C 3 µA Note: (**) Per island ) (s s b O Table 6. Protection (Per each channel) (See note 1) Symbol Parameter TTSD Shut-down Temperature TR Reset Temperature Thyst Thermal Hysteresis ete ol bs O o r P Status Delay in Overload Conditions tsdl Ilim du VDEMAG ct Current limitation Turn-off Output Clamp Voltage Test Conditions Min. Typ. Max. Unit 150 175 200 °C 135 7 °C 15 Tj>TTSD 3.5 5 5.5V<VCC<36V IOUT =1A; L=6mH VCC-41 VCC-48 °C 20 µs 7.5 A 7.5 A VCC-55 V Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles Table 7. VCC - Output Diode Symbol VF 4/20 Parameter Forward on Voltage Test Conditions -IOUT=0.5A; Tj=150°C Min Typ Max 0.6 Unit V VNQ810-E ELECTRICAL CHARACTERISTICS (continued) Table 8. Status Pin (Per each channel) Symbol Parameter Test Conditions VSTAT Status Low Output Voltage ISTAT =1.6mA ILSTAT Status Leakage Current Normal Operation; VSTAT=5V Status Pin Input Normal Operation; VSTAT=5V CSTAT Capacitance ISTAT =1mA VSCL Status Clamp Voltage ISTAT =-1mA Min 6 Typ 6.8 Max 0.5 10 Unit V µA 100 pF 8 V -0.7 V Table 9. Switching (Per each channel) (VCC=13V) Symbol Parameter td(on) Turn-on Delay Time td(off) Turn-off Delay Time Test Conditions RL=13Ω from VIN rising edge to VOUT =1.3V RL=13Ω from VIN falling edge to VOUT =11.7V dVOUT /dt(on) Turn-on Voltage Slope RL=13Ω from VOUT =1.3V to VOUT =10.4V dVOUT /dt(off) Turn-off Voltage Slope RL=13Ω from VOUT =11.7V to VOUT =1.3V IOL Parameter Openload ON State Detection Threshold Openload ON State Test Conditions s ( t c du tDOL(on) VOL Detection Delay Openload OFF State Voltage Detection Threshold Openload Detection Delay at Turn Off e t e l tDOL(off) o s b o r P )- s b O VIN=5V Typ 30 o r P See relative diagram See relative diagram Unit µs µs V/µs V/µs Min Typ Max Unit 20 40 80 mA 200 µs 3.5 V 1000 µs Max 1.25 Unit V µA V µA V V IOUT=0A VIN=0V ) s ( t Max c u d 30 e t e ol Table 10. Openload Detection Symbol Min 1.5 2.5 Table 11. Logic Input (Per each channel) O Symbol VIL IIL VIH IIH VI(hyst) VICL Parameter Test Conditions Input Low Level Low Level Input Current VIN=1.25V Input High Level High Level Input Current VIN=3.25V Input Hysteresis Voltage IIN=1mA Input Clamp Voltage IIN=-1mA Min Typ 1 3.25 10 0.5 6 6.8 -0.7 8 V 5/20 VNQ810-E Table 12. Truth Table CONDITIONS INPUT OUTPUT SENSE Normal Operation L H L H H H Current Limitation L H H L X X H (Tj < TTSD) H (Tj > TTSD) L Overtemperature L H L L H L Undervoltage L H L L X X Overvoltage L H L L Output Voltage > VOL L H H H Output Current < IOL L H L H ) (s VOUT > VOL VINn t c u d o r VSTATn P e t e l o s b O 6/20 IOUT < IOL tDOL(off) du e t e ol Figure 5. s b O OPEN LOAD STATUS TIMING (with external pull-up) ) s ( ct H H o r P H L OVER TEMP STATUS TIMING Tj > TTSD VINn VSTATn tSDL tDOL(on) L H tSDL VNQ810-E Figure 6. Switching time Waveforms VOUTn 90% 80% dVOUT/dt(off) dVOUT/dt(on) 10% t VINn td(on) ) s ( ct td(off) u d o r P e ISO T/R 7637/1 Test Pulse I 1 2 3a 3b 4 5 -25 V +25 V -25 V +25 V -4 V +26.5 V s b O 1 2 3a 3b 4 5 CLASS C E s ( t c u d o r P e t e l o ISO T/R 7637/1 Test Pulse )- II I C C C C C C -50 V +50 V -50 V +50 V -5 V +46.5 V t e l o s b O Table 13. Electrical Transient Requirements On VCC Pin t TEST LEVELS III IV -75 V +75 V -100 V +75 V -6 V +66.5 V -100 V +100 V -150 V +100 V -7 V +86.5 V TEST LEVELS RESULTS II III C C C C C C C C C C E E Delays and Impedance 2 ms 10 Ω 0.2 ms 10 Ω 0.1 µs 50 Ω 0.1 µs 50 Ω 100 ms, 0.01 Ω 400 ms, 2 Ω IV C C C C C E CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. 7/20 VNQ810-E Figure 7. Waveforms NORMAL OPERATION INPUTn OUTPUT VOLTAGEn STATUSn ) s ( ct UNDERVOLTAGE VUSDhyst VCC VUSD u d o INPUTn OUTPUT VOLTAGEn STATUSn t e l o OVERVOLTAGE VCC>VOV VCC<VOV VCC INPUTn OUTPUT VOLTAGEn STATUSn ) (s t c u s b O OPEN LOAD with external pull-up d o r INPUTn OUTPUT VOLTAGEn P e STATUSn t e l o bs O >V VV >V OUT OL OUT OL VOL OL OPEN LOAD without external pull-up INPUTn OUTPUT VOLTAGEn STATUSn OVERTEMPERATURE Tj TTSD TR INPUTn OUTPUT CURRENTn STATUSn 8/20 r P e undefined VNQ810-E Figure 8. Application Schematic +5V +5V +5V VCC1,2 VCC3,4 Rprot STATUS1 Rprot INPUT1 ) s ( ct Dld Rprot STATUS2 Rprot INPUT2 Rprot STATUS3 µC Rprot OUTPUT1 u d o r P e t e l o INPUT3 OUTPUT2 Rprot STATUS4 OUTPUT4 INPUT4 du e t e ol OUTPUT3 O ) s ( t c Rprot bs o r P GND1,2 GND3,4 RGND VGND +5V +5V DGND s b O Note: Channels 3 & 4 have the same internal circuit as channel 1 & 2. GND PROTECTION REVERSE BATTERY NETWORK AGAINST Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND ≤ 600mV / 2(IS(on)max). 2) RGND ≥ (−VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the of the device’s datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggest to utilize Solution 2 . 9/20 VNQ810-E For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V 5kΩ ≤ Rprot ≤ 65kΩ. Recommended Rprot value is 10kΩ. Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected. OPEN LOAD DETECTION IN OFF STATE Off state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1) no false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT=(VPU/(RL+RPU))RL<VOlmin ) s ( ct LOAD DUMP PROTECTION Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table. .µC I/Os PROTECTION: If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the µC I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os. -VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax Calculation example: ) (s 2) no misdetection when load is disconnected: in this case the VOUT has to be higher than VOLmax; this results in the following condition RPU<(VPU–VOLmax)/ IL(off2). Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pull-up resistor RPU should be connected to a supply that is switched OFF when the module is in standby. The values of VOLmin, VOLmax and IL(off2) are available in the Electrical Characteristics section. u d o r P e t e l o s b O Figure 9. Open Load detection in off state t c u od r P e t e l o bs O INPUT V batt. VPU VCC RPU DRIVER + LOGIC IL(off2) OUT + R STATUS VOL GROUND 10/20 RL VNQ810-E Figure 13. High Level Input Current Figure 10. Off State Output Current IL(off1) (uA) Iih (uA) 1.6 5 1.44 4.5 Off state Vcc=36V Vin=Vout=0V 1.28 1.12 Vin=3.25V 4 3.5 0.96 3 0.8 2.5 0.64 2 0.48 1.5 0.32 1 0.16 0.5 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (ºC) 8 Iin=1mA bs 7.6 0.04 7.4 7.2 ) s ( ct 7 6.8 6.6 du -25 0 25 e t e ol o r P 50 75 100 125 175 125 150 175 125 150 175 u d o -O Vstat=5V 0.03 0.02 0.01 0 150 175 -50 -25 0 25 Tc (°C) 50 75 100 Tc (°C) Figure 12. Status Low Output Voltage s b O 150 t e l o 0.05 6.4 125 r P e Ilstat (uA) 7.8 -50 100 Figure 14. Status Leakage Current Vicl (V) 6 75 Tc (°C) Figure 11. Input Clamp Voltage 6.2 50 ) s ( ct Figure 15. Status Clamp Voltage Vstat (V) Vscl (V) 0.8 8 7.8 0.7 Istat=1mA Istat=1.6mA 7.6 0.6 7.4 0.5 7.2 0.4 7 6.8 0.3 6.6 0.2 6.4 0.1 6.2 0 6 -50 -25 0 25 50 75 Tc (°C) 100 125 150 175 -50 -25 0 25 50 75 100 Tc (°C) 11/20 VNQ810-E Figure 16. Overvoltage Shutdown Figure 19. ILIM Vs Tcase Vov (V) Ilim (A) 50 10 48 9 46 8 44 7 42 6 40 5 38 4 36 3 34 2 Vcc=13V 32 1 30 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (°C) 1000 500 900 450 Vcc=13V Rl=13Ohm 350 600 )- 500 s ( t c 400 300 du 200 -25 0 o r P 25 e t e ol 50 75 u d o 100 150 175 125 150 175 t e l o Rl=13Ohm s b O 400 700 -50 125 r P e dVout/dt(off) (V/ms) 0 100 Figure 20. Turn-off Voltage Slope dVout/dt(on) (V/ms) 100 75 Tc (°C) Figure 17. Turn-on Voltage Slope 800 50 ) s ( ct 300 250 200 150 100 50 0 150 -50 175 -25 0 25 Tc (ºC) 50 75 100 125 Tc (°C) Figure 18. On State Resistance Vs Tcase Figure 21. On State Resistance Vs VCC s b O Ron (mOhm) Ron (mOhm) 400 300 275 350 Iout=0.5A 250 Iout=0.5A Vcc=8V; 13V & 36V 300 Tc= 150°C 225 250 200 175 200 150 150 Tc= 25°C 125 100 100 Tc= - 40°C 50 75 0 50 -50 -25 0 25 50 75 Tc (°C) 12/20 100 125 150 175 5 10 15 20 25 Vcc (V) 30 35 40 VNQ810-E Figure 22. Input High Level Figure 25. Input Low Level Vih (V) Vil (V) 3.6 2.6 3.4 2.4 3.2 2.2 3 2 2.8 1.8 2.6 1.6 2.4 1.4 2.2 1.2 2 1 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (°C) 5 55 4.5 4 O ) 45 40 s ( t c 30 u d o r P e 15 10 -50 -25 0 t e l o 25 50 75 u d o 100 125 150 175 t e l o bs Vcc=13V Vin=5V 35 125 r P e Vol (V) 60 20 100 Figure 26. Openload Off State Detection Threshold Iol (mA) 25 75 Tc (°C) Figure 23. Openload On State Detection Threshold 50 50 ) s ( ct Vin=0V 3.5 3 2.5 2 1.5 1 0.5 0 150 175 Tc (°C) -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Figure 24. Input Hysteresis Voltage s b O Vhyst (V) 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) 13/20 VNQ810-E Figure 27. SO-28 (Double Island) Maximum turn off current versus load inductance ILMAX (A) 10 A B ) s ( ct C u d o r P e t e l o 1 0.01 0.1 ) (s t c u A = Single Pulse at TJstart=150ºC B= Repetitive pulse at T Jstart=100ºC C= Repetitive Pulse at T Jstart=125ºC od r P e t e l o Conditions: VCC=13.5V s 1 b OL(mH) 10 100 Values are generated with R L=0Ω In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. s b O VIN, IL Demagnetization Demagnetization Demagnetization t 14/20 VNQ810-E SO-28 Double Island Thermal Data Figure 28. SO-28 Double Island PC Board ) s ( ct u d o Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35µm, Copper areas: 0.5cm2, 3cm2, 6cm2). r P e t e l o Table 14. Thermal Calculation According To The Pcb Heatsink Area Chip 1 ON OFF ON ON Chip 2 OFF ON ON ON Tjchip1 RthA x Pdchip1 + Tamb RthC x Pdchip2 + Tamb RthB x (Pdchip1 + Pdchip2) + Tamb (RthA x Pdchip1) + RthC x Pdchip2 + Tamb ) (s Tjchip2 Note RthC x Pdchip1 + Tamb RthA x Pdchip2 + Tamb RthB x (Pdchip1 + Pdchip2) + Tamb Pdchip1=Pdchip2 (RthA x Pdchip2) + RthC x Pdchip1 + Tamb Pdchip1≠Pdchip2 s b O t c u RthA = Thermal resistance Junction to Ambient with one chip ON RthB = Thermal resistance Junction to Ambient with both chips ON and Pdchip1=Pdchip2 RthC = Mutual thermal resistance d o r Figure 29. Rthj-amb Vs. PCB Copper Area In Open Box Free Air Condition P e s b O t e l o RTHj_am b (°C/W) 70 60 RthA 50 RthB 40 RthC 30 20 10 0 1 2 3 4 5 PCB Cu heatsink area (cm ^2)/island 6 7 15/20 VNQ810-E Figure 30. SO-28 Thermal Impedance Junction Ambient Single Pulse Zth(°C/W) 100 0,5 cm ^2/is land 3 cm ^2/is land 6 cm ^2/is land 10 One channel ON ) s ( ct Two channels ON on same chip 1 u d o r P e 0.1 t e l o 0.01 0.0001 0.001 0.01 ) (s 0.1 1 time(s) t c u od Figure 31. Thermal fitting model of a double channel HSD in SO-28 e t e ol Tj_1 Pd1 bs Tj_2 O C1 C2 R1 R2 C13 R13 Pr C4 C5 C6 R3 R4 R5 R6 R14 R17 R18 C7 C8 C9 R7 R8 R9 C15 R15 C10 R10 C16 R16 Pd4 T_amb 16/20 100 1000 Pulse calculation formula Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ ) δ = tp ⁄ T Table 15. Thermal Parameter C14 C11 C12 Pd3 Tj_4 10 where C3 Pd2 Tj_3 s b O R11 R12 Area/island (cm2) R1=R7=R13=R15 (°C/W) R2=R8=R14=R16 (°C/W) R3=R9 (°C/W) R4=R10 (°C/W) R5=R11 (°C/W) R6=R12 (°C/W) C1=C7=C13=C15 (W.s/°C) C2=C8=C14=C16 (W.s/°C) C3=C9 (W.s/°C) C4=C10 (W.s/°C) C5=C11 (W.s/°C) C6=C12 (W.s/°C) R17=R18 (°C/W) 0.5 0.05 0.3 3.4 11 15 30 0.001 5.00E-03 1.00E-02 0.2 1.5 5 150 6 13 8 VNQ810-E PACKAGE MECHANICAL Table 16. SO-28 Mechanical Data millimeters Symbol Min A a1 b b1 C c1 D E e e3 F L S Typ Max 2.65 0.30 0.49 0.32 0.10 0.35 0.23 0.50 45° (typ.) 17.7 10.00 18.1 10.65 ) s ( ct 1.27 16.51 7.40 0.40 7.60 1.27 8° (max.) u d o r P e Figure 32. SO-28 Package Dimensions t e l o ) (s s b O t c u d o r P e t e l o s b O 17/20 VNQ810-E Figure 33. SO-28 Tube Shipment (No Suffix) Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) C B 28 700 532 3.5 13.8 0.6 All dimensions are in mm. A ) s ( ct u d o Figure 34. Tape And Reel Shipment (Suffix “TR”) r P e REEL DIMENSIONS let Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) o s b O ) s ( t c u d o r P e TAPE DIMENSIONS 1000 1000 330 1.5 13 20.2 16.4 60 22.4 According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 t e l o Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing s b O W P0 (± 0.1) P D (± 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) 16 4 12 1.5 1.5 7.5 6.5 2 End All dimensions are in mm. Start Top No components Components No components cover tape 500mm min Empty components pockets saled with cover tape. User direction of feed 18/20 500mm min VNQ810-E REVISION HISTORY Date Oct. 2004 Revision 1 - First Issue Description of Changes ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 19/20 VNQ810-E ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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