W28F641B/T
64MBIT (4MBIT × 16)
PAGE MODE DUAL WORK FLASH MEMORY
Table of Contents1. GENERAL DESCRIPTION.................................................................................................................. 2
2. FEATURES ......................................................................................................................................... 2
3. PIN CONFIGURATION ....................................................................................................................... 3
4. ELECTRICAL CHARACTERISTICS ................................................................................................. 16
Absolute Maximum Ratings* ............................................................................................................ 16
Operating Conditions ........................................................................................................................ 16
Capacitance(1) .................................................................................................................................. 17
AC Input/Output Test Conditions...................................................................................................... 17
DC Characteristics............................................................................................................................ 18
AC Characteristics - Read-only Operations(1) ................................................................................. 20
AC Characteristics - Write Operations(1, 2) ...................................................................................... 23
Reset Operations.............................................................................................................................. 25
Reset AC Specifications ................................................................................................................... 25
Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance(3) ............. 26
5. ADDITIONAL INFORMATION........................................................................................................... 27
Recommended Operating Conditions .............................................................................................. 27
At Device Power-Up ................................................................................................................... 27
Glitch Noises .............................................................................................................................. 28
6. ORDERING INFORMATION............................................................................................................. 29
7. PACKAGE DIMENSIONS ................................................................................................................. 30
48-pin Standard Thin Small Outline Package (measured in millimeters)......................................... 30
48-ball TFBGA (8 mm x 11 mm) (measurements in millimeters) ..................................................... 30
8. VERSION HISTORY ......................................................................................................................... 31
-1-
Publication Release Date: March 27, 2003
Revision A3
W28F641B/T
1. GENERAL DESCRIPTION
The W28F641, a 4-Plane Page Mode Dual Work (Simultaneous Read while Erase/Program) Flash
memory, is a low power, high density, low cost, nonvolatile read/write storage solution for a wide
range of applications. The product can be operated at VDD = 2.7V to 3.6V and VPP = 1.65V to 3.6V or
11.7V to 12.3V. Its low voltage operation capability greatly extends battery life for portable
applications.
The W28F641 provides high performance asynchronous page mode. It allows code execution directly
from Flash, thus eliminating time-consuming wait states. Furthermore, the configurative partitioning
architecture allows flexible dual work operation.
The memory array block architecture utilizes Enhanced Data Protection features, and provides
separate Parameter and Main Blocks that provide maximum flexibility for safe nonvolatile code and
data storage.
Fast program capability is provided through the use of high speed Page Buffer Program. Special OTP
(One Time Program) block provides an area to store permanent code such as a unique number.
2. FEATURES
− One hundred and twenty-seven 32k-word
Main Blocks
− Top or Bottom Parameter Location
• 64M Density with 16Bit I/O Interface
• High-Performance Reads
•
•
•
•
•
− 80/35 nS 8-Word Page Mode
Configurative 4-Plane Dual Work
− Flexible Partitioning
− Read operations during Block Erase or (Page
Buffer) Program
− Status Register for Each Partition
Low Power Operation
− 2.7V Read and Write Operations
− VDDQ for Input/Output Power Supply Isolation
− Automatic Power Savings Mode Reduces
ICCR in Static Mode
Enhanced Code + Data Storage
− 5 µS Typical Erase/Program Suspends
OTP (One Time Program) Block
− 4-Word Factory-Programmed Area
− 4-Word User-Programmable Area
High Performance Program with Page Buffer
− 16-Word Page Buffer
− 5 µS/ Word (Typ.) at 12V VPP
• Enhanced Data Protection Features
− Individual Block Lock and Block Lock-Down
with Zero-Latency
− All blocks are locked at power-up or device
reset
− Absolute Protection with VPP ≤ VPPLK
− Block Erase, Full Chip Erase, (Page Buffer)
Word Program Lockout during Power
Transitions
• Automated Erase/Program Algorithms
− 3.0V Low-Power 11 µS/ Word (Typ.)
Programming
− 12V No Glue Logic 9 µS/ Word (Typ.)
Production Programming and 0.5s Erase
(Typ.)
• Cross-Compatible Command Support
− Common Flash Interface (CFI)
− Basic Command Set
• Extended Cycling Capability
• Operating Temperature
− -40°C to +85°C
• CMOS Process (P-type silicon substrate)
− Minimum 100,000 Block Erase Cycles
• Chip-Size Packaging
− 0.75 mm pitch 48-Ball TFBGA and 48-Pin
TSOP
• Flexible Blocking Architecture
− Eight 4k-word Parameter Blocks
• ETOX™ Flash Technology
-2-
W28F641B/T
* ETOX is a trademark of Intel Corporation.
• No designed or rated as radiation hardened
3. PIN CONFIGURATION
H
A13
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
#WE
#RESET
VPP
#WP
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
G
A11
F
E
D
C
A19
A
A7
A4
1
A8
VPP
#WP
#WE
#RESET
A18
A17
A5
A2
2
A21
A20
A6
A3
A1
3
DQ2
DQ8
#CE
A0
4
DQ9
DQ0
Vss
5
DQ10
DQ1
#OE
6
A14
A10
A15
A12
A9
A16
DQ14
DQ5
DQ11
VDDQ
DQ15
DQ6
DQ12
DQ3
Vss
DQ7
DQ13
DQ4
V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
B
DD
48-pin TSOP
Standard Pinout
12mm X 20mm
Top View
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
0.75 mm pitch
48-Ball TFBGA
Pinout
A16
VDDQ
Vss
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V DD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
#OE
Vss
#CE
A0
8 x 11 mm
TOP VIEW
Figure 1. 0.75 mm pitch TFBGA 48-Ball and 48-Lead TSOP (Normal Bend) Pinout
-3-
Publication Release Date: March 27, 2003
Revision A3
W28F641B/T
Table 1. Pin Descriptions
SYMBOL
TYPE
A0 − A21
INPUT
NAME AND FUNCTION
ADDRESS INPUTS: Inputs for addresses. 64M: A0 − A21.
DATA INPUT/OUTPUTS: Inputs data and commands during CUI (Command User
Interface) write cycles, outputs data during memory array, status register, query code,
INPUT/
identifier code and partition configuration register code reads. Data pins float to high
DQ0 − DQ15
OUTPUT
impedance (High Z) when the chip or outputs are deselected. Data is internally
latched during an erase or program cycle.
#CE
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and
sense amplifiers. #CE-high (VIH) deselects the device and reduces power
consumption to standby levels.
#RESET
INPUT
RESET: When low (VIL), #RESET resets internal automation and inhibits write
operations, which provides data protection. #RESET-high (VIH) enables normal
operation. After power-up or reset mode, the device is automatically set to read array
mode. #RESET must be low during power-up/down.
#OE
INPUT
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
#WE
INPUT
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data
are latched on the rising edge of #CE or #WE (whichever goes high first).
#WP
INPUT
WRITE PROTECT: When #WP is VIL, locked-down blocks cannot be unlocked. Erase
or program operation can be executed to the blocks which are not locked and not
locked-down. When #WP is VIH, lock-down is disabled.
MONITORING POWER SUPPLY VOLTAGE: VPP is not used for power supply pin.
With VPP ≤ VPPLK, block erase, full chip erase, (page buffer) program or OTP program
cannot be executed and should not be attempted.
VPP
INPUT
Applying 12V ±0.3V to VPP provides fast erasing or fast programming mode. In this
mode, VPP is power supply pin. Applying 12V ±0.3V to VPP during erase/program can
only be done for a maximum of 1,000 cycles on each block. VPP may be connected to
12V ±0.3V for a total of 80 hours maximum. Use of this pin at 12V beyond these
limits may reduce block cycling capability or cause permanent damage.
VDD
DEVICE POWER SUPPLY: With VDD ≤ VLKO, all write attempts to the flash memory
SUPPLY are inhibited. Device operations at invalid VDD voltage (see DC Characteristics)
produce spurious results and should not be attempted.
VDDQ
SUPPLY
VSS
SUPPLY GROUND: Do not float any ground pins.
INPUT/OUTPUT POWER SUPPLY (2.7V to 3.6V): Power supply for all input/output
pins.
-4-
W28F641B/T
Table 2. Simultaneous Operation Modes Allowed with Four Planes(1,2)
THEN THE MODES ALLOWED IN THE OTHER PARTITION IS:
IF ONE
PARTITION IS:
Read Read Read Read
Array ID/OTP Status Query
Word
Program
Page
Buffer
Program
Full
Block
OTP
Block
Program
Chip
Erase
Program Erase
Suspend
Erase
Suspend
Read Array
X
X
X
X
X
X
X
X
X
Read ID/OTP
X
X
X
X
X
X
X
X
X
Read Status
X
X
X
X
X
X
X
X
Read Query
X
X
X
X
X
X
X
X
Word Program
X
X
X
X
X
Page Buffer
Program
X
X
X
X
X
OTP Program
Block Erase
X
X
X
X
X
X
X
Full Chip Erase
X
X
X
Program
Suspend
X
X
X
X
Block Erase
Suspend
X
X
X
X
X
X
X
X
Notes:
1. "X" denotes the operation available.
2. Configurative Partition Dual Work Restrictions:
Status register reflects partition state, not WSM (Write State Machine) state - this allows a status register for each partition.
Only one partition can be erased or programmed at a time - no command queuing.
Commands must be written to an address within the block targeted by that command.
-5-
Publication Release Date: March 27, 2003
Revision A3
W28F641B/T
4K-WORD
4K-WORD
4K-WORD
4K-WORD
4K-WORD
4K-WORD
4K-WORD
4K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
BLOCK NUMBER
ADDRESS RANGE
3FF000H - 3FFFFFH
3FE000H - 3FEFFFH
3FD000H - 3FDFFFH
3FC000H - 3FCFFFH
3FB000H - 3FBFFFH
3FA000H - 3FAFFFH
3F9000H - 3F9FFFH
3F8000H - 3F8FFFH
3F0000H - 3F7FFFH
3E8000H - 3EFFFFH
3E0000H - 3E7FFFH
3D8000H - 3DFFFFH
3D0000H - 3D7FFFH
3C8000H - 3CFFFFH
3C0000H - 3C7FFFH
3B8000H - 3BFFFFH
3B0000H - 3B7FFFH
3A8000H - 3AFFFFH
3A0000H - 3A7FFFH
398000H - 39FFFFH
390000H - 397FFFH
388000H - 38FFFFH
380000H - 387FFFH
378000H - 37FFFFH
370000H - 377FFFH
368000H - 36FFFFH
360000H - 367FFFH
358000H - 35FFFFH
350000H - 357FFFH
348000H - 34FFFFH
340000H - 347FFFH
338000H - 33FFFFH
330000H - 337FFFH
328000H - 32FFFFH
320000H - 327FFFH
318000H - 31FFFFH
310000H - 317FFFH
308000H - 30FFFFH
300000H - 307FFFH
2F8000H - 2FFFFFH
2F0000H - 2F7FFFH
2E8000H - 2EFFFFH
2E0000H - 2E7FFFH
2D8000H - 2DFFFFH
2D0000H - 2D7FFFH
2C8000H - 2CFFFFH
2C0000H - 2C7FFFH
2B8000H - 2BFFFFH
2B0000H - 2B7FFFH
2A8000H - 2AFFFFH
2A0000H - 2A7FFFH
298000H - 29FFFFH
290000H - 297FFFH
288000H - 28FFFFH
280000H - 287FFFH
278000H - 27FFFFH
270000H - 277FFFH
268000H - 26FFFFH
260000H - 267FFFH
258000H - 25FFFFH
250000H - 257FFFH
248000H - 24FFFFH
240000H - 247FFFH
238000H - 23FFFFH
230000H - 237FFFH
228000H - 22FFFFH
220000H - 227FFFH
218000H - 21FFFFH
210000H - 217FFFH
208000H - 20FFFFH
200000H - 207FFFH
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
1F8000H - 1FFFFFH
1F0000H - 1F7FFFH
1E8000H - 1EFFFFH
1E0000H - 1E7FFFH
1D8000H - 1DFFFFH
1D0000H - 1D7FFFH
1C8000H - 1CFFFFH
1C0000H - 1C7FFFH
1B8000H - 1BFFFFH
1B0000H - 1B7FFFH
1A8000H - 1AFFFFH
1A0000H - 1A7FFFH
198000H - 19FFFFH
190000H - 197FFFH
188000H - 18FFFFH
180000H - 187FFFH
178000H - 17FFFFH
170000H - 177FFFH
168000H - 16FFFFH
160000H - 167FFFH
158000H - 15FFFFH
150000H - 157FFFH
148000H - 14FFFFH
140000H - 147FFFH
138000H - 13FFFFH
130000H - 137FFFH
128000H - 12FFFFH
120000H - 127FFFH
118000H - 11FFFFH
110000H - 117FFFH
108000H - 10FFFFH
100000H - 107FFFH
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
0F8000H - 0FFFFFH
0F0000H - 0F7FFFH
0E8000H - 0EFFFFH
0E0000H - 0E7FFFH
0D8000H - 0DFFFFH
0D0000H - 0D7FFFH
0C8000H - 0CFFFFH
0C0000H - 0C7FFFH
0B8000H - 0BFFFFH
0B0000H - 0B7FFFH
0A8000H - 0AFFFFH
0A0000H - 0A7FFFH
098000H - 09FFFFH
090000H - 097FFFH
088000H - 08FFFFH
080000H - 087FFFH
078000H - 07FFFFH
070000H - 077FFFH
068000H - 06FFFFH
060000H - 067FFFH
058000H - 05FFFFH
050000H - 057FFFH
048000H - 04FFFFH
040000H - 047FFFH
038000H - 03FFFFH
030000H - 037FFFH
028000H - 02FFFFH
020000H - 027FFFH
018000H - 01FFFFH
010000H - 017FFFH
008000H - 00FFFFH
000000H - 007FFFH
Figure 2.1 Top Parameter Memory Map
-6-
ADDRESS RANGE
PLANE1 (UNIFORM PLANE)
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
PLANE0 (UNIFORM PLANE)
PLANE2 (UNIFORM PLANE)
PLANE3 (PARAMETER PLANE)
BLOCK NUMBER
W28F641B/T
3F8000H - 3FFFFFH
3F0000H - 3F7FFFH
3E8000H - 3EFFFFH
3E0000H - 3E7FFFH
3D8000H - 3DFFFFH
3D0000H - 3D7FFFH
3C8000H - 3CFFFFH
3C0000H - 3C7FFFH
3B8000H - 3BFFFFH
3B0000H - 3B7FFFH
3A8000H - 3AFFFFH
3A0000H - 3A7FFFH
398000H - 39FFFFH
390000H - 397FFFH
388000H - 38FFFFH
380000H - 387FFFH
378000H - 37FFFFH
370000H - 377FFFH
368000H - 36FFFFH
360000H - 367FFFH
358000H - 35FFFFH
350000H - 357FFFH
348000H - 34FFFFH
340000H - 347FFFH
338000H - 33FFFFH
330000H - 337FFFH
328000H - 32FFFFH
320000H - 327FFFH
318000H - 31FFFFH
310000H - 317FFFH
308000H - 30FFFFH
300000H - 307FFFH
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
2F8000H - 2FFFFFH
2F0000H - 2F7FFFH
2E8000H - 2EFFFFH
2E0000H - 2E7FFFH
2D8000H - 2DFFFFH
2D0000H - 2D7FFFH
2C8000H - 2CFFFFH
2C0000H - 2C7FFFH
2B8000H - 2BFFFFH
2B0000H - 2B7FFFH
2A8000H - 2AFFFFH
2A0000H - 2A7FFFH
298000H - 29FFFFH
290000H - 297FFFH
288000H - 28FFFFH
280000H - 287FFFH
278000H - 27FFFFH
270000H - 277FFFH
268000H - 26FFFFH
260000H - 267FFFH
258000H - 25FFFFH
250000H - 257FFFH
248000H - 24FFFFH
240000H - 247FFFH
238000H - 23FFFFH
230000H - 237FFFH
228000H - 22FFFFH
220000H - 227FFFH
218000H - 21FFFFH
210000H - 217FFFH
208000H - 20FFFFH
200000H - 207FFFH
BLOCK NUMBER
ADDRESS RANGE
PLANE1 (UNIFORM PLANE)
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
1F8000H - 1FFFFFH
1F0000H - 1F7FFFH
1E8000H - 1EFFFFH
1E0000H - 1E7FFFH
1D8000H - 1DFFFFH
1D0000H - 1D7FFFH
1C8000H - 1CFFFFH
1C0000H - 1C7FFFH
1B8000H - 1BFFFFH
1B0000H - 1B7FFFH
1A8000H - 1AFFFFH
1A0000H - 1A7FFFH
198000H - 19FFFFH
190000H - 197FFFH
188000H - 18FFFFH
180000H - 187FFFH
178000H - 17FFFFH
170000H - 177FFFH
168000H - 16FFFFH
160000H - 167FFFH
158000H - 15FFFFH
150000H - 157FFFH
148000H - 14FFFFH
140000H - 147FFFH
138000H - 13FFFFH
130000H - 137FFFH
128000H - 12FFFFH
120000H - 127FFFH
118000H - 11FFFFH
110000H - 117FFFH
108000H - 10FFFFH
100000H - 107FFFH
PLANE0 (PARAMETER PLANE)
PLANE3 (UNIFORM PLANE)
ADDRESS RANGE
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
PLANE2 (UNIFORM PLANE)
BLOCK NUMBER
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
4K-WORD
4K-WORD
4K-WORD
4K-WORD
4K-WORD
4K-WORD
4K-WORD
4K-WORD
0F8000H - 0FFFFFH
0F0000H - 0F7FFFH
0E8000H - 0EFFFFH
0E0000H - 0E7FFFH
0D8000H - 0DFFFFH
0D0000H - 0D7FFFH
0C8000H - 0CFFFFH
0C0000H - 0C7FFFH
0B8000H - 0BFFFFH
0B0000H - 0B7FFFH
0A8000H - 0AFFFFH
0A0000H - 0A7FFFH
098000H - 09FFFFH
090000H - 097FFFH
088000H - 08FFFFH
080000H - 087FFFH
078000H - 07FFFFH
070000H - 077FFFH
068000H - 06FFFFH
060000H - 067FFFH
058000H - 05FFFFH
050000H - 057FFFH
048000H - 04FFFFH
040000H - 047FFFH
038000H - 03FFFFH
030000H - 037FFFH
028000H - 02FFFFH
020000H - 027FFFH
018000H - 01FFFFH
010000H - 017FFFH
008000H - 00FFFFH
007000H - 007FFFH
006000H - 006FFFH
005000H - 005FFFH
004000H - 004FFFH
003000H - 003FFFH
002000H - 002FFFH
001000H - 001FFFH
000000H - 000FFFH
Figure 2.2 Bottom Parameter Memory Map
-7-
Publication Release Date: March 27, 2003
Revision A3
W28F641B/T
Table 3. Identifier Codes and OTP Address for Read Operation
ADDRESS
[A15 − A0]
CODE
Manufacture Code
Manufacture Code
0000H
1
00B0H
1, 2
00B1H
1, 2
DQ0 = 0
3
DQ0 = 1
3
DQ1 = 0
3
DQ1 = 1
3
0006H
PCRC
1, 4
OTP Lock
0080H
OTP-LK
1, 5
OTP
0081-0088H
OTP
1, 6
0001H
Bottom Parameter
Block is Unlocked
Block is Locked
Block Lock Configuration Code
Block Address
+2
Block is not Locked-Down
Block is Locked-Down
Device Configuration Code
Partition Configuration register
OTP
NOTES
00B0H
Top Parameter
Device Code
DATA
[DQ15 − DQ0]
Notes:
1. The address A21 − A16 are shown in below table for reading the manufacturer code, device code, device configuration code
and OTP data.
2. Bottom parameter device has its parameter blocks in the plane0 (The lowest address).
Top parameter device has its parameter blocks in the plane3 (The highest address).
3. Block Address = The beginning location of a block address within the partition to which the Read Identifier Codes/OTP
command (90H) has been written.
DQ15 − DQ2 are reserved for future implementation.
4. PCRC = Partition Configuration Register Code.
5. OTP-LK = OTP Block Lock configuration.
6. OTP = OTP Block data.
Table 4. Identifier Codes and OTP Address for Read Operation on Partition Configuration(1)
PARTITION CONFIGURATION REGISTER(2)
PCR.10
PCR.9
ADDRESS (64M-bit device)
[A21 − A16]
PCR.8
0
0
0
00H
0
0
1
00H or 10H
0
1
0
00H or 20H
1
0
0
00H or 30H
0
1
1
00H or 10H or 20H
1
1
0
00H or 20H or 30H
1
0
1
00H or 10H or 30H
1
1
1
00H or 10H or 20H or 30H
Notes:
1. The address to read the identifier codes or OTP data is dependent on the partition which is selected when writing the Read
Identifier Codes/OTP command (90H).
2. Refer to Table 12 for the partition configuration register.
-8-
W28F641B/T
[A21-A0]
000088H
Customer Programmable Area
000085H
000084H
Factory Programmed Area
000081H
000080H
Reserved for Future Implementation
(DQ15-DQ2)
Customer programmable Area Lock Bit (DQ1)
Factory programmed Area Lock Bit (DQ0)
Figure 3. OTP Block Address Map for OTP Program (The area outside 80H~88H cannot be used.)
Table 5. Bus Operations (1, 2)
NOTE
#RESET
#CE
#OE
#WE
ADDRESS
VPP
DQ0 − 15
6
VIH
VIL
VIL
VIH
X
X
DOUT
Output Disable
VIH
VIL
VIH
VIH
X
X
High Z
Standby
VIH
VIH
X
X
X
X
High Z
MODE
Read Array
Reset
3
VIL
X
X
X
X
X
High Z
Read Identifier
Codes/OTP
6
VIH
VIL
VIL
VIH
See
Table 3, 4
X
See
Table 3, 4
6,7
VIH
VIL
VIL
VIH
See
Appendix
X
See
Appendix
4,5,6
VIH
VIL
VIH
VIL
X
X
DIN
Read Query
Write
Notes:
1. Refer to DC Characteristics. When VPP ≤ VPPLK, memory contents can be read, but cannot be altered.
2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2 for VPP. See DC Characteristics for VPPLK and VPPH1/2
voltages.
3. #RESET at VSS ±0.2V ensures the lowest power consumption.
4. Command writes involving block erase, (page buffer) program or OTP program are reliably executed when VPP = VPPH1/2 and
VDD = 2.7V to 3.6V.
Command writes involving full chip erase are reliably executed when VPP = VPPH1 and VDD = 2.7V to 3.6V.
5. Refer to Table 6 for valid DIN during a write operation.
6. Never hold #OE low and #WE low at the same timing.
7. Refer to Appendix for more information about query code.
-9-
Publication Release Date: March 27, 2003
Revision A3
W28F641B/T
Table 6. Command Definitions(11)
COMMAND
Read Array
BUS
CYCLES
REQ’D.
1
NOTE
FIRST BUS CYCLE
Oper(1)
Addr(2)
Data
Write
PA
FFH
SECOND BUS CYCLE
Oper(1)
Addr(2)
Data(3)
Read Identifier Codes/OTP
≥2
4
Write
PA
90H
Read
Read Query
≥2
2
1
2
2
4
Write
PA
98H
Read
QA
QD
PA
PA
BA
X
PA
SRD
Write
Write
BA
X
D0H
D0H
2
5, 6
Write
WA
70H
50H
20H
30H
40H or
10H
Read
5
5, 9
Write
Write
Write
Write
Write
WA
WD
≥4
5, 7
Write
WA
E8H
Write
WA
N-1
1
8, 9
Write
PA
B0H
1
8, 9
Write
PA
D0H
Write
Write
Write
Write
BA
BA
BA
OA
60H
60H
60H
C0H
Write
Write
Write
Write
BA
BA
BA
OA
01H
D0H
2FH
OD
Write
PCRC
60H
Write
PCRC
04H
Read Status Register
Clear Status Register
Block Erase
Full Chip Erase
Program
Page Buffer Program
Block Erase and (Page Buffer)
Program Suspend
Block Erase and (Page Buffer)
Program Resume
Set Block Lock Bit
Clear Block Lock Bit
Set Block Lock-down Bit
OTP Program
Set Partition configuration
Register
2
2
2
2
2
10
9
IA or OA ID or OD
Notes:
1. Bus operations are defined in Table 5.
2. All address which is written at the first bus cycle should be the same as the address which is written at the second bus cycle.
X = Any valid address within the device.
PA = Address within the selected partition.
IA = Identifier codes address (See Table 3 and Table 4).
QA = Query codes address. Refer to Appendix for details.
BA = Address within the block being erased, set/cleared block lock bit or set block lock-down bit.
WA = Address of memory location for the Program command or the first address for the Page Buffer Program command.
OA = Address of OTP block to be read or programmed (See Figure 3).
PCRC = Partition configuration register code presented on the address A0 − A15.
3. ID = Data read from identifier codes. (See Table 3 and Table 4).
QD = Data read from query database. Refer to Appendix for details.
SRD = Data read from status register. See Table 10 and Table 11 for a description of the status register bits.
WD = Data to be programmed at location WA. Data is latched on the rising edge of #WE or #CE (whichever goes high first)
during command write cycles.
OD = Data within OTP block. Data is latched on the rising edge of #WE or #CE (whichever goes high first) during command
write cycles.
N-1 = N is the number of the words to be loaded into a page buffer.
4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock
configuration code, partition configuration register code and the data within OTP block (See Table 3 and Table 4). The Read
Query command is available for reading CFI (Common Flash Interface) information.
5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block
can be erased or programmed when #RESET is VIH.
6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.
- 10 -
W28F641B/T
7. Following the third bus cycle, inputs the program sequential address and write data of "N" times. Finally, input the any valid
address within the target block to be programmed and the confirm command (D0H). Refer to Appendix for details.
8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the
suspended program operation should be resumed first, and then the suspended erase operation should be resumed next.
9. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be accepted while
the block erase operation is being suspended.
10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when #WP is VIL. When #WP is
VIH, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration.
11. Commands other than those shown above are reserved by Winbond for future device implementations and should not be
used.
Table 7. Functions of Block Lock(5) and Block Lock-Down
CURRENT STATE
ERASE/PROGRAM
ALLOWED(2)
#WP
DQ1(1)
DQ0(1)
0
0
0
Unlocked
Yes
[001]
0
0
1
Locked
No
[011]
0
1
1
Locked-down
No
[100]
State
[000]
(3)
State Name
1
0
0
Unlocked
Yes
(3)
1
0
1
Locked
No
(4)
[110]
1
1
0
Lock-down Disable
Yes
[111]
1
1
1
Lock-down Disable
No
[101]
Notes:
1. DQ0 = 1: a block is locked; DQ0 = 0: a block is unlocked.
DQ1 = 1: a block is locked-down; DQ1 = 0: a block is not locked-down.
2. Erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program
operations.
3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is, [001] (#WP = 0) or [101] (#WP
= 1), regardless of the states before power-off or reset operation.
4. When #WP is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked.
5. OTP (One Time Program) block has the lock function, which is different from those described above.
Table 8. Block Locking State Transitions upon Command Write(4)
CURRENT STATE
RESULT AFTER LOCK COMMAND WRITTEN (NEXT STATE)
State
#WP
DQ1
DQ0
Set Lock(1)
Clear Lock(1)
Set Lock-down(1)
[000]
0
0
0
[001]
No Change
[011](2)
[001]
0
0
1
No Change(3)
[000]
[011]
[011]
0
1
1
No Change
No Change
No Change
[100]
1
0
0
[101]
No Change
[111](2)
[101]
1
0
1
No Change
[100]
[111]
[110]
1
1
0
[111]
No Change
[111](2)
[111]
1
1
1
No Change
[110]
No Change
- 11 -
Publication Release Date: March 27, 2003
Revision A3
W28F641B/T
Notes:
1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit command and "Set Lock-down"
means Set Block Lock-Down Bit command.
2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ0 = 0), the corresponding block is lockeddown and automatically locked at the same time.
3. "No Change" means that the state remains unchanged after the command written.
4. In this state transitions table, assumes that #WP is not changed and fixed VIL or VIH.
Table 9. Block Locking State Transitions upon #WP Transition(4)
RESULT AFTER #WP TRANSITION
(NEXT STATE)
CURRENT STATE
PREVIOUS STATE
(1)
(1)
State
#WP
DQ1
DQ0
[000]
0
0
0
[100]
-
[001]
0
0
1
[101]
-
[110]
-
[011]
0
1
1
[111]
-
-
[100]
1
0
0
-
[000]
-
[101]
1
0
1
-
[001]
-
[110]
1
1
0
-
[011](3)
-
[111]
1
1
1
-
[011]
(2)
[110]
(2)
Other than [110]
#WP = 0→1
#WP = 1→0
Notes:
1. "#WP = 0→1" means that #WP is driven to VIH and "#WP = 1→0" means that #WP is driven to VIL.
2. State transition from the current state [011] to the next state depends on the previous state.
3. When #WP is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked.
4. In this state transitions table, assumes that lock configuration commands are not written in previous, current and next state.
- 12 -
W28F641B/T
Table 10. Status Register Definition
R
R
R
R
R
R
R
R
15
14
13
12
11
10
9
8
WSMS
BESS
BEFCES
PBPOPS
VPPS
PBPSS
DPS
R
7
6
5
4
3
2
1
0
SR.15 − SR.8 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
NOTES:
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
Status Register indicates the status of the partition, not WSM
(Write State Machine). Even if the SR.7 is "1", the WSM may
be occupied by the other partition when the device is set to
2, 3 or 4 partitions configuration.
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
Check SR.7 to determine block erase, full chip erase, (page
buffer) program or OTP program completion. SR.6 − SR.1
are invalid while SR.7 = "0".
SR.5 = BLOCK ERASE AND FULL CHIP ERASE STATUS
(BEFCES)
1 = Error in Block Erase or Full Chip Erase
0 = Successful Block Erase or Full Chip Erase
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase, page buffer program, set/clear block lock bit, set block
lock-down bit, set partition configuration register attempt, an
improper command sequence was entered.
SR.4 = (PAGE BUFFER) PROGRAM AND OTP PROGRAM
STATUS (PBPOPS)
1 = Error in (Page Buffer) Program or OTP Program
0 = Successful (Page Buffer) Program or OTP Program
SR.3 does not provide a continuous indication of VPP level.
The WSM interrogates and indicates the VPP level only after
Block Erase, Full Chip Erase, (Page Buffer) Program or OTP
Program command sequences. SR.3 is not guaranteed to
report accurate feedback when VPP ≠ VPPH1, VPPH2 or VPPLK.
SR.3 = VPP STATUS (VPPS)
1 = VPP LOW Detect, Operation Abort
0 = VPP OK
SR.2 = (PAGE BUFFER) PROGRAM SUSPEND STATUS
(PBPSS)
1 = (Page Buffer) Program Suspended
0 = (Page Buffer) Program in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Erase or Program Attempted on a Locked Block,
Operation Abort
0 = Unlocked
SR.1 does not provide a continuous indication of block lock
bit. The WSM interrogates the block lock bit only after Block
Erase, Full Chip Erase, (Page Buffer) Program or OTP
Program command sequences. It informs the system,
depending on the attempted operation, if the block lock bit is
set. Reading the block lock configuration codes after writing
the Read Identifier Codes/OTP command indicates block
lock bit status.
SR.15 − SR.8 and SR.0 are reserved for future use and
should be masked out when polling the status register.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
- 13 -
Publication Release Date: March 27, 2003
Revision A3
W28F641B/T
Table 11. Extended Status Register Definition
R
R
R
R
R
R
R
R
15
14
13
12
11
10
9
8
SMS
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
XSR.15 − 8 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
XSR.7 = STATE MACHINE STATUS (SMS)
1 = Page Buffer Program available
0 = Page Buffer Program not available
XSR.6-0 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
NOTES:
After issue a Page Buffer Program command (E8H), XSR.7
= "1" indicates that the entered command is accepted. If
XSR.7 is "0", the command is not accepted and a next
Page Buffer Program command (E8H) should be issued
again to check if page buffer is available or not.
XSR.15 − 8 and XSR.6 − 0 are reserved for future use and
should be masked out when polling the extended status
register.
- 14 -
W28F641B/T
Table 12. Partition Configuration Register Definition
R
R
R
R
R
PC2
PC1
PC0
15
14
13
12
11
10
9
8
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
See Figure 4 for the detail on partition configuration.
PCR.15 − 11 and PCR.7 − 0 are reserved for future use
and should be masked out when checking the partition
configuration register.
0
1
PLANE2
PLANE2
1
PLANE0
PARTITION1
PLANE0
PLANE2
PLANE3
PLANE3
PLANE0
PARTITION0
PARTITION3 PARTITION2 PARTITION1 PARTITION0
1
1
1
PLANE0
PLANE1
PLANE0
PARTITION2
PARTITION0
PLANE1
0
PARTITION0
PLANE2
0
0
PARTITION0
PLANE2
1
PLANE3
PARTITION1
1
PLANE3
0
1
PARTITION1 PARTITION0
PARTITION2 PARTITION1
1
PLANE0
1
PLANE2
0
PLANE3
PARTITION1
PLANE1
1
1
PARTITION0
PLANE1
0
PLANE2
0
PLANE3
PARTITION1
0
PLANE0
0
PARTITION2
PLANE1
0
PLANE3
0
PLANE2
PARTITION0
PARTITIONING FOR DUAL WORK
PLANE0
PC2 PC1 PC0
PLANE1
PARTITIONING FOR DUAL WORK
NOTES:
After power-up or device reset, PCR10 − 8 (PC2 − 0) is set
to "001" in a bottom parameter device and "100" in a top
parameter device.
PLANE3
PC2 PC1 PC0
PCR.7 − 0 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
PLANE1
PCR.10 − 8 = PARTITION CONFIGURATION (PC2-0)
000 = No partitioning. Dual Work is not allowed.
001 = Plane1-3 are merged into one partition.
(default in a bottom parameter device)
010 = Plane 0 − 1 and Plane2 − 3 are merged into one
partition respectively.
100 = Plane 0 − 2 are merged into one partition.
(default in a top parameter device)
011 = Plane 2 − 3 are merged into one partition.
There are three partitions in this configuration.
Dual work operation is available between any
two partitions.
110 = Plane 0 − 1 are merged into one partition.
There are three partitions in this configuration.
Dual work operation is available between any
two partitions.
101 = Plane 1 − 2 are merged into one partition.
There are three partitions in this configuration.
Dual work operation is available between any
two partitions.
111 = There are four partitions in this configuration.
Each plane corresponds to each partition respectively.
Dual work operation is available between any two
partitions.
PLANE1
PCR.15 − 11 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
Figure 4. Partition Configuration
- 15 -
Publication Release Date: March 27, 2003
Revision A3
W28F641B/T
4. ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings*
Operating Temperature
During Read, Erase and Program ..................................................................................... -40°C to +85°C(1)
Storage Temperature
During under Bias .............................. .................................................................................. -40°C to +85°C
During non Bias .............................. .................................................................................. .. -65°C to +125°C
Voltage On Any Pin
(except VDD and VPP) ......... .......................................................................................... -0.5V to VDD +0.5V(2)
VDD and VDDQ Supply Voltage......................... ........................................................................ -0.2V to +3.9V(2)
VPP Supply Voltage..................................................................................................... .... -0.2V to +12.6V(2,3,4)
Output Short Circuit Current............. .............................................................................. ...................100 mA(5)
*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress
ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond
the "Operating Conditions" may affect device reliability.
Notes:
1. Operating temperature is for extended temperature product defined by this specification.
2. All specified voltages are with respect to VSS. Minimum DC voltage is -0.5V on input/output pins and -0.2V on VDD and VPP
pins. During transitions, this level may undershoot to -2.0V for periods <20 nS. Maximum DC voltage on input/output pins is
VDD +0.5V, which, during transitions, may overshoot to VDD +2.0V for periods <20 nS.
3. Maximum DC voltage on VPP may overshoot to +13.0V for periods <20 nS.
4. VPP erase/program voltage is normally 2.7V to 3.6V. Applying 11.7V to 12.3V to VPP during erase/program can be done for a
maximum of 1,000 cycles on the main blocks and 1,000 cycles on the parameter blocks. VPP may be connected to 11.7V to
12.3V for a total of 80 hours maximum.
5. Output shorted for no more than one second. No more than one output shorted at a time.
Operating Conditions
SYM.
MIN.
TYP.
MAX.
UNIT
Operating Temperature
PARAMETER
TA
-40
+25
+85
°C
VDD Supply Voltage
VDD
2.7
3.0
3.6
V
1
I/O Supply Voltage
VDDQ
2.7
3.0
3.6
V
1
VPP Voltage when Used as a Logic Control
VPPH1
1.65
3.0
3.6
V
1
VPP Supply Voltage
VPPH2
11.7
12
12.3
V
1, 2
Main Block Erase Cycling: VPP = VPPH1
100,000
Cycles
Parameter Block Erase Cycling: VPP = VPPH1
100,000
Cycles
Main Block Erase Cycling: VPP = VPPH2, 80 hrs.
1,000
Cycles
Parameter Block Erase Cycling: VPP = VPPH2, 80 hrs.
1,000
Cycles
80
Hours
Maximum VPP hours at VPPH2
NOTE
Notes:
1. See DC Characteristics tables for voltage range-specific specification.
2. Applying VPP = 11.7V to 12.3V during a erase or program can be done for a maximum of 1,000 cycles on the main blocks and
1,000 cycles on the parameter blocks. A permanent connection to VPP = 11.7V to 12.3V is not allowed and can cause
damage to the device.
- 16 -
W28F641B/T
Capacitance(1)
TA = +25° C, f = 1 MHz
PARAMETER
SYM.
TYP.
MAX.
UNIT
CONDITION
CIN
6
8
pF
VIN = 0.0V
COUT
10
12
pF
VOUT = 0.0V
Input Capacitance
Output Capacitance
Note: Sampled, not 100% tested.
AC Input/Output Test Conditions
VDDQ
TEST POINTS
VDDQ/2
INPUT
VDDQ/2
OUTPUT
0.0
AC test inputs are driven at VDDQ(min) for a Logic "1" and 0.0V for a Logic "0".
Input timing begins, and output timing ends at VDDQ/2. Input rise and fall times (10% to 90%) < 5 nS.
Worst case speed conditions are when VDD = VDD(min).
Figure 5. Transient Input/Output Reference Waveform for VDD = 2.7V to 3.6V
VDDQ(min)/2
1N914
R L =3.3K ohm
DEVICE
UNDER
TEST
OUT
C L Includes Jig Capacitance
CL
Figure 6. Transient Equivalent Testing Load Circuit
Table 13. Configuration Capacitance Loading Value
TEST CONFIGURATION
CL(PF)
VDD = 2.7V to 3.6V
50
- 17 -
Publication Release Date: March 27, 2003
Revision A3
W28F641B/T
DC Characteristics
PARAMETER
SYM.
TEST CONDITIONS
Input Load Current
(note 1)
ILI
Output Leakage Current
(note1)
ILO
VDD Standby Current
(note 1)
ICCS
VDD = VDD Max. #CE =
#RESET = VDDQ ±0.2V,
#WP = VDDQ or VSS
VDD Automatic Power Saving Current
(note 1, 4)
ICCAS
VDD Reset Power-Down Current
(note 1)
VDD = 2.7V to 3.6V
Min.
Typ.
Max.
UNIT
-1.0
+1.0
µA
-1.0
+1.0
µA
4
20
µA
VDD = VDD Max. #CE = VSS
±0.2V, #WP = VDDQ or VSS
4
20
µA
ICCD
#RESET = VSS ±0.2V
4
20
µA
15
25
mA
ICCR
VDD = VDD Max.,
#CE = VIL, #OE = VIH,
f = 5 MHz
5
10
mA
VPP = VPPH1
20
60
mA
VPP = VPPH2
10
20
mA
VPP = VPPH1
10
30
mA
VPP = VPPH2
10
30
mA
ICCWS
ICCES
#CE = VIH
10
200
µA
VPP Standby or Read Current
(note 1, 6, 7)
IPPS
IPPR
VPP ≤ VDD
2
5
µA
VPP (Page Buffer) Program Current
(note 1, 5, 6, 7)
IPPW
VPP = VPPH1
2
5
µA
VPP = VPPH2
10
30
mA
VPP Block Erase, Full Chip Erase
Current (note 1, 5, 6, 7)
IPPE
VPP = VPPH1
2
5
µA
VPP = VPPH2
5
15
mA
VPP = VPPH1
2
5
µA
VPP = VPPH2
10
200
µA
VPP = VPPH1
2
5
µA
VPP = VPPH2
10
200
µA
Average VDD Read Current
Normal Mode (note1, 7)
Average VDD Read Current
Page Mode (note1, 7)
8 Word
Read
VDD (Page Buffer) Program Current
(note 1, 5, 7)
ICCW
VDD Block Erase, Full Chip Erase
Current (note 1, 5, 7)
ICCE
VDD (Page Buffer) Program or Block
Erase Suspend Current (note 1, 2, 7)
VPP (Page Buffer) Program Suspend
Current (note 1, 6, 7)
IPPWS
VPP Block Erase Suspend Current (note
IPPES
1, 6, 7)
VDD = VDD Max.,
VDDQ = VDDQ Max.,
VIN/VOUT = VDDQ or VSS
- 18 -
W28F641B/T
DC Characteristics, continued
PARAMETER
SYM.
TEST
CONDITIONS
VDD = 2.7V − 3.6V
Min.
Typ.
Max.
UNIT
Input Low Voltage (note 5)
VIL
-0.4
0.4
V
Input High Voltage (note 5)
VIH
2.4
VDDQ
+0.4
V
Output Low Voltage (note 5)
VOL
VDD = VDD Min., VDDQ =
VDDQ Min., IOL = 100 µA
0.2
V
Output High Voltage (note 5)
VOH
VDD = VDD Min., VDDQ =
VDDQ Min., IOH = -100 µA
VDDQ
-0.2
VPP Lockout during Normal Operations
(note 3, 5, 6)
VPPLK
VPP during Block Erase, Full Chip
Erase, (Page Buffer) Program or OTP
Program Operations (note 6)
VPPH1
1.65
VPP during Block Erase, (Page Buffer)
Program or OTP Program Operations
(note 6)
VPPH2
11.7
VDD Lockout Voltage
VLKO
1.5
V
0.4
V
3.0
3.6
V
12
12.3
V
V
Notes:
1. All currents are in RMS unless otherwise noted. Typical values are the reference values at VDD = 3.0V and TA = +25° C unless
VDD is specified.
2. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program is executed while in block erase
suspend mode, the device's current draw is the sum of ICCES and ICCR or ICCW . If read is executed while in (page buffer)
program suspend mode, the device’s current draw is the sum of ICCWS and ICCR.
3. Block erases, full chip erase, (page buffer) program and OTP program are inhibited when VPP ≤ VPPLK, and not guaranteed in
the range between VPPLK (max.) and VPPH1 (min.), between VPPH1 (max.) and VPPH2 (min.) and above VPPH2 (max.).
4. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle completion.
Standard address access timings (tAVQV) provide new data when address are changed.
5. Sampled, not 100% tested.
6. VPP is not used for power supply pin. With VPP ≤ VPPLK, block erase, full chip erase, (page buffer) program and OTP program
cannot be executed and should not be attempted.
Applying 12V ±0.3V to V VPP provides fast erasing or fast programming mode. In this mode, VPP is power supply pin and
supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths and
layout considerations given to the VDD power bus.
Applying 12V ±0.3V to VPP during erase/program can only be done for a maximum of 1,000 cycles on each block. VPP may be
connected to 12V ±0.3V for a total of 80 hours maximum.
7. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane.
- 19 -
Publication Release Date: March 27, 2003
Revision A3
W28F641B/T
AC Characteristics - Read-only Operations(1)
VDD = 2.7V to 3.6V, TA = -40°C to +85°C
PARAMETER
SYM.
MIN.
Read Cycle Time
tAVAV
80
Address to Output Delay
tAVQV
80
nS
#CE to Output Delay (note 3)
tELQV
80
nS
Page Address Access Time
tAPA
35
nS
#OE to Output Delay (note 3)
tGLQV
20
nS
#RESET High to Output Delay
tPHQV
150
nS
tEHQZ, tGHQZ,
20
nS
#CE or #OE to Output in High Z, whichever Occurs First (note 2)
MAX.
UNIT
nS
#CE to Output in Low Z (note 2)
tELQX
0
nS
#OE to Output in Low Z (note 2)
tGLQX
0
nS
tOH
0
nS
Address Setup to #CE, #OE, Going Low for Reading Status
Register (note 4,6)
tAVEL, tAVGL
10
nS
Address Hold from #CE, #OE, Going Low for Reading Status
Register (note 5,6)
tELAX, tGLAX
30
nS
#CE, #OE Pulse Width High for Reading Status Register (note 6)
tEHEL, tGHGL
30
nS
Output Hold from first Occurring Address, #CE or #OE Change
(note 2)
Notes:
1. See AC Input/Output Reference Waveform for timing measurements and maximum allowable input slew rate.
2. Sampled, not 100% tested.
3. #OE may be delayed up to tELQV to tGLQV after the falling edge of #CE without impact to tELQV.
4. Address setup time (tAVEL to tAVGL) is defined from the falling edge of #CE or #OE (whichever goes low last).
5. Address hold time (tELAX to tGLAX) is defined from the falling edge of #CE or #OE (whichever goes low last).
6. Specifications tAVEL, tAVGL, tELAX, tGLAX, and tEHEL,, tGHGL for read operations apply to only status register read operations.
- 20 -
W28F641B/T
VIH
A21-0(A)
Vaild Address
VIL
t AVAV
t AVQV
VIH
#CE(E) V
IL
tEHQZ
tGHQZ
tEHEL
tAVEL
t ELAX
t AVGL
t GLAX
t GHGL
#OE(G)
#WE(W)
VIH
VIL
t ELQV
VIH
t GLQV
VIL
tGLQX
t OH
t ELQX
VOH
DQ15-0 (D/Q)
VOL
HIGH Z
Valid Output
t PHQV
#RESET(P)
VIH
VIL
Figure 7. AC Waveform for Single Asynchronous Read Operations from Status Register,
Identifier codes, OTP Block or Query Code
- 21 -
Publication Release Date: March 27, 2003
Revision A3
W28F641B/T
A21-3(A)
VIH
Valid Address
VIL
t AVQV
A2-0(A)
VIH
VIL
Valid
Address
Valid Address
Valid
Address
Valid
Address
VIH
#CE(E)
VIL
t EHQZ
t GHQZ
t ELQV
#OE(G)
#WE(W)
DQ15-0 (D/Q)
VIH
VIL
VIH
t GLQV
VIL
VOH
t OH
tAPA
tGLQX
t ELQX
HIGH Z
Valid
Address
VOL
Valid
Address
Valid
Address
Valid
Address
t PHQV
#RESET(P)
VIH
VIL
Figure 8. AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks or Parameter Blocks
- 22 -
W28F641B/T
AC Characteristics - Write Operations(1, 2)
VDD = 2.7V to 3.6V, TA = -40°C to +85°C
PARAMETER
SYMBOL
MIN.
tAVAV
80
nS
#RESET High Recovery to #WE(#CE) Going Low (note 3)
tPHWL(tPHEL)
150
nS
#CE(#WE) Setup to #WE(#CE) Going Low
tELWL(tWLEL)
0
nS
#WE(#CE) Pulse Width (note 4)
tWLWH(tELEH)
50
nS
Data Setup to #WE(#CE) Going High (note 8)
tDVWH(tDVEH)
40
nS
Address Setup to #WE(#CE) Going High (note 8)
tAVWH(tAVEH)
50
nS
#CE(#WE) Hold from #WE(#CE) High
tWHEH(tEHWH)
0
nS
Data Hold from #WE(#CE) High
tWHDX(tEHDX)
0
nS
Address Hold from #WE(#CE) High
tWHAX(tEHAX)
0
nS
#WE(#CE) Pulse Width High (note 5)
tWHWL(tEHEL)
30
nS
#WP High Setup to #WE(#CE) Going High (note 3)
tSHWH(tSHEH)
0
nS
VPP Setup to #WE(#CE) Going High (note 3)
tVVWH(tVVEH)
200
nS
Write Recovery before Read
tWHGL(tEHGL)
30
nS
#WP High Hold from Valid SRD (note 3,6)
tQVSL
0
nS
VPP Hold from Valid SRD (note 3,6)
tQVVL
0
nS
Write Cycle Time
#WE(#CE) High to SR.7 Going "0" (note 3,7)
tWHR0(tEHR0)
MAX.
tAVQV+50
UNIT
nS
Notes:
1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and OTP
program operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations.
2. A write operation can be initiated and terminated with either #CE or #WE.
3. Sampled, not 100% tested.
4. Write pulse width (tWP) is defined from the falling edge of #CE or #WE (whichever goes low last) to the rising edge of #CE or
#WE (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.
5. Write pulse width high (tWPH) is defined from the rising edge of #CE or #WE (whichever goes high first) to the falling edge of
#CE or #WE (whichever goes low last). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
6. VPP should be held at VPP = VPPH1/2 until determination of block erase, (page buffer) program or OTP program success
(SR.1/3/4/5 = 0) and held at VPP = VPPH1 until determination of full chip erase success (SR.1/3/5 = 0).
7. tWHR0 (tEHR0) after the Read Query or Read Identifier Codes/OTP command = tAVQV+100 nS.
8. Refer to Table 6 for valid address and data for block erase, full chip erase, (page buffer) program, OTP program or lock bit
configuration.
- 23 -
Publication Release Date: March 27, 2003
Revision A3
W28F641B/T
A21-0(A)
#CE(E)
#OE(G)
#WE(W)
V IH
Note 1
Note 2
V IL
Valid Address
Valid Address
t AVAV
t AVWH (t AVEH )
V IL
t WHAX (t EHAX )
Note 5,6
t ELWL (t WLEL)
t WHEH (t EHWH )
t WHGL (t EHGL)
V IH
V IL
Note 5
Valid Address
V IH
t PHWL (t PHEL)
Note 5,6
t WHWL (t EHEL)
V IH
V IL
t DVWH (t DVEH)
t WLWH (t ELEH)
DQ15-0(D/Q)
Note 4
Note 3
V IH
V IL
t WHQV1,2,3 (t EHQV1,2,3)
t WHDX (t EHDX)
D IN
Valid
D IN
SRD
t WHR0 (t EHR0)
("1")
SR.7(R)
#RESET(P)
#WP(S)
("0")
V IH
V IL
t SHWH(t SHEH)
t QVSL
t VVWH(t VVEH)
t QVVL
V IH
V IL
VPPH1,2
VPP (V)
V PPLK
V IL
Figure 9. AC Waveform for Write Operations
Notes:
1. VDD power-up and standby.
2. Write each first cycle command.
3. Write each second cycle command or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. For read operation, #OE and #CE must be driven active, and #WE de-asserted.
- 24 -
W28F641B/T
Reset Operations
t PHQV
#RESET(P)
DQ15-0(D/Q)
VIH
VIL
VOH
VOL
t PLPH
High Z
t PLRH
#RESET(P)
DQ15-0(D/Q)
Valid Output
(A)Reset During Read Array Mode
SR.7="1"
Abort
Complete
t PHQV
VIH
VIL
VOH
VOL
t PLPH
High Z
Valid Output
(B)Reset During Erase or Program Mode
VDD (min)
VDD
Vss
t VHQV
t PHQV
t 2VPH
#RESET(P)
DQ15-0(D/Q)
VIH
V IL
VOH
High Z
Valid Output
VOL
(C)#RESET Rising Timing
Figure 10. AC Waveform for Reset Operation
Reset AC Specifications
VDD = 2.7V to 3.6V, TA = -40°C to +85°C
PARAMETER
#RESET Low to Reset during Read
(#RESET should be low during power-up.) (note 1, 2, 3)
SYM.
MIN.
tPLPH
100
#RESET Low to Reset during Erase or Program (note 1, 3, 4)
tPLRH
VDD 2.7V to #RESET High (note 1, 3, 5)
t2VPH
VDD 2.7V to Output Delay (note 3)
tVHQV
- 25 -
MAX.
UNIT
nS
22
100
µS
nS
1
mS
Publication Release Date: March 27, 2003
Revision A3
W28F641B/T
Notes:
1. A reset time, tPHQV, is required from the later of SR.7 going "1" or #RESET going high until outputs are valid. Refer to AC
Characteristics - Read-Only Operations for tPHQV.
2. tPLPH is <100 nS the device may still reset but this is not guaranteed.
3. Sampled, not 100% tested.
4. If #RESET asserted while a block erase, full chip erase, (page buffer) program or OTP program operation is not executing,
the reset will complete within 100 nS.
5. When the device power-up, holding #RESET low minimum 100ns is required after VDD has been in predefined range and also
has been in stable there.
Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program
Performance(3)
VDD = 2.7V to 3.6V, TA = -40°C to +85°C
PARAMETER
SYM.
4K-Word Parameter Block
Program Time (note 2)
tWPB
32K-Word Main Block
Program Time (note 2)
tWMB
PAGE BUFFER
VPP = VPPH1
VPP = VPPH2
COMMAND IS
(IN SYSTEM)
(IN MANUFACTURING) UNIT
USED OR NOT
(1)
(2)
MIN. TYP.(1) MAX.(2)
MIN. TYP. MAX.
USED
Not Used
0.05
0.3
0.04
0.12
S
Used
0.03
0.12
0.02
0.06
S
Not Used
0.38
2.4
0.31
1.0
S
Used
0.24
1.0
0.17
0.5
S
Not Used
11
200
9
185
µS
Used
7
100
5
90
µS
Word Program Time (note 2)
tWHQV1/
tEHQV1
OTP Program Time (note 2)
tWHOV1/
tEHOV1
Not Used
36
400
27
185
µS
4K-Word Parameter Block
Erase Time (note 2)
tWHQV2/
tEHQV2
-
0.3
4
0.2
4
S
32K-Word Main Block Erase
Time (note 2)
tWHQV3/
tEHQV3
-
0.6
5
0.5
5
S
80
700
Full Chip Erase Time (note 2)
(Page Buffer) Program
Suspend Latency Time to
Read (note 4)
S
tWHRH1/
tEHRH1
-
5
10
5
10
µS
Block Erase Suspend Latency tWHRH2/
Time to Read (note 4)
tEHRH2
-
5
20
5
20
µS
Latency Time from Block
Erase Resume Command to
Block Erase Suspend
Command (note 5)
-
TERES
500
500
µS
Notes:
1. Typical values measured at VDD = 3.0V, VPP = 3.0V or 12V, and TA = +25°C. Assumes corresponding lock bits are not set.
Subject to change based on device characterization.
2. Excludes external system-level overhead.
3. Sampled, but not 100% tested.
- 26 -
W28F641B/T
4. A latency time is required from writing suspend command (#WE or #CE going high) until SR.7 going "1".
5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than
tERES and its sequence is repeated, the block erase operation may not be finished.
5. ADDITIONAL INFORMATION
Recommended Operating Conditions
At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at
device power-up. If the timing in the figure is ignored, the device may not operate correctly.
VDD
#RESET (p)
Vpp
*1
Vss
(E)
#WE (W)
#OE
(G)
#WP
(S)
DATA (D/Q)
tVR
t 2VPH
t PHQV
VIH
V IL
(V) V PPH1/2
Vss
ADDRESS (A)
#CE
VDD (min)
VIH
tAVQV
tR or tF
tR or tF
Valid Address
VIL
tF
VIH
t ELQV
tR
VIL
VIH
VIL
tF
t GLQV
tR
VIH
VIL
VIH
VIL
VOH
VOL
HIGH Z
Valid Output
*1 To prevent the unwanted writes, system designers should consider the design, which applies VPP to 0V during read
operations and VPPH1/2 during write or erase operations.
Figure A-1. AC Timing at Device Power-up
For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the “ELECTRICAL SPECIFICATIONS“ described in
specifications for the supply voltage range, the operating temperature and the AC specifications not shown in the next page.
- 27 -
Publication Release Date: March 27, 2003
Revision A3
W28F641B/T
Rise and Fall Time
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
VDD Rise Time (note 1)
tVR
0.5
30000
µS/ V
Input Signal Rise Time (note1, 2)
tR
1
µS/ V
Input Signal Fall Time (note1, 2)
tF
1
µS/ V
Notes:
1. Sampled, not 100% tested.
2. This specification is applied for not only the device power-up but also the normal operations.
Glitch Noises
Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset,
and control signals, as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure
A-2 (a).
Input Singal
Input Singal
VIH(Min.)
VIH(Min.)
VIL (Max.)
VIL (Max.)
Input Singal
Input Singal
(a) Acceptable Glitch Noises
(b) NOT Acceptable Glitch Noises
Figure A-2. Waveform for Glitch Noises
See the "DC CHARACTERISTICS" described in specifications for VIH (Min.) and VIL (Max.).
- 28 -
W28F641B/T
6. ORDERING INFORMATION
ACCESS
TIME
OPERATING
TEMPERATURE
(nS)
(°C)
W28F641BT80L
80
-40º C to 85° C
Bottom Boot
48-Pin TSOP
W28F641BB80L
80
-40º C to 85º C
Bottom Boot
48-Ball TFBGA
W28F641TT80L
80
-40º C to 85° C
Top Boot
48-Pin TSOP
W28F641TB80L
80
-40º C to 85º C
Top Boot
48-Ball TFBGA
PART NO.
BOOT BLOCK
PACKAGE
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
- 29 -
Publication Release Date: March 27, 2003
Revision A3
W28F641B/T
7. PACKAGE DIMENSIONS
48-pin Standard Thin Small Outline Package (measured in millimeters)
1
48
MILLIMETER
INCH
Sym. MIN. NOM.
MAX. MIN. NOM. MAX.
e
E
b
c
D
HD
0.05
A2
0.95
1.00
1.05
0.037 0.039 0.041
D
18.3
18.4
18.5
0.720 0.724 0.728
HD
19.8
20.0
20.2
0.780 0.787 0.795
E
11.9
12.0
12.1
0.468 0.472 0.476
b
c
0.17
0.22
0.27 0.007 0.009 0.011
0.50
A
A1
L1
0.020
0.70
0.60
0.031
0.004
0.10
Y
θ
Y
0.020 0.024 0.028
0.80
L1
0.008
0.21 0.004
0.50
L
θ L
0.002
0.10
e
A2
0.047
1.20
A
A1
0
5
0
5
48-ball TFBGA (8 mm x 11 mm) (measurements in millimeters)
CONTROL DIMENSIONS ARE IN MILLIMETERS
b
1
2
3
4
5
6
MIN. NOM. MAX.
H
G
F
E
D
C
B
A
-
A
e
D2 D
7.80
8.00
8.20 0.312 0.320 0.328
3.75 BASIC
0.150 BASIC
10.80 11.00 11.20 0.400 0.440 0.480
e
- 30 -
0.042
D
b
A1
-
0.30 0.008 0.010 0.012
y
SEATING PLANE
-
0.25
E2
A
1.05
0.20
E
E2
E
-
MIN. NOM. MAX.
A1
D2
e
INCH
MILLIMETER
SYMBOL
5.25 BASIC
0.210
0.10 BASIC
0.37
0.40
0.75 BASIC
0.004 BASIC
0.43 0.015 0.016 0.017
0.030 BASIC
W28F641B/T
8. VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A1
Jan. 7, 2003
-
A2
Feb. 17, 2003
29
Modify TFBGA Package Dimension drawing
A3
March 27, 2003
All
Typo Correction
Initial Issued
Headquarters
Winbond Electronics Corporation America
Winbond Electronics (Shanghai) Ltd.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
TEL: 86-21-62365999
FAX: 86-21-62365998
Taipei Office
Winbond Electronics Corporation Japan
Winbond Electronics (H.K.) Ltd.
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
TEL: 81-45-4781881
FAX: 81-45-4781800
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 31 -
Publication Release Date: March 27, 2003
Revision A3