WCMA1008C1X 128K x 8 Static RAM Features • Voltage Range — 4.5V–5.5V • Low active power — Typical active current: 6 mA @ f = fmax (70 ns speed) • Low standby current • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE1, CE2, and OE features • CMOS for optimum speed/power Functional Description The WCMA1008C1X is a high-performance CMOS static RAM organized as 128K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and three-state drivers. This device has an automatic power-down feature that reduces power consumption by more than 75% when deselected. Writing to the device is accomplished by taking Chip Enable 1 (CE1) and Write Enable (WE) inputs LOW and Chip Enable 2 (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable 1 (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable 2 (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW) The WCMA1008C1X is available in a standard 32-pin 450-mil-wide body width SOIC and 32-pin TSOP type I. Logic Block Diagram Pin Configuration Top View SOIC INPUT BUFFER 512x 256x 8 ARRAY SENSE AMPS I/O 1 ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND I/O 0 I/O 2 I/O 3 I/O 4 I/O 5 OE COLUMN DECODER POWER DOWN I/O 6 I/O 7 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 CE1 CE2 WE A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TSOP I Top View (not to scale) VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 6 I/O I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 April 5, 2002 WCMA1008C1X Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND ....... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] .....................................–0.5V to VCC +0.5V DC Input Voltage[1]..................................–0.5V to VCC +0.5V Current into Outputs (LOW) .........................................20 mA Static Discharge Voltage...............................................2001V (per MIL-STD-883, Method 3015) Latch-Up Current .....................................................>200 mA Product Portfolio Power Dissipation Operating, Icc VCC Range Product WCMA1008C1X Standby (ISB2) f = fmax Min. Typ.[2] Max. 4.5 V 5.0V 5.5V Speed Temp. 70 ns 55 ns Ind’l Typ.[2] Max. 6 mA 15 mA 7.5 mA 20 mA Typ.[2] Max. 4 µA 20 µA Operating Range Range Industrial Ambient Temperature VCC –40°C to +85°C 4.5V–5.5V Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. Typical values are measured at VCC = 5V, TA = 25°C, and are included for reference only and are not tested or guaranteed. Page 2 of 11 WCMA1008C1X Electrical Characteristics Over the Operating Range WCMA1008C1X-55 Parameter Description Test Conditions Min. Typ. [2] WCMA1008C1X-70 Max. VOH Output HIGH Voltage VCC = Min., IOH = – 1 mA VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA VIH Input HIGH Voltage 2.2 VCC +0.3 VIL Input LOW Voltage –0.3 IIX Input Leakage Current GND ≤ VI ≤ VCC IOZ Output Leakage Current GND ≤ VI ≤ VCC, Output Disabled ICC VCC Operating Supply Current f=fMAX=1/tRC ISB1 Automatic CE Power-Down Current —TTL Inputs ISB2 Automatic CE Power-Down Current —CMOS Inputs Min. 2.4 Typ.[2] Max. Units 2.4 V 0.4 0.4 V 2.2 VCC +0.3 V 0.8 –0.3 0.8 V –1 +1 –1 +1 µA –1 +1 –1 +1 µA IOUT =0 mA VCC = Max., 7.5 20 6 15 mA Max. VCC,CE1≥VIH,CE2<VIH VIN ≥ VIH or VIN ≤ VIL, f = fMAX 0.1 2 0.1 1 mA Max. VCC, CE1 ≥ VCC – 0.3V,CE2 <0.3 VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, f =0 2.5 15 15 µA Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 9 pF 9 pF AC Test Loads and Waveforms R1 1800Ω R1 1800 Ω 5V ALL INPUT PULSES 5V OUTPUT 100 pF INCLUDING JIG AND SCOPE (a) OUTPUT R2 5 pF 990 Ω INCLUDING JIG AND SCOPE (b) 3.0V 90% R2 990 Ω GND ≤ 3 ns 10% 90% 10% ≤ 3 ns Equivalent to: THEVENIN EQUIVALENT 639 Ω 1.77V OUTPUT Note: 3. Tested initially and after any design or process changes that may affect these parameters. Page 3 of 11 WCMA1008C1X Switching Characteristics[4] Over the Operating Range 55 Parameter Description Min. 70 Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid 55 tOHA Data Hold from Address Change tACE CE1 LOW to Data Valid, CE2 HIGH to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z[5] 5 OE HIGH to High tLZCE CE1 LOW to Low Z, CE2 HIGH to Low Z[5] tHZCE CE1 HIGH to High Z, CE2 LOW to High Z[5, 6] tPU CE1 LOW to Power-Up, CE2 HIGH to Power-Up tPD CE1 HIGH to Power-Down, CE2 LOW to Power-Down ns 70 5 55 20 0 Z[5, 6] tHZOE 70 55 ns 70 ns 35 ns 0 20 5 ns 25 5 20 0 ns ns 25 0 55 ns ns ns 70 ns WRITE CYCLE[7] tWC Write Cycle Time 55 70 ns tSCE CE1 LOW to Write End, CE2 HIGH to Write End 45 60 ns tAW Address Set-Up to Write End 45 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 45 50 ns tSD Data Set-Up to Write End 25 30 ns tHD Data Hold from Write End 0 0 ns 5 5 ns tLZWE tHZWE WE HIGH to Low Z[5, 6] WE LOW to High Z[6] 20 25 ns Notes: 4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. The internal write time of the memory is defined by the overlap of CE1 LOW and CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. Page 4 of 11 WCMA1008C1X Data Retention Characteristics (Over the Operating Range) Parameter VDR Description Conditions VCC for Data Retention Min. Typ.[2] Max. 2.0 VCC = VDR = 3.0V, CE1 ≥ VCC – 0.3V, CE2 < 0.3V VIN ≥ VCC – 0.3V or, VIN ≤ 0.3V Unit V 1.5 20 µA ICCDR Data Retention Current tCDR[3] Chip Deselect to Data Retention Time 0 ns tR[8] Operation Recovery Time 70 ns Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR VDR > 2V 3.0V tR CE Page 5 of 11 WCMA1008C1X Switching Waveforms Read Cycle No.1[9, 10] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[10, 11] ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tHZCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU 50% ICC 50% ISB Notes: 8. Full Device operatin requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at Vcc(min) > 100 µs. 9. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. Page 6 of 11 WCMA1008C1X Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[7. 12, 13] tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 14 tHZOE Write Cycle No. 2 (CE1 or CE2 Controlled)[7, 12, 13] tWC ADDRESS tSCE CE1 tSA CE2 tAW tHA tPWE WE OE tSD DATA I/O tHD DATAIN VALID Notes: 12. If CE1 goes HIGH and CE2 LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. 13. Data I/O is high-impedance if OE = VIH. 14. During this period the I/Os are in the output state and input signals should not be applied. Page 7 of 11 WCMA1008C1X Switching Waveforms (continued) Write Cycle No.3 (WE Controlled, OE LOW)[12] tWC ADDRESS tSCE CE1 CE2 tSCE tAW tSA tHA tPWE WE tSD NOTE 14 DATAI/O tHD DATA VALID tLZWE tHZWE Truth Table CE1 CE2 OE WE I/O0 – I/O7 Mode Power H X X X High Z Power-Down Standby (ISB) X L X X High Z Power-Down Standby (ISB) L H L H Data Out Read Active (ICC) L H X L Data In Write Active (ICC) L H H H High Z Selected, Outputs Disabled Active (ICC) Page 8 of 11 WCMA1008C1X Ordering Information Speed (ns) 70 55 Ordering Code Package Name Package Type WCMA1008C1X-GF70 G32 32-Lead (450-Mil) Molded SOIC WCMA1008C1X-TF70 T32 32-Lead TSOP WCMA1008C1X-GF55 G32 32-Lead (450-Mil) Molded SOIC WCMA1008C1X-TF55 T32 32-Lead TSOP Operating Range Industrial Package Diagrams 32-Lead (450 MIL) Molded SOIC, G32 Page 9 of 11 WCMA1008C1X Package Diagrams (continued) 32-Lead Thin Small Outline Package T32 Page 10 of 11 WCMA1008C1X Document Title: WCMA1008C1X, 128K x 8 Static RAM REV. Spec # ECN # Issue Date Orig. of Change ** 38-14022 115241 4/24/2002 MGN Description of Change New Datasheet Page 11 of 11