XRD6414 CMOS 10-Bit, 20 MSPS, High Speed Analog-to-Digital Converter ...the analog plus company TM with 4:1 Input Analog Multiplexer March 1997–3 FEATURES APPLICATIONS 10-Bit Resolution Multiplexed Data Acquisition 20MHz Sampling Rate Precision Scanners 4:1 Analog Input Multiplexer Digital Color Copiers Internal S/H Function Test and Scientific Instruments Single 5.0V Power Supply Digital Cameras VIN DC Range: 0V to VDD Medical Imaging IR Imaging VREF DC Range: 1V to VDD Low Power: 120mW (typ) BENEFITS Three-State Digital Outputs Power Down: 1.5mW (typ) Power Dissipation Complete Analog-to-Digital Converter (ADC) that Requires no External Active Components ESD Protection: 2000V Minimum Small Outline Package to Reduce Board Space For 3V Operation Refer to XRD64L14 Low Power Dissipation Easy to Use Rugged Design GENERAL DESCRIPTION The XRD6414 is a 10-bit, 20 MSPS, Analog-to-Digital Converter (ADC) with a 4:1 Analog Input Multiplexer for applications that require high speed and high accuracy. Designed using an advanced CMOS process, this part offers excellent performance, low power consumption and latch-up free operation. The XRD6414 uses a subranging architecture to maintain low power consumption at high conversion rates. Our proprietary comparator design achieves a low analog input capacitance. The input circuitry of the XRD6414 includes an on-chip S/H function that allows the product to digitize analog input signals between AGND and AVDD. The XRD6414 can be placed into power down (stand-by) mode, reducing the power dissipation to 1.5mW (typical) by a digitally controlled pin. Providing external reference voltages allows easy interface to any input signal range between AGND and AVDD. This also allows the system to calibrate out zero scale and full scale errors by adjusting VRT and VRB. A separate power supply pin, DVDD, sets the output logic levels for 3V or 5V interface. This device operates from a single 5.0V supply. Power consumption from a 5.0V supply is typically 120mW at FS=15MHz. For 3.3V power supply operation refer to XRD64L14. ORDERING INFORMATION Part No. Package Operating Temperature Range XRD6414AIQ 32 Lead TQFP (7 x 7 x 1.4 mm) –40°C to +85°C Rev. 1.00 1996 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017 XRD6414 AVDD(3) DVDD AGND(3) VRT DGND Latched MSB Comparators OFW DB9 (MSB) Encoder and Error Correction RL 11 F/F Latched LSB Comparators DB0 (LSB) VRB VIN AOUT AIN1 AIN2 AIN3 AIN4 THA Clock and Control Logic 4:1 MUX A1 A0 CLK PD Figure 1. Simplified Block Diagram PIN CONFIGURATION 24 17 25 16 32 9 1 8 32 Lead TQFP (7 x 7 x 1.4 mm) Rev. 1.00 2 OE XRD6414 PIN DESCRIPTION Pin # Symbol 1 DB9 Description Data Output Bit 9 (MSB) 2 DGND Ground (Digital Outputs) 3 AGND Ground 4 A0 MUX Select Bit 0 5 A1 MUX Select Bit 1 6 AVDD Power Supply 7 CLK Sampling Clock Input 8 OE Output Enable Control 9 PD Power Down Control 10 AVDD Power Supply 11 AGND Ground 12 VRT Top of Reference Ladder 13 VRB Bottom of Reference Ladder 14 AIN4 MUX Analog Signal Input 4 15 AIN3 MUX Analog Signal Input 3 16 AGND 17 AIN2 MUX Analog Signal Input 2 18 AIN1 MUX Analog Signal Input 1 19 AOUT MUX Analog Signal Output 20 VIN 21 AVDD Power Supply 22 DVDD Power Supply (Digital Outputs) 23 OFW Overflow Output 24 DB0 Data Output Bit 0 (LSB) 25 DB1 Data Output Bit 1 26 DB2 Data Output Bit 2 27 DB3 Data Output Bit 3 28 DB4 Data Output Bit 4 29 DB5 Data Output Bit 5 30 DB6 Data Output Bit 6 31 DB7 Data Output Bit 7 32 DB8 Data Output Bit 8 Ground Analog Input Voltage to ADC Rev. 1.00 3 XRD6414 ELECTRICAL CHARACTERISTICS Unless Otherwise Specified: AVDD = DVDD = 5.0V, FS = 15MHz (50% Duty Cycle), VRT = 5.0V, VRB = 0.0V, TA = 25°C Symbol Parameter Min. Typ. Max. Unit 20 15 MSPS Conditions Key Features n Resolution FS Maximum Sample Rate 10 Bits DC Accuracy1 DNL Differential Non-Linearity –0.8 0.6 1.0 LSB INL Integral Non-Linearity –2.5 1.5 2.5 LSB EZS Zero Scale Error 0 20 40 mV EFS Full Scale Error –1.0 0.4 1.0 % VINPP DC Input Range AGND AVDD V Best Fit Line (Max INL – Min INL)/2 VIN can swing from AGND to AVDD, actual digitized range is set by VRT & VRB. Reference Voltages VRT Top Reference Voltage VRB Bottom Reference Voltage VREF RL Differential Ref. Voltage2 Ladder Resistance 1.0 2.5 AVDD V AGND 0.5 AVDD–1 V 1.0 2 AVDD V 350 500 650 Ω VRT V Analog Input3 Input Voltage Range BW CIN CIN Input Bandwidth (–1dB)4 VRB VRB min. = AGND VRT max = AVDD 50 MHz Input Capacitance Sample5 20 pF CLK = low Input Capacitance Convert5 7 pF CLK = high Analog Multiplexer RON Switch Impedance 60 120 Ω ROFF Switch Impedance 10 5 MΩ TSW Switching Time 15 ns Crosstalk –80 dB Xt fIN = 6MHz Conversion Character tAP Aperture Delay 6 ns tAJ Aperture Jitter 30 ps 57 dB FS = 10MSPS 56 dB FS = 10MSPS Dynamic SNR Signal-to-Noise Ratio FIN = 1MHz SNDR SNR and Distortion FIN = 1MHz Rev. 1.00 4 XRD6414 ELECTRICAL CHARACTERISTICS (CONT’D) Symbol Parameter Min. Typ. Max. Unit Conditions Digital Inputs VIH Digital Input High Voltage VIL Digital Input Low Voltage IIN DC Leakage 3.5 V 1.5 V Currents6 CLK, OE, PD, A0, A1 Input Capacitance 5 A 5 pF Between AGND and AVDD Digital Outputs VOH Output High Voltage 4.5 VOL Output Low Voltage IOZ High-Z Leakage –10 tDL Data Valid Delay2 10 tDEN Data Enable Delay tDHZ Data High-Z Delay V 0.4 V 10 A 12 14 ns 10 12 14 ns 7 8 9 ns Pipeline Delay (Latency) 3 cycles OE = high, or PD = high Time delay between CLK and data output Power Supplies IDD(PD) Power Down (IDD) AVDD Operating Voltage7,8 4.5 DVDD Supply9 2.7 IDD Logic Power Supply Current (IDD) 0.3 0.5 mA 5.0 5.5 V 5.5 V 32 mA 24 PD = high, excluding current through reference ladder PD = low Notes 1 Tester measures code transitions by dithering the voltage of the analog input (V ). The difference between the measured and the IN ideal code width (VREF /1024) is the DNL error. The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage. Accuracy is a function of the sampling rate (FS). 2 Specified values guarantee functionality. Refer to other parameters for accuracy. 3 Guaranteed. Not tested. 4 –1 dB bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to other parameters for accuracy within the specified bandwidth. 5 See V equivalent circuit. Switched capacitor analog input requires driver with low output resistance. IN 6 All inputs have diodes to AV DD and AGND. Input DC currents will not exceed specified limits for any input voltage between AGND and AVDD . 7 The GND pins are connected through the silicon substrate. Connect all GND pins together at the package and to the analog ground plane. DGND and GND are connected through junction diodes. See logic output interface section. 8 The V DD pins should be tied together at the package. 9 See logic output interface section. Specifications are subject to change without notice Rev. 1.00 5 XRD6414 ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3 Storage Temperature . . . . . . . . . . . . . . –65 to +150°C Package Power Dissipation Rating to 75°C TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000mW Derates above 75°C . . . . . . . . . . . . . . . . . . . 14mW/°C Lead Temperature (Soldering 10 seconds) . . +300°C VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V VRT & VRB . . . . . . . . . . . . . . . . VDD +0.5 to GND –0.5V VIN . . . . . . . . . . . . . . . . . . . . . . VDD +0.5 to GND –0.5V All Inputs . . . . . . . . . . . . . . . . . VDD +0.5 to GND –0.5V All Outputs . . . . . . . . . . . . . . . VDD +0.5 to GND –0.5V NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. 3 VDD refers to AVDD and DVDD. GND refers to AGND and DGND. 1/FS tPWL tPWH CLK N+1 N N+2 Pipeline Delay tAP Analog Input VIN DATA (DB0-DB9 and OFW) N+1 N Sampling Points tDL N–3 N–2 N–1 N Figure 2. XRD6414 Timing Diagram OE tDHZ DATA (DB0-DB9 and OFW) High Impedance Figure 3. 3-State Timing Diagram Rev. 1.00 6 tDEN N+1 XRD6414 THEORY OF OPERATION VIN Analog Input Power Supply Sequencing This part has a switched capacitor type input circuit. The input impedance changes with the phase of the input clock. VIN is sampled at the low to high clock transition and the digital data changes at the low to high clock transition. The diagram Figure 4. shows an equivalent input circuit. There are no power supply sequencing issues if DVDD and AVDD of the XRD6414 are driven from the same supply. Best parametric results, however, are obtained when DVDD and AVDD are driven from separate supplies. When DVDD and AVDD are driven separately, AVDD must come up at the same time or before DVDD, and go down at the same time or after DVDD. If the power supply sequencing in this case is not followed, then damage may occur to the product due to current flow through the source-body junction diodes between DVDD and AVDD. A low threshold schottky diode placed locally between DVDD and AVDD can prevent damage to the XRD6414. AVDD CLK 100Ω 18pF 100Ω VIN 5pF VRT + VRB + − 2 AGND CLK 1.5pF CL Logic Output Interface The digital output drive circuitry of the XRD6414 was designed to operate separately from the analog supplies. The DVDD pin of the XRD6414 is a separate power supply dedicated to the logic output drivers. DVDD is not connected internally with any of the other power supplies. Figure 5. illustrates the power supply circuity of the XRD6414. Figure 4. Equivalent Input Circuit OFW Overflow (Output) This signal indicates when the Analog Input (VIN) goes above VRT. The pin is normally at a low logic level. When VIN > VRT, OFW will go high and the data bits (DB0 – DB9) will show full scale (i.e. all 1s). DVDD and DGND connect directly to the digital logic power of the user’s system isolating the analog and digital power supplies and grounds. DGND is not common to the XRD6414 substrate. The XRD6414 substrate is common only to the packages’ AGND pins. Best spectral performance is obtained when DVDD is lowered to 3.3V. See the power supply sequencing section if AVDD and DVDD are powered separately. OE Output Enable (Input) This signal controls the 3-state drivers on the digital outputs DB0 – DB9 and OFW. During normal operation OE should be held low so that all outputs are enabled. When OE is driven high DB0 – DB9 and OFW go into high impedance mode. This control operates asynchronous to the clock and will only control the output drivers. The internal output register will get updated if the clock is running while the outputs are in three-state mode. OE DBO-DB9 OFW 0 Enabled Enabled 1 Three-Stated Three-Stated Table 1. Output Enable Rev. 1.00 7 XRD6414 the output of the driving op amp from the switching input capacitance of the XRD6414. FINAL DESIGN CONSIDERATIONS The XRD6414 can be evaluated with the XRD6414AB application board. Contact your distributor or sales person for delivery. Using the XRD6414AB the following final design considerations can be made. 1. Be generous with analog and digital ground planes. Mirror the ground plane with the supply planes. Use a 5 mil power / ground plane separation if a four layer board can be used. The XRD6414 substrate is common to the packages’ AGND pins only. DGND and DVDD are separate supplies dedicated to the output logic drivers of the XRD6414. Connect DGND and DVDD to the power planes of the system’s digital logic. 2. Keep high frequency decoupling capacitors very close to the A/D pins and minimize the loop area included so less flux will induce less noise. Use decoupling capacitors in the same locations as on the XRD6414AB. 3. Coupling between logic signals and analog circuitry can easily change a 10-bit system into an 8-bit system or worse. Completely separate them. Watch for coupling opportunities from other sources not immediately associated with the A/D. Don’t use switching power supplies in adjacent locations, for example. 4. The DC performance of the XRD6414 is optimized with rise and fall times of CLK edges limited to greater than or equal to 10ns. A resistor in series with the CLK input pin can combine with parasitic capacitance to limit rise and fall times. Select a low jitter clock with a 50% duty cycle for best spectral results. 5. Use support devices equivalent to those used on the evaluation board. Use the application board to verify these devices up front, i.e. use very linear passive components in the signal path. 6. 7. DNL and INL performance is optimized when the VRB input of the XRD6414 is buffered. If VRB is connected to the PCB ground plane it is subject to the noise and ground bounce in that plane. For example VRB could be buffered to 50mV above ground and still have a wide reference voltage range set by connecting VRT to a voltage near AVDD. 8. Use 50 or 100Ω resistors to isolate the XRD6414 digital output pins from a latch or bus connection. This protects the output drivers and reduces the effects of high speed switching logic signals from degrading the ADC performance. Layout the latch or digital buffers as close to the ADC as possible to minimize trace length. AVDD Source–body junction diode DVDD between DVDD & AVDD DB(0-9) & OFW A/D Circuit AGND Source–body junction diode between DGND & AGND DGND Figure 5. XRD6414 ADC Power Supply Circuit Allows Separate AVDD & DVDD and Separate AGND & DGND Select a driving op amp whose noise, speed, and linearity fits the application. Use a resistor to decouple Rev. 1.00 8 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 –0.8 –0.9 LSB LSB XRD6414 0 200 400 600 800 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 –1.4 –1.6 –1.8 –2.0 1000 0 200 400 CODE LSB LSB 400 1000 Figure 7. XRD6414, INL @ 15MSPS AVDD = 5V, VRT = 2.5V, VRB = 0.5V 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 –0.05 –0.01 –0.15 –0.20 –0.25 –0.30 –0.35 200 800 CODE Figure 6. XRD6414, DNL @ 15MSPS AVDD = 5V, VRT = 2.5V, VRB = 0.5V 0 600 600 800 1000 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 –1.4 –1.6 –1.8 –2.0 –2.2 –2.4 0 CODE 200 400 600 800 1000 CODE Figure 8. XRD6414, DNL @ 15MSPS AVDD = 5V, VRT = 5V, VRB = AGND Figure 9. XRD6414, INL @ 15MSPS AVDD = 5V, VRT = 5V, VRB = AGND Rev. 1.00 9 XRD6414 Figure 10. Crossplot Staircase Output CLK = (15MSPS, trf = 15ns), VIN = 3V, VREF = 2V RON vs. VIN 140 6.0 120 100 4.0 80 A OUT (V) R ON (Ω) AOUT 5.0 AVDD = 5V 60 3.0 2.0 1.0 40 A0 0.0 20 –1.0 0 0 1 2 3 VIN (Volts) 4 0 5 10 20 30 40 50 60 70 80 90 t(ns) Figure 11. Analog MUX RON vs. Input Voltage Figure 12. MUX Switching Time Waveform, AVDD = 5V Rev. 1.00 10 XRD6414 A1 A0 Selected Analog Input 0 0 AIN1 0 1 AIN2 1 0 AIN3 1 1 AIN4 Table 2. Truth Table for Analog Input Selection PD Device Status 1 Off (Not Operating) 0 On (Operating) Table 3. Power Down 5V or 3V AIN1 A1 AIN2 A0 Crosstalk (dB) AVDD (5 V) 50Ω 26pF 10MW AGND JP15 (2,3) AOUT VIN XRD6414 –78 –80 –82 –84 –86 –88 –90 –92 –94 –96 –98 –100 –102 –104 –106 –108 –110 –112 –114 0.00 2.00 4.00 6.00 FIN(MHz) Figure 14. XRD6414 Crosstalk, AVDD = 5V and VIN = 8dBm Figure 13. MUX Switching Time Test Circuit Rev. 1.00 11 XRD6414 40 30 20 5V 10 AVDD –10 0 VSOURCE 50Ω AIN1 –20 XRD6414 VOUT 50Ω AIN3 –30 dB VIN –40 –50 AOUT –60 A0 –70 A1 AGND –80 –90 –100 –110 0 0.1 0.2 0.3 0.4 0.5 FIN / FS Figure 15. Crosstalk Test Circuit Figure 16. XRD6414 FFT VREF = AVDD = 5V, DVDD = 3.3V, FIN = 100kHz, FS = 10MSPS, CIN = 100pF 58 59 57 58 56 55 57 dB dB 60 54 56 53 55 52 51 54 50 53 49 10 100 1,000 10 Input Frequency (kHz) 100 1,000 Input Frequency (kHz) Figure 17. XRD6414 SNR & SNDR vs. FIN, AVDD = 5V, DVDD = 3.3V, VREF = 5V & 2V, FS = 10MSPS, CIN = 100pF Figure 18. XRD6414 SNR & SNDR vs. FIN, AVDD = 5V, DVDD = 3.3V, VREF = 5V & 2V, FS = 15MSPS, CIN = 100pF Rev. 1.00 12 XRD6414 32 LEAD THIN QUAD FLAT PACK (7 x 7 x 1.4 mm TQFP) Rev. 2.00 D D1 24 17 16 25 D1 D 9 32 1 8 B e A2 C A α Seating Plane A1 L INCHES SYMBOL MIN MILLIMETERS MAX MIN MAX A 0.055 0.063 1.40 1.60 A1 0.002 0.006 0.05 0.15 A2 0.053 0.057 1.35 1.45 B 0.012 0.018 0.30 0.45 C 0.004 0.008 0.09 0.20 D 0.346 0.362 8.80 9.20 D1 0.272 0.280 6.90 7.10 e 0.0315 BSC 0.80 BSC L 0.018 0.030 0.45 0.75 α 0° 7° 0° 7° Note: The control dimension is the millimeter column Rev. 1.00 13 XRD6414 Notes Rev. 1.00 14 XRD6414 Notes Rev. 1.00 15 XRD6414 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1996 EXAR Corporation Datasheet March 1997 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 1.00 16