Revised August 1999 74F402 Serial Data Polynomial Generator/Checker General Description Features The 74F402 expandable Serial Data Polynomial generator/ checker is an expandable version of the 74F401. It provides an advanced tool for the implementation of the most widely used error detection scheme in serial digital handling systems. A 4-bit control input selects one-of-six generator polynomials. The list of polynomials includes CRC16, CRC-CCITT and Ethernet, as well as three other standard polynomials (56th order, 48th order, 32nd order). Individual clear and preset inputs are provided for floppy disk and other applications. The Error output indicates whether or not a transmission error has occurred. The CWG Control input inhibits feedback during check word transmission. The 74F402 is compatible with FAST devices and with all TTL families. ■ Guaranteed 30 MHz data rate ■ Six selectable polynomials ■ Other polynomials available ■ Separate preset and clear controls ■ Expandable ■ Automatic right justification ■ Error output open collector ■ Typical applications: Floppy and other disk storage systems Digital cassette and cartridge systems Data communication systems Ordering Code: Order Number Package Number 74F402PC N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Logic Symbol Connection Diagram FAST is a registered trademark of Fairchild Semiconductor Corporation. Ethernet is a registered trademark of Xerox Corporation. © 1999 Fairchild Semiconductor Corporation DS009535 www.fairchildsemi.com 74F402 Serial Data Polynomial Generator/Checker April 1988 74F402 Unit Loading/Fan Out Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL S0–S3 Polynomial Select Inputs 1.0/0.67 20 µA/−0.4 mA CWG Check Word Generate Input 1.0/0.67 20 µA/−0.4 mA D/CW Serial Data/Check Word 285(100)/13.3(6.7) −5.7 mA(−2 mA)/8 mA (4 mA) D Data Input ER 1.0/0.67 20 µA/−0.4 mA Error Output (Note 1) /26.7(13.3) (Note 1) /16 mA (8 mA) RO Register Output 285(100)/13.3(6.7) −5.7 mA(−2 mA)/8 mA (4 mA) CP Clock Pulse 1.0/0.67 20 µA/−0.4 mA SEI Serial Expansion Input 1.0/0.67 20 µA/−0.4 mA RFB Register Feedback 1.0/0.67 20 µA/−0.4 mA MR Master Reset 1.0/0.67 20 µA/−0.4 mA P Preset 1.0/0.67 20 µA/−0.4 mA Note 1: Open Collector Functional Description erate (CWG) must be held HIGH while the data is being entered. After the last data bit is entered, the CWG is brought LOW and the check bits are shifted out of the register(s) and appended to the data bits (no external gating is needed). The 74F402 Serial Data Polynomial Generator/Checker is an expandable 16-bit programmable device which operates on serial data streams and provides a means of detecting transmission errors. Cyclic encoding and decoding schemes for error detection are based on polynomial manipulation in modulo arithmetic. For encoding, the data stream (message polynomial) is divided by a selected polynomial. This division results in a remainder (or residue) which is appended to the message as check bits. For error checking, the bit stream containing both data and check bits is divided by the same selected polynomial. If there are no detectable errors, this division results in a zero remainder. Although it is possible to choose many generating polynomials of a given degree, standards exist that specify a small number of useful polynomials. The 74F402 implements the polynomials listed in Table 1 by applying the appropriate logic levels to the select pins S0, S1, S2 and S3. To check an incoming message for errors, both the data and check bits are entered through the D Input with the CWG Input held HIGH. The Error Output becomes valid after the last check bit has been entered into the ’F402 by a LOW-to-HIGH transition of CP, with the exception of the Ethernet polynomial (see Applications paragraph). If no detectable errors have occurred during the data transmission, the resultant internal register bits are all LOW and the Error Output (ER) is HIGH. If a detectable error has occurred, ER is LOW. ER remains valid until the next LOWto-HIGH transition of CP or until the device has been preset or reset. The 74F402 consists of a 16-bit register, a Read Only Memory (ROM) and associated control circuitry as shown in the Block Diagram. The polynomial control code presented at inputs S0, S1, S2 and S3 is decoded by the ROM, selecting the desired polynomial or part of a polynomial by establishing shift mode operation on the register with Exclusive OR (XOR) gates at appropriate inputs. To generate the check bits, the data stream is entered via the Data Inputs (D), using the LOW-to-HIGH transition of the Clock Input (CP). This data is gated with the most significant Register Output (RO) via the Register Feedback Input (RFB), and controls the XOR gates. The Check Word Gen- www.fairchildsemi.com A HIGH on the Master Reset Input (MR) asynchronously clears the entire register. A LOW on the Preset Input (P) asynchronously sets the entire register with the exception of: 1. The Ethernet residue selection, in which the registers containing the non-zero residue are cleared; 2. The 56th order polynomial, in which the 8 least significant register bits of the least significant device are cleared; and, 3. Register S = 0, in which all bits are cleared. 2 Hex S3 S2 S1 Polynomial S0 Remarks 0 L L L L 0 S=0 C H H L L X32+X26+X23+X22+X16+ Ethernet D H H L H X12+X11+X10+X8+X7+X5+X4+X2+X+1 Polynomial E H H H L X32+X31+X27+X26+X25+X19+X16+ Ethernet F H H H H X15+X13+X12+X11+X9+X7+X6+X5+X4+X2+X+1 Residue 7 L H H H X16+X15+X2+1 CRC-16 B H L H H X16+X12+X5+1 CRC-CCITT 3 L L H H X56+X55+X49+X45+X41+ 2 L L H L X39+X38+X37+X36+X31+ 56th 4 L H L L X22+X19+X17+X16+X15+X14+X12+X11+X9+ Order 8 H L L L X5+X+1 5 L H L H X48+X36+X35+ 9 H L L H X23+X21+ 48th 1 L L L H X15+X13+X8+X2+1 Order 6 L H H L X32+X23+X21+ 32nd A H L H L X11+X2+1 Order Block Diagram 3 www.fairchildsemi.com 74F402 TABLE 1. Select Code 74F402 TABLE 2. Select Code P3 P2 P1 P0 C2 C1 C0 0 0 0 0 0 1 0 0 S=0 C 1 1 1 1 1 0 1 Ethernet D 1 1 1 1 1 0 1 Polynomial E 0 0 0 0 0 0 0 Ethernet F 0 0 0 0 0 1 0 Residue Polynomial 7 1 1 1 1 1 0 0 CRC-16 B 1 1 1 1 1 0 0 CRC-CCITT 3 1 1 1 1 1 0 0 2 1 1 1 1 1 0 0 56th 4 1 1 1 1 1 0 0 Order 8 0 0 1 1 1 0 0 5 1 1 1 1 1 0 0 48th 9 1 1 1 1 1 0 0 Order 1 1 1 1 1 1 0 0 6 1 1 1 1 1 0 0 32nd A 1 1 1 1 1 0 0 Order Applications This allows the user to choose a lower order polynomial even if the system is configured for a higher order one. In addition to polynomial selection there are four other capabilities provided for in the 74F402 ROM. The first is set or clear selectability. The sixteen internal registers have the capability to be either set or cleared when P is brought LOW. This set or clear capability is done in four groups of 4 (see Table 2, P0–P3). The second ROM capability (C0) is in determining the polarity of the check word. As is the case with the Ethernet polynomial the check word can be inverted when it is appended to the data stream or as is the case with the other polynomials, the residue is appended with no inversion. Thirdly, the ROM contains a bit (C1) which is used to select the RFB input instead of the SEI input to be fed into the LSB. This is used when the polynomial selected is actually a residue (least significant) stored in the ROM which indicates whether the selected location is a polynomial or a residue. If the latter, then it inhibits the RFB input. The 74F402 expandable CRC generator checker contains 6 popular CRC polynomials, 2-16th Order, 2-32nd Order, 148th Order and 1-56th Order. The application diagram shows the 74F402 connected for a 56th Order polynomial. Also shown are the input patterns for other polynomials. When the 74F402 is used with a gated clock, disabling the clock in a HIGH state will ensure no erroneous clocking occurs when the clock is re-enabled. Preset and Master Reset are asynchronous inputs presetting the register to S or clearing to 1s respectively (note Ethernet residue and 56th Order select code 8, LSB, are exceptions to this). To generate a CRC, the pattern for the selected polynomial is applied to the S inputs, the register is preset or cleared as required, clock is enabled, CWG is set HIGH, data is applied to D input, output data is on D/CW. When the last data bit has been entered, CWG is set LOW and the register is clocked for n bits (where n is the order of the polynomial). The clock may now be stopped if desired (holding CWG LOW and clocking the register will output zeros from D/CW after the residue has been shifted out). As mentioned previously, upon a successful data transmission, the CRC register has a zero residue. There is an exception to this, however, with respect to the Ethernet polynomial. This polynomial, upon a successful data transmission, has a non-zero residue in the CRC register (C7 04 DD 7B)16. In order to provide a no-error indication, two ROM locations have been preloaded with the residue so that by selecting these locations and clocking the device one additional time, after the last check bit has been entered, will result in zeroing the CRC register. In this manner a no-error indication is achieved. To check a CRC, the pattern for the selected polynomial is applied to the S inputs, the register is preset or cleared as required, clock is enabled, CWG is set HIGH, the data stream including the CRC is applied to D input. When the last bit of the CRC has been entered, the ER output is checked: HIGH = error free data, LOW = corrupt data. The clock may now be stopped if desired. With the present mix of polynomials, the largest is 56th order requiring four devices while the smallest is 16th order requiring just one device. In order to accommodate multiplexing between high order polynomials (X 16th order) and lower order polynomials, a location of all zeros is provided. www.fairchildsemi.com To implement polynomials of lower order than 56th, select the number of packages required for the order of polynomial and apply the pattern for the selected polynomial to the S inputs (0000 on S inputs disables the package from the feedback chain). 4 74F402 5 www.fairchildsemi.com 74F402 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. −0.5V to VCC Standard Output −0.5V to +5.5V 3-STATE Output Note 3: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output twice the rated IOL (mA) in LOW State (Max) DC Electrical Characteristics Symbol Parameter Min Typ Max VCC Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min VOH Output HIGH V Min Voltage VOL IIH 2.0 Units VIH 10% VCC 2.4 5% VCC 2.7 V 10% VCC 0.5 IOL = 16 mA (ER) 0.5 IOL = 8 mA (D/CW, RO) Input HIGH Input HIGH Current Output HIGH Input Leakage Test IOD Output Leakage IIL Input LOW Current IOS Output Short-Circuit Current −20 Open Collector, Output OFF Leakage Test ICC Power Supply Current www.fairchildsemi.com 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.4 mA Max VIN = 0.5V −130 mA Max VOUT = 0V (D/CW, RO) 250 µA Min VOUT = VCC (ER) 165 mA Max 4.75 Circuit Current IOHC IOH = −5.7 mA (RO, D/CW) IOH = −5.7 mA (RO, D/CW) 10% VCC Leakage Current VID IIN = −18 mA Output LOW Breakdown Test ICEX Recognized as a LOW Signal Voltage Current IBVI Conditions Recognized as a HIGH Signal 110 6 IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded 74F402 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ fMAX Maximum Clock Frequency 30 45 Max Min Max tPLH Propagation Delay 8.5 15.0 tPHL CP to D/CW 10.5 18.0 23.0 9.5 26.5 9.5 25.0 tPLH Propagation Delay 8.0 13.5 17.0 7.0 26.0 7.0 19.0 tPHL CP to RO 8.0 14.0 18.0 7.0 22.5 7.0 20.0 tPLH Propagation Delay 15.5 26.0 33.0 14.0 38.5 14.0 35.0 tPHL CP to ER 8.5 14.5 18.5 7.5 23.5 7.5 20.5 30 19.0 7.5 Min Max 30 26.5 7.5 Units MHz 21.0 ns ns ns tPLH Propagation Delay 11.0 18.5 23.5 10.0 31.0 10.0 25.5 tPHL P to D/CW 11.5 19.5 24.5 10.5 32.0 10.5 26.5 tPLH Propagation Delay 9.5 16.0 20.5 8.5 31.5 8.5 22.5 ns 10.0 17.0 21.5 9.0 26.0 9.0 23.5 ns P to RO tPLH Propagation Delay P to ER ns tPLH Propagation Delay 10.5 18.0 23.0 9.5 29.0 9.5 25.5 tPHL MR to D/CW 11.0 19.0 24.0 10.0 28.5 10.0 26.0 tPHL Propagation Delay 9.0 15.5 19.5 8.0 23.5 8.0 21.5 ns ns MR to RO tPLH Propagation Delay 16.5 28.0 35.5 14.5 39.0 14.5 37.5 6.0 10.5 13.5 5.0 19.5 5.0 15.0 D to D/CW 7.5 12.0 16.0 6.5 20.0 6.5 18.0 Propagation Delay 6.5 11.0 14.0 5.5 21.5 5.5 15.5 MR to ER tPLH Propagation Delay tPHL tPLH tPHL CWG to D/CW 7.0 12.0 15.5 6.0 21.5 6.0 17.5 tPLH Propagation Delay 11.5 19.5 24.5 9.0 29.0 10.5 26.5 tPHL Sn to D/CW 9.5 16.0 20.0 8.5 25.0 8.5 22.0 7 ns ns ns ns www.fairchildsemi.com 74F402 AC Operating Requirements Symbol Parameter TA = +25°C TA = −55°C to +125°C VCC = +5.0V VCC = +5.0V Min Max Min Max TA = 0°C to +70°C VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 4.5 6.0 5.0 tS(L) SEI to CP 4.5 6.0 5.0 tH(H) Hold Time, HIGH or LOW 0 1.0 0 tH(L) SEI to CP 0 1.0 0 tS(H) Setup Time, HIGH or LOW 11.0 14.0 12.5 tS(L) RFB to CP 11.0 14.0 12.5 tH(H) Hold Time, HIGH or LOW 0 0 0 tH(L) RFB to CP 0 0 0 tS(H) Setup Time, HIGH or LOW 13.5 16.0 15.0 tS(L) S1 to CP 13.0 15.5 14.5 tH(H) Hold Time, HIGH or LOW 0 0 0 Units Max ns ns ns tH(L) S1 to CP 0 0 0 tS(H) Setup Time, HIGH or LOW 9.0 11.5 10.0 tS(L) D to CP 9.0 11.5 10.0 tH(H) Hold Time, HIGH or LOW 0 0 0 tH(L) D to CP 0 0 0 tS(H) Setup Time, HIGH or LOW 7.0 9.0 8.0 tS(L) CWG to CP 5.5 8.0 6.5 tH(H) Hold Time, HIGH or LOW 0 0 0 tH(L) CWG to CP 0 0 0 tW(H) Clock Pulse Width 4.0 7.0 4.5 tW(L) HIGH or LOW 4.0 5.0 4.5 tW(H) MR Pulse Width, HIGH 4.0 7.0 4.5 ns tW(L) P Pulse Width, LOW 4.0 5.0 4.5 ns tREC Recovery Time 3.0 4.0 3.5 tREC Recovery Time 5.0 6.5 6.0 MR to CP P to CP www.fairchildsemi.com ns ns ns ns 8 74F402 Serial Data Polynomial Generator/Checker Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com