74LVQ573 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 3.3V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.5 V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) PCI BUS LEVELS GUARANTEED AT 24mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The LVQ573 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. These 8 bit D-Type flip-flops are controlled by a latch enable input (LE) and an output enable M (Micro Package) T (TSSOP Package) ORDER CODES : 74LVQ573M 74LVQ573T input (OE). While the LE input is held at a high level, the Q outputs will follow the data input precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. It has better speed performance at 3.3V than 5V LSTTL family combined with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS February 1999 1/10 74LVQ573 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 OE NAME AND FUNCT ION 2, 3, 4, 5, 6, 7, 8, 9 D0 to D7 Data Inputs 12, 13, 14, 15, 16, 17, 18, 19 Q0 to Q7 3 State Latch Outputs 11 LE Latch Enable Input 10 GND Ground (0V) 20 VCC Positive Supply Voltage 3 State Output Enable Input (Active LOW) TRUTH TABLE INPUTS LE D Q H X X Z L L X NO CHANGE * L H L L L H H H X:Don’t care Z: High impedance * Q outputs are latched atthe time when the LEinput Is taken low logic level. LOGIC DIAGRAM 2/10 OUT PUTS OE 74LVQ573 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V VI DC Input Voltage -0.5 to VCC + 0.5 V VO DC Output Voltage -0.5 to VCC + 0.5 V IIK DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 50 mA ± 400 mA ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 o 300 o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage (note 1) Valu e Unit 2 to 3.6 V V VI Input Voltage 0 to VCC VO Output Voltage 0 to VCC Top Operating Temperature: dt/dv Input Rise and Fall Time (VCC = 3V) (note 2) -40 to +85 0 to 10 V o C ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V 3/10 74LVQ573 DC SPECIFICATIONS Symb ol Parameter Test Co nditions VIH High Level Input Voltage VIL Low Level Input Voltage VOH VOL II 3.0 Low Level Output Voltage 3.0 T yp. Un it o -40 to 85 C Max. 2.0 Min. Max. 2.0 0.8 V 0.8 VI = V IH or V IL I O =-50 µA 2.9 IO=-12 mA 2.58 VI(*) = VIH or VIL IO=50 µA 0.002 0.1 0.1 IO=12 mA 0 0.36 0.44 (* ) 2.99 V 2.9 V 2.48 IO=-24 mA 2.2 IO=24 mA V 0.55 3.6 VI = VCC or GND ±0.1 ±1 µA 3.6 VI = VIH or VIL VO = VCC or GND ±0.25 ±2.5 µA Quiescent Supply Current 3.6 VI = VCC or GND 4 40 µA Dynamic Output Current (note 1, 2) 3.6 VOLD = 0.8 V max 36 mA VOHD = 2 V min -25 mA Input Leakage Current IOZ 3 State Output Leakage Current ICC IOLD IOHD Min. 3.0 to 3.6 High Level Output Voltage Valu e o T A = 25 C V CC (V) 1) Maximum test duration 2ms, one output loaded attime 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 Ω. (*) All outputs loaded. DYNAMIC SWITCHING CHARACTERISTICS Symb ol Parameter Test Co nditions Dynamic Low Voltage Quiet Output (note 1, 2) 3.3 VIHD Dynamic High Voltage Input (note 1, 3) 3.3 VILD Dynamic Low Voltage Input (note 1, 3) 3.3 VOLP VOLV Valu e o Min. -0.8 -40 to 85 C T yp. Max. 0.5 0.8 Min. Max. -0.6 2 C L = 50 pF Un it o T A = 25 C V CC (V) V 0.8 1) Worst case package 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND 3) max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD). f=1MHz 4/10 74LVQ573 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns) Symb ol Parameter T est Con ditio n Valu e Un it o o -40 to 85 C T A = 25 C Min. T yp. Max. Min. Max. V CC (V) tPLH tPHL Propagation Delay Time LE to Q 2.7 3.3(*) tPLH tPHL Propagation Delay Time D to Q 7.5 15.0 16.0 3.3 (*) 6.0 10.0 11.0 tPLZ tPHZ Output Disable Time 2.7 3.3(*) 8.5 7.0 20.0 14.0 21.0 15.0 tPZL tPZH Output Enable Time LE pulse Width, HIGH 2.7 3.3(*) 2.7 9.0 7.0 2.0 18.0 12.0 5.0 19.0 13.0 6.0 (*) tsL tsH Setup Time D to LE HIGH or LOW 3.3 2.7 3.3(*) 1.5 0.0 0.0 4.0 2.5 2.0 4.0 3.0 2.5 thL thH Hold Time D to LE, HIGH or LOW 2.7 3.3(*) 0.0 0.0 2.5 2.0 3.0 2.5 ns Output to Output Skew Time (note 1, 2) 2.7 0.5 1.0 1.5 ns 3.3(*) 0.5 1.0 1.5 tw tOSLZ tOSHL 8.0 6.5 2.7 17.0 11.0 18.0 12.0 ns ns ns ns ns ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tpHLn|) 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V CAPACITIVE CHARACTERISTICS Symb ol Parameter Test Co nditions Input Capacitance 3.3 COUT Output Capacitance 3.3 CPD Power Dissipation Capacitance (note 1) 3.3 C IN Valu e T A = 25 oC V CC (V) Min. fIN = 10 MHz T yp. Max. Un it -40 to 85 o C Min. Max. 4 pF 10 pF 10 pF 1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC •fIN + ICC/* (per Latch) 5/10 74LVQ573 TEST CIRCUIT T EST tPLH , tPHL SW IT CH Open tPZL , tPLZ 2VCC tPZH , tPHZ Open CL = 50 pF or equivalent (includes jigand probe capacitance) RL = R1 = 500Ω orequivalent RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/10 74LVQ573 WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3: Dn TO Qn PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 7/10 74LVQ573 SO-20 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 2.65 0.10 0.104 0.20 a2 MAX. 0.004 0.007 2.45 0.096 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 C 0.50 0.020 c1 45 (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.299 L 0.50 1.27 0.19 0.050 M S 0.75 0.029 8 (max.) P013L 8/10 74LVQ573 TSSOP20 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. A MIN. TYP. MAX. 1.1 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.19 0.30 0.0075 0.0118 c 0.09 0.2 0.0035 0.0079 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.25 6.4 6.5 0.246 0.252 0.256 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 BSC 0.0256 BSC K 0o 4o 8o 0o 4o 8o L 0.50 0.60 0.70 0.020 0.024 0.028 A A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 9/10 74LVQ573 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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