DISCRETE SEMICONDUCTORS DATA SHEET BF1105; BF1105R; BF1105WR N-channel dual-gate MOS-FETs Product specification Supersedes data of 1997 Dec 01 File under Discrete Semiconductors, SC07 1997 Dec 02 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1105; BF1105R; BF1105WR PINNING FEATURES • Short channel transistor with high forward transfer admittance to input capacitance ratio PIN DESCRIPTION 1 source • Low noise gain controlled amplifier up to 1 GHz. 2 drain 3 gate 2 • Internal self-biasing circuit to ensure good cross-modulation performance during AGC and good DC stabilization. 4 gate 1 handbook, 2 columns 3 4 2 1 Top view MSB035 BF1105R marking code: NAp. Fig.2 APPLICATIONS Simplified outline (SOT143R). • VHF and UHF applications with 5 V supply voltage, such as television tuners and professional communications equipment. page 4 3 1 2 alfpage 3 4 2 1 DESCRIPTION Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1105, BF1105R and BF1105WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively. Top view MSB014 BF1105 marking code: NEp. Fig.1 Simplified outline (SOT143B). Top view MSB842 BF1105WR marking code: NA. Fig.3 Simplified outline (SOT343R). QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDS drain-source voltage − − 7 V ID drain current − − 30 mA Ptot total power dissipation − − 200 mW yfs forward transfer admittance Tamb ≤ 80 °C 25 31 − mS Cig1-ss input capacitance at gate 1 − 2.2 2.7 pF Crss reverse transfer capacitance f = 1 MHz − 25 40 fF F noise figure f = 800 MHz − 1.7 2.5 dB Xmod cross-modulation input level for k = 1% at 40 dB AGC 100 − − dBµV Tj operating junction temperature − 150 °C − CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B. 1997 Dec 02 2 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1105; BF1105R; BF1105WR LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage − 7 V ID drain current − 30 mA IG1 gate 1 current − ±10 mA IG2 gate 2 current Ptot total power dissipation Tstg Tj − ±10 mA − 200 mW storage temperature −65 +150 °C operating junction temperature − +150 °C Tamb ≤ 80 °C; note 1; see Fig.4 Note 1. Device mounted on a printed-circuit board. MGM243 250 handbook, halfpage Ptot (mW) 200 150 100 50 0 0 40 80 120 160 Tamb (°C) Fig.4 Power derating curve. 1997 Dec 02 3 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1105; BF1105R; BF1105WR THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS Rth j-a thermal resistance from junction to ambient in free air Rth j-s thermal resistance from junction to soldering point VALUE note 1 UNIT 350 K/W 200 K/W Note 1. Device mounted on a printed-circuit board. STATIC CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT 7 − − V V(BR)G1-SS gate 1-source breakdown voltage VG2-S = 0; ID = 0; IG1-S = 10 µA 7 − − V V(BR)G2-SS gate 2-source breakdown voltage VG1-S = VDS = 0; IG2-S = 10 µA 7 − − V V(BR)DSS drain-source breakdown voltage VG1-S = VG2-S = 0; ID = 10 µA MIN. VG2-S (th) gate 2-source threshold voltage VG1-S = 5 V; VDS = 5 V; ID = 20 µA 0.3 0.8 1.2 V IDSX self-biasing drain current VG2-S = 4 V; VDS = 5 V 8 − 16 mA IG1-SS gate 1 cut-off current VG1-S = 5 V; VG2-S = 0; ID = 0 − − 50 nA IG2-SS gate 2 cut-off current VG1-S = VDS = 0; VG2-S = 4 V − − 20 nA DYNAMIC CHARACTERISTICS Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; self-biasing current; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. yfs forward transfer admittance pulsed; Tj = 25 °C 25 31 Cig1-ss input capacitance at gate 1 f = 1 MHz − Cig2-ss input capacitance at gate 2 f = 1 MHz − Coss output capacitance f = 1 MHz Crss F Gp Xmod MAX. UNIT − mS 2.2 2.7 pF 1.6 − pF − 1.2 − pF reverse transfer capacitance f = 1 MHz − 25 40 fF noise figure f = 800 MHz; YS = YS opt − 1.7 2.5 dB power gain GS = 2 mS; BS = BS opt; GL = 0.5 mS; BL = BL opt; f = 200 MHz; see Fig.16 − 38 − dB GS = 3.3 mS; BS = BS opt; GL = 1 mS; BL = BL opt; f = 800 MHz; see Fig.17 − 20 − dB input level for k = 1% at 0 dB AGC; fw = 50 MHz; funw = 60 MHz; see Fig.18 85 − − dBµV input level for k = 1% at 40 dB AGC; fw = 50 MHz; funw = 60 MHz; see Fig.18 100 − − dBµV cross-modulation 1997 Dec 02 4 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1105; BF1105R; BF1105WR MGM244 25 handbook, halfpage VG1 = 1.7 V ID (mA) 20 MGM245 40 handbook, halfpage ID (mA) 1.6 V VG2-S = 4 V 30 3.5 V 3V 1.5 V 15 1.4 V 10 2.5 V 20 1.3 V 2V 1.2 V 5 10 1.1 V 1.5 V 1V 1V 0 0 0 2 4 6 VDS (V) 0 8 VG2-S = 4 V. Tj = 25 °C. 0.5 1 1.5 2 2.5 VG1 (V) VDS = 5 V. Tj = 25 °C. Fig.5 Output characteristics; typical values. Fig.6 Transfer characteristics; typical values. MGM246 MGM247 16 40 handbook, halfpage handbook, halfpage yfs (mS) ID (mA) VG2-S = 4 V 3.5 V 12 30 (1) (2) (3) 3V 8 20 (4) (5) 4 10 2.5 V 2V 0 0 0 10 20 ID (mA) 0 30 (1) VDS = 5 V. (2) VDS = 4.5 V. (3) VDS = 4 V. VDS = 5 V. Tj = 25 °C. Fig.7 1 Forward transfer admittance as a function of drain current; typical values. 1997 Dec 02 Fig.8 5 2 3 4 5 VG2-S (V) (4) VDS = 3.5 V. (5) VDS = 3 V. Drain current as a function of gate 2 voltage; typical values. Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1105; BF1105R; BF1105WR fMGM248 MGM249 16 16 handbook, halfpage handbook, halfpage ID (mA) ID (mA) 12 12 8 8 4 4 0 0 0 2 4 6 VDS (V) 8 VG2-S = 4 V. Tj = 25 °C. Fig.9 −4 −2 IG1 (µA) 0 Fig.10 Drain current as a function of gate 1 current; typical values. MGM250 110 handbook, halfpage Vunw (dBµV) 100 90 80 20 40 60 gain reduction (dB) VDS = 5 V; VG2nom = 4 V; IDnom = Iself bias; fw = 50 MHz; funw = 60 MHz; Tamb = 25 °C. Fig.11 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values (see Fig.18). 1997 Dec 02 −6 VDS = 5 V; VG2-S = 4 V; Tj = 25 °C. Drain current as a function of drain-source voltage; typical values. 0 −8 6 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1105; BF1105R; BF1105WR MGM251 102 handbook, halfpage MGM252 103 handbook, halfpage yis (mS) −103 ϕrs (deg) |yrs| (µS) 10 ϕrs 102 −102 bis 1 |yrs| 10−1 10−2 10 gis 102 −10 10 f (MHz) 1 10 103 102 f (MHz) −1 103 VDS = 5 V; VG2-S = 4 V. ID = 12 mA; Tamb = 25 °C. VDS = 5 V; VG2-S = 4 V. ID = 12 mA; Tamb = 25 °C. Fig.12 Input admittance as a function of frequency; typical values. Fig.13 Reverse transfer admittance and phase as a function of frequency; typical values. MGM253 102 handbook, halfpage MGM254 −102 10 handbook, halfpage ϕfs (deg) |yfs| (mS) yos (mS) |yfs| bos 1 −10 10 gos 10−1 ϕfs 1 10 102 f (MHz) −1 103 10−2 10 VDS = 5 V; VG2-S = 4 V. ID = 12 mA; Tamb = 25 °C. f (MHz) 103 VDS = 5 V; VG2-S = 4 V. ID = 12 mA; Tamb = 25 °C. Fig.14 Forward transfer admittance and phase as a function of frequency; typical values. 1997 Dec 02 102 Fig.15 Output admittance as a function of frequency; typical values. 7 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1105; BF1105R; BF1105WR VAGC handbook, full pagewidth VDS 1 nF 2 µH 1 nF 1 nF 1 nF 47 kΩ 1 nF L2 G2 D BF1105 BF1105R BF1105WR 5.5 pF input 50 Ω G1 C1 L1 output 50 Ω S 15 pF 10 pF BB405 330 kΩ 1 nF BB405 1 nF 330 kΩ 1 nF Vtun input Vtun output MGM255 VDS = 5 V, GS= 2 mS, GL = 0.5 mS, f = 200 MHz. L1 = 45 nH, 4 turns, internal diameter = 4 mm, 0.8 mm copper wire. L2 = 160 nH, 3 turns, internal diameter = 8 mm, 0.8 mm copper wire; tapped at approximately half a turn from the cold side, to set GL = 0.5 mS. C1 adjusted for GS = 2 mS. Fig.16 Gain test circuit. VAGC handbook, full pagewidth VDS 1 nF 1 nF 47 kΩ ,,, 1 nF input 50 Ω 1 nF L1 2 to 18 pF G2 G1 ,,,, ,,,, L3 L2 D BF1105 BF1105R BF1105WR 0.5 to 3.5 pF S 0.5 to 3.5 pF VDS = 5 V, GS= 3.3 mS, GL = 1 mS, f = 800 MHz. L1 = 2 cm, silvered 0.8 mm copper wire 4 mm above ground plane. L2 = 2 cm, silvered 0.8 mm copper wire 4 mm above ground plane. L3 = 11 turns 0.5 mm copper wire without spacing, internal diameter = 3 mm, L = approx. 200 nH. Fig.17 Gain test circuit. 1997 Dec 02 8 1 nF output 50 Ω 4 to 40 pF MGM256 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1105; BF1105R; BF1105WR VG2 handbook, full pagewidth VDS 4.7 nF 10 kΩ 4.7 nF 10 nF Rgen 50 Ω 47 µH G2 D BF1105 BF1105R G1 BF1105WR S 10 nF R1 = 50 Ω 50 Ω MGM257 Vi Fig.18 Cross-modulation test set-up. Table 1 f (MHz) Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 12 mA S11 S21 S12 S22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) 50 0.994 −3.8 3.060 175.4 0.000 86.9 0.985 −2.1 100 0.991 −7.5 3.047 170.9 0.002 86.1 0.983 −4.2 200 0.982 −14.7 3.004 162.1 0.003 82.7 0.980 −8.3 300 0.968 −21.7 2.932 153.4 0.004 79.7 0.976 −12.1 400 0.956 −28.8 2.896 145.3 0.006 77.8 0.972 −16.2 500 0.937 −35.4 2.815 137.1 0.007 76.7 0.967 −20.0 600 0.918 −41.8 2.735 129.2 0.007 76.3 0.961 −23.7 700 0.897 −48.1 2.651 121.5 0.008 76.7 0.955 −27.3 800 0.878 −54.0 2.575 114.0 0.008 79.7 0.948 −30.9 900 0.858 −59.9 2.482 106.5 0.008 82.2 0.941 −34.4 1000 0.840 −65.5 2.396 99.5 0.008 88.0 0.935 −37.9 Table 2 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 12 mA Γopt f (MHz) Fmin (dB) (ratio) (deg) Rn (Ω) 800 1.5 0.674 39.7 37.15 1997 Dec 02 9 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1105; BF1105R; BF1105WR PACKAGE OUTLINES Plastic surface mounted package; 4 leads SOT143B D B E A X y HE v M A e bp w M B 4 3 Q A A1 c 1 2 Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp b1 c D E e e1 HE Lp Q v w y mm 1.1 0.9 0.1 0.48 0.38 0.88 0.78 0.15 0.09 3.0 2.8 1.4 1.2 1.9 1.7 2.5 2.1 0.45 0.15 0.55 0.45 0.2 0.1 0.1 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 97-02-28 SOT143B 1997 Dec 02 EUROPEAN PROJECTION 10 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1105; BF1105R; BF1105WR Plastic surface mounted package; reverse pinning; 4 leads D SOT143R B E A X y HE v M A e bp w M B 3 4 Q A A1 c 2 1 Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp b1 c D E e e1 HE Lp Q v w y mm 1.1 0.9 0.1 0.48 0.38 0.88 0.78 0.15 0.09 3.0 2.8 1.4 1.2 1.9 1.7 2.5 2.1 0.55 0.25 0.45 0.25 0.2 0.1 0.1 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 97-03-10 SOT143R 1997 Dec 02 EUROPEAN PROJECTION 11 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1105; BF1105R; BF1105WR Plastic surface mounted package; reverse pinning; 4 leads D SOT343R E B A X HE y v M A e 3 4 Q A A1 c 2 w M B 1 bp Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp b1 c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.4 0.3 0.7 0.5 0.25 0.10 2.2 1.8 1.35 1.15 1.3 1.15 2.2 2.0 0.45 0.15 0.23 0.13 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 97-05-21 SOT343R 1997 Dec 02 EUROPEAN PROJECTION 12 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1105; BF1105R; BF1105WR DEFINITIONS Data Sheet Status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1997 Dec 02 13 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1105; BF1105R; BF1105WR NOTES 1997 Dec 02 14 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1105; BF1105R; BF1105WR NOTES 1997 Dec 02 15 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 117067/00/03/pp16 Date of release: 1997 Dec 02 Document order number: 9397 750 03136