ESD103-B1-02EL Data Sheet (644 KB, EN)

TVS Diodes
Transient Voltage Suppressor Diodes
ESD103-B1-02 Series
Bi-directional Femto Farad Capacitance TVS Diode
ESD103-B1-02ELS
ESD103-B1-02EL
Data Sheet
Revision 1.3, 2014-06-12
Final
Power Management & Multimarket
Edition 2014-06-12
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG
All Rights Reserved.
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characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
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be endangered.
ESD103-B1-02 Series
Bi-directional Femto Farad Capacitance TVS Diode
1
Bi-directional Femto Farad Capacitance TVS Diode
1.1
Features
•
•
•
•
•
•
•
ESD/Transient protection of RF and ultra-high speed signal lines according to:
– IEC61000-4-2: ±10 kV (contact)
Extremely low capacitance CL = 0.09 pF (typical) at f = 1 GHz
Maximum working voltage: VRWM = ±15 V
Very low reverse current: IR < 0.1 nA (typ.)
Very low series inductance down to 0.2 nH typical (TSSLP-2-4)
Extremely small form factor down to 0.62 x 0.32 x 0.31 mm²
Pb-free package (RoHS compliant)
1.2
•
•
•
•
Application Examples [4]
ESD protection in RF applications
Tailored for connectivity applications
WLAN, GPS antenna, DVB T/H, Bluetooth Class 1 and 2
Automated Meter Reading
1.3
Product Description
Pin 1
Pin 2
Pin 1 marking
(lasered)
Pin 1
TSLP-2
Pin 1
Pin 2
Pin 2
TSSLP-2
a) Pin configuration
b) Schematic diagram
Figure 1
Pin configuration and Schematic diagram
Table 1
Ordering Information
Type
Package
Configuration
Marking code
ESD103-B1-02ELS
TSSLP-2-4
1 line, bi-directional
V
ESD103-B1-02EL
TSLP-2-20
1 line, bi-directional
V
Final Data Sheet
4
Revision 1.3, 2014-06-12
ESD103-B1-02 Series
Characteristics
2
Characteristics
Table 2
Maximum Ratings at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
VESD
-10
–
10
kV
Operating temperature
TOP
-55
–
125
°C
Storage temperature
Tstg
-65
–
150
°C
ESD contact discharge
1)
1) VESD according to IEC61000-4-2 (R = 330 Ω, C = 150 pF discharge network)
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
2.1
Electrical Characteristics at TA = 25 °C, unless otherwise specified
Figure 2
!"#
Definitions of electrical characteristics
Final Data Sheet
5
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ESD103-B1-02 Series
Characteristics
Table 3
DC Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Reverse working voltage
VRWM
-15
–
15
V
Trigger voltage
VTrig
–
21
–
V
–
21
–
Note /
Test Condition
IBR = 1 mA, from Pin 1
to Pin 2
IBR = 1 mA, from Pin 2
to Pin 1
Reverse current
Table 4
IR
<0.1
50
nA
VR = 15 V
Unit
Note /
Test Condition
pF
VR = 0 V, f = 1 MHz
RF Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Line capacitance
CL
Series inductance
Table 5
–
Values
Min.
Typ.
Max.
–
0.13
0.2
–
0.09
–
–
–
0.2
0.4
–
–
VR = 0 V, f = 1 GHz
nH
LS
ESD103-B1-02ELS
ESD103-B1-02EL
ESD Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
1)
Clamping voltage
Dynamic resistance
VCL
1)
RDYN
Values
Unit
Note /
Test Condition
V
ITLP = 1 A
Min.
Typ.
Max.
–
20
–
–
36
–
ITLP = 8 A
–
48
–
ITLP = 16 A
–
1.8
–
Ω
tp = 100 ns
1) ANSI/ESD STM5.5.1 - Electrostatic Discharge Sensitive Testing using Transmission Line Pulse (TLP) Model. TLP
conditions: Z0 = 50 Ω, tp = 100 ns, tr = 0.6 ns, ITLP and VTLP averaging window: t1 = 30 ns to t2 = 60 ns, extraction of
dynamic resistance using least squares fit of TLP characteristic between ITLP1 = 2 A and ITLP2 = 14.1 A. Please refer to
Application Note AN210[1].
Final Data Sheet
6
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ESD103-B1-02 Series
Typical Characteristics
3
Typical Characteristics
At TA = 25 °C, unless otherwise specified
10-3
10-4
-5
10
IR [A]
10-6
-7
10
10-8
-9
10
10-10
-11
10
-12
10
Figure 3
-20
-15
-10
-5
0
VR [V]
5
10
15
20
10
15
20
Reverse current IR = f(VR)
0.2
0.18
0.16
CL [pF]
0.14
f=1MHz
0.12
f=1GHz
0.1
0.08
0.06
0.04
0.02
0
-20
Figure 4
-15
-10
-5
0
VR [V]
5
Line capacitance CL = f(VR), f = 1 MHz
Final Data Sheet
7
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ESD103-B1-02 Series
Typical Characteristics
0.2
0.18
0.16
CL [pF]
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
Figure 5
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
f [GHz]
Line capacitance: CL = f(f), VR = 0 V
Final Data Sheet
8
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ESD103-B1-02 Series
Typical Characteristics
20
ESD103-B1-02ELS
RDYN
10
15
7.5
RDYN = 1.78 Ω
5
5
2.5
0
0
-5
-2.5
-10
Equivalent VIEC [kV]
ITLP [A]
10
-5
RDYN = 1.78 Ω
-15
-7.5
-20
-10
-80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80
VTLP [V]
Figure 6
Clamping voltage (TLP): ITLP = f(VTLP) according ANSI/ESDSTM5.5.1-Electrostatistic
Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions:
Z0 = 50 Ω, tp = 100 ns, tr = 0.6 ns, ITLP and VTLP average window: t1 = 30 ns to t2 = 60 ns,
extraction of dynamic resistance using squares fit to TLP characteristics between ITLP1 = 2 A
and ITLP2 = 14.1 A. Please refer to Application Note AN210[1]
Final Data Sheet
9
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ESD103-B1-02 Series
Typical Characteristics
350
Scope: 6 GHz, 20 GS/s
VCL [V]
300
250
VCL-max-peak = 319 V
200
VCL-30ns-peak = 43 V
150
100
50
0
-50
-50
Figure 7
0
50
100
150
200
tp [ns]
250
300
350
400
450
Clamping voltage at +8 kV discharge according IEC61000-4-2 (R = 330 Ω, C = 150 pF)
50
0
-50
VCL [V]
-100
-150
-200
VCL-max-peak = -319 V
-250
VCL-30ns-peak = -41 V
-300
-350
-50
Figure 8
Scope: 6 GHz, 20 GS/s
0
50
100
150
200
tp [ns]
250
300
350
400
450
Clamping voltage at -8 kV discharge according IEC61000-4-2 (R = 330 Ω, C = 150 pF)
Final Data Sheet
10
Revision 1.3, 2014-06-12
ESD103-B1-02 Series
Package Information
4
Package Information
4.1
TSSLP-2-4 [2]
Top view
Bottom view
0.31 +0.01
-0.02
0.32 ±0.05
0.355
0.62 ±0.05
2
Cathode
marking
0.26 ±0.035
0.2 ±0.035 1)
1
0.05 MAX.
1)
1) Dimension applies to plated terminals
TSSLP 2 3 PO V01
TSSLP-2-4 Package outline
0.19
0.24
Solder mask
0.19
0.57
0.62
Copper
0.19
0.27
0.14
0.32
0.24
Figure 9
Stencil apertures
TSSLP-2-1,-2-FP V02
Figure 10
TSSLP-2-4 Footprint
g
0.35
Tape type
Ex Ey
Punched Tape
0.43 0.73
Embossed Tape 0.37 0.67
8
Ey
4
Cathode
marking
Figure 11
Deliveries can be both tape types (no selection possible).
Specification allows identical processing (pick & place) by users.
Ex
TSSLP-2-1,-2-TP V03
TSSLP-2-4 Packing
1
Type code
Pin 1 marking
TSSLP-2-3, -4-MK V01
Figure 12
TSSLP-2-4 Marking (example)
Final Data Sheet
11
Revision 1.3, 2014-06-12
ESD103-B1-02 Series
Package Information
4.2
TSLP-2-20 [2]
Top view
Bottom view
0.31 +0.01
-0.02
0.6 ±0.05
1±0.05
2
1
0.25 ±0.035 1)
0.65 ±0.05
0.05 MAX.
0.5 ±0.035 1)
Pin 1
marking
1) Dimension applies to plated terminals
TSLP-2-19, -20-PO V01
TSLP-2-20 Package outline
0.28
0.35
Solder mask
0.38
0.93
1
Copper
0.28
0.45
0.3
0.6
0.35
Figure 13
Stencil apertures
TSLP-2-19, -20-FP V01
Figure 14
TSLP-2-20 Footprint
0.4
1.16
Pin 1
marking
8
4
0.76
TSLP-2-19, -20-TP V02
Figure 15
TSLP-2-20 Packing
Type code
12
Pin 1 marking
TSLP-2-19, -20-MK V01
Figure 16
TSLP-2-20 Marking (example)
Final Data Sheet
12
Revision 1.3, 2014-06-12
ESD103-B1-02 Series
References
References
[1]
Infineon AG - Application Note AN210: Effective ESD Protection Design at System Level using VF-TLP
Characterization Methodology
[2]
Infineon AG - Recommendations for PCB Assembly of Infineon TSLP and TSSLP Packages
[3]
Tero, Ranta, Juha Ellä, Helena Pohjonen: Antenna Switch Linearity Requirements for GSM/WCDMA Mobile
Phone Front-Ends. Nokia Technology Platforms, P.O.Box 86, FIN-24101 SALO.
[4]
Infineon AC - Application Note AN327: ESD101-B1 / ESD103-B1, Bi-directional Ultra Low Capacitance
Transient Voltage Suppression Diodes for High Power RF Applications.
Final Data Sheet
13
Revision 1.3, 2014-06-12
ESD103-B1-02 Series
Revision History: Revision 1.2, 2013-07-22
Page or Item
Subjects (major changes since previous revision)
Revision 1.3, 2014-06-12
6
Table 5) updated
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Last Trademarks Update 2010-06-09
Final Data Sheet
3
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