1.5um BiCMOS Process

Process Introduction
1.5um BiCMOS Process Technology
Process features
Key Design Rules








P substrate and P-epi
Twin well
LOCOS
High performance bipolar devices
Dual gate oxide available(optional)
Low voltage CMOS(5V)
High voltage CMOS(30V)
High poly resistor(optional)
14 Masks

Double metal
Min. Width/Space(um)
Active
1.5/3
PBASE
3.0
Poly
1.5/2
Cont
1.5
M1
2/2
Via
2
M2
3/3
Device Specification
Device
HV NPN
(Ae=5x7um2)
NPN
(Ae=5x7um2)
HV LPNP
(Wb=4um )
LPNP
(Wb=4um )
LV-NMOS
(W/L=20/1.5)
LV-PMOS
(W/L=20/1.5)
HV-NMOS
(W/L=50/3)
HV-PMOS
(W/L=50/3)
Sheet Resistance
Capacitance
Parameter
Hfe(Ic=100uA)
BVebo(Iebo=1uA)
BVceo(Iceo=1uA)
Hfe(Ic=100uA)
BVebo(Iebo=1uA)
BVceo(Ic=1uA)
Hfe(Ic=10uA)
BVceo(Ic=1uA)
Hfe(Ic=10uA)
BVceo(Ic=1uA)
Vth(Vds=0.1V)
BVdss
Vth(Vds=-0.1V)
BVdss
Vth(Vds=0.1V)
BVdss
Vth(Vds=-0.1V)
BVdss
N+
P+
N+ Poly
High-R Poly
N-Well
Poly/N-Well(200A)
Poly/N-Well(600A)
Specification
Min
60
11
25
80
10
9
140
50
20
35
0.5
8
-0.9
-18
0.9
30
-1.6
25
60
18
1.6
0.8
1.55
0.5
Typ
13.6
-
Max
200
200
13.6
-
-
-
-
0.65
12
-0.75
-12
1.3
0.8
18
-0.6
-8
1.7
-1.2
-0.8
-30
55
100
32
2.4
1.4
1.95
0.65
40
80
25
2.0
1.1
1.75
0.58
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Ω/□
Ω/□
Ω/□
kΩ/□
kΩ/□
fF/um2
fF/um2
-1-
Process Introduction
Vertical NPN, CBE, with sink ——model name: VN5x7_D(LV)
-2-
Process Introduction
Vertical NPN, CBE, with sink ——model name: HN5x7_D(HV)
-3-
Process Introduction
Vertical NPN, Use Pwell as base, with sink
Model name: WN5x7_D
-4-
Process Introduction
Circle emitter Use pbase as emitter and collector
Emitter φ=7, Base width=4
Model name: LP7_4
-5-
Process Introduction
Low voltage NMOS L=1.5um~20um, W=2um~50um
Model name: nl
-6-
Process Introduction
Low voltage PMOS L=1.5um~20um, W=2um~50um
Model name: pl
-7-
Process Introduction
High voltage NMOS lmin=3.0um lmax=50um wmin=5um wmax=50um
model name: nh nh L=3um W=50um
-8-
Process Introduction
High Voltage PMOS lmin=3.0um lmax=50um wmin=5um wmax=50um
Model name: ph PH W=50um L=3um
-9-
Similar pages