Order this document by MTB50N06EL/D SEMICONDUCTOR TECHNICAL DATA !'" $ " ##$!"# !" %" !% $ ! & ((( N–Channel Enhancement–Mode Silicon Gate Motorola Preferred Device TMOS POWER FET LOGIC LEVEL 50 AMPERES 60 VOLTS RDS(on) = 0.028 OHM These TMOS Power FETs are designed for high speed, low loss power switching applications such as switching regulators, converters, solenoid and relay drivers. This Logic Level Series part is specified to operate with level logic gate–to–source voltage of 5 volt and 4 volt. • Silicon Gate for Fast Switching Speeds • Low RDS(on) — 0.028 Ω max • Replace External Zener Transient Suppressor — Absorbs High Energy in the Avalanche Mode • Specially Designed Leadframe for Maximum Power Dissipation • Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number D G MAXIMUM RATINGS (TC = 25°C unless otherwise noted) CASE 418B–02, Style 2 D2PAK S Symbol Value Unit Drain–Source Voltage VDSS 60 Vdc Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 60 Vdc Gate–Source Voltage — Continuous VGS ±15 Vdc Drain Current — Continuous Drain Current — Continuous @ 100°C Drain Current — Single Pulse (tp ≤ 10 µs) ID ID IDM 50 28 142 Adc Total Power Dissipation Derate above 25°C Total Power Dissipation @ TA = 25°C, when mounted with the minimum recommended pad size PD 125 1.0 2.5 Watts W/°C Watts TJ, Tstg – 55 to 150 °C Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 25 Vdc, VGS = 5.0 Vpk, IL = 50 Apk, L = 0.32 mH, RG = 25 Ω ) EAS 400 mJ Thermal Resistance — Junction to Case Thermal Resistance — Junction to Ambient Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size RθJC RθJA RθJA 1.0 62.5 50 °C/W TL 260 °C Rating Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Apk This document contains information on a new product. Specifications and information herein are subject to change without notice. E–FET, Designer’s and L2TMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company Preferred devices are Motorola recommended choices for future use and best overall value. REV 1 TMOS Motorola Motorola, Inc. 1994 Power MOSFET Transistor Device Data 1 MTB50N06EL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Min Typ Max Unit 60 — — 64 — — Vdc mV/°C — — — — 10 100 — — 100 nAdc 1.0 — — 4.78 2.0 — Vdc mV/°C — — — — 0.028 0.039 Ohm — — — — 1.68 1.40 gFS 17 — — mhos Ciss — 3100 4340 pF Coss — 1065 1491 Crss — 260 520 td(on) — 21 42 tr — 365 730 td(off) — 55 110 tf — 150 300 QT — 52 73 Q1 — 13 — Q2 — 34 — Q3 — 27 — — — 1.52 1.1 2.5 — trr — 200 — ns Internal Drain Inductance (Measured from the tab to center of die) Ld — 3.5 — nH Internal Source Inductance (Measured from the source lead 0.1″ from package to source bond pad) Ls — 7.5 — nH Characteristic OFF CHARACTERISTICS Drain–Source Breakdown Voltage (VGS = 0 V, ID = 250 µAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0) (VDS = 60 Vdc, VGS = 0, TJ = 125°C) IDSS Gate–Body Leakage Current (VGS = ±15 Vdc, VDS = 0) IGSS µAdc ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) Temperature Coefficient (Negative) VGS(th) Static Drain–Source On–Resistance (VGS = 5.0 Vdc, ID = 25 Adc) (VGS = 4.0 Vdc, ID = 25 Adc) RDS(on) Drain–Source On–Voltage (VGS = 5.0 Vdc) (ID = 50 Adc) (ID = 25 Adc, TJ = 125°C) VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 25 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn–On Delay Time (VDD = 25 Vdc, ID = 50 Adc, VGS = 5.0 Vdc, RG = 9.1 Ω) Rise Time Turn–Off Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 50 Adc, VGS = 5.0 Vdc) ns nC SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage VSD (IS = 50 Adc, VGS = 0) (IS = 50 Adc, VGS = 0, TJ = °C) Reverse Recovery Time (IS = 50 Adc, VGS = 0 , dIS/dt = 100 A/µs) Vdc INTERNAL PACKAGE INDUCTANCE (1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. (2) Switching characteristics are independent of operating junction temperature. 2 Motorola TMOS Power MOSFET Transistor Device Data MTB50N06EL PACKAGE DIMENSIONS C E V B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 4 A S 1 2 3 -TSEATING PLANE STYLE 2: PIN 1. 2. 3. 4. K J G H D 3 PL 0.13 (0.005) M T GATE DRAIN SOURCE DRAIN DIM A B C D E G H J K S V INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.575 0.625 0.045 0.055 MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 14.60 15.88 1.14 1.40 CASE 418B–02 ISSUE B Motorola TMOS Power MOSFET Transistor Device Data 3 MTB50N06EL Motorola reserves the right to make changes without further notice to any products herein. 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ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 4 ◊ *MTB50N06EL/D* Motorola TMOS Power MOSFET Transistor Device Data MTB50N06EL/D