VND670SP ® DUAL HIGH SIDE SWITCH WITH DUAL POWER MOS GATE DRIVER (BRIDGE CONFIGURATION) TYPE VND670SP ■ RDS(on) 30 mΩ IOUT 15 A VDSS 40 V OUTPUT CURRENT:15A PER CHANNEL 5V LOGIC LEVEL COMPATIBLE INPUTS GATE DRIVE FOR TWO EXTERNAL POWER MOS ■ UNDERVOLTAGE AND OVERVOLTAGE SHUT-DOWN ■ OVERVOLTAGE CLAMP ■ THERMAL SHUT DOWN ■ CROSS-CONDUCTION PROTECTION ■ CURRENT LIMITATION ■ VERY LOW STAND-BY POWER CONSUMPTION ■ PWM OPERATION UP TO 10 KHz ■ PROTECTION AGAINST: LOSS OF GROUND AND LOSS OF VCC ■ REVERSE BATTERY PROTECTION (*) ■ ■ 10 1 PowerSO-10™ configuration. The device integrates two 30 mΩ Power MOSFET in high side configuration, and provides gate drive for two external Power MOSFET used as low side switches. INA and INB allow to select clockwise or counter clockwise drive or brake; DIAGA/ENA, DIAGB/ENB allow to disable one half bridge and feedback diagnostic. Built-in thermal shut-down, combined with a current limiter, protects the chip in overtemperature and short circuit conditions. Short to battery protects the external connected low-side Power MOSFET. DESCRIPTION The VND670SP is a monolithic device made using STMicroelectronics VIPower technology M0-3, intended for driving motors in full bridge BLOCK DIAGRAM VCC Undervolt. IN A INTERNAL SUPPLY Short to battery INB OUTA LOGIC DIAGA/ENA Short to battery OUTB DIAGB/EN B GATEA PWM Overtemp. A Overtemp. B Current Limiter B Current Limiter A GATEB GND (*) See note at page 5 January 2003 1/14 VND670SP ABSOLUTE MAXIMUM RATING Symbol VCC Imax1 Imax2 IR IIN IEN Ipw Igs VESD Tj TSTG Parameter Supply voltage Maximum output current (continuous) Maximum output current (250 ms pulse duration) Reverse output current (continuous) Input current Enable pin current PWM pin current Output gate current Electrostatic discharge (R=1.5kΩ, C=100pF) Junction operating temperature Storage temperature Value -0.3 .. 40 15 20 -15 +/- 10 +/- 10 +/- 10 +/- 20 2000 -40 to 150 -55 to 150 Unit V A A A mA mA mA mA V °C °C CURRENT AND VOLTAGE CONVENTIONS ICC VCC IINA IINB IENA IENB VCC INA IOUTA OUTA INB OUTB DIAGA/ENA GATE A DIAGB/ENB GATE B IOUTB IgsB VOUTB VgsA GND PWM VOUTA IgsA VgsB Ipw VINA VINB VENA VENB IGND Vpw CONNECTION DIAGRAM (TOP VIEW) 5 4 3 6 7 8 9 10 INPUT B DIAGB/ENB PWM DIAGA/ENA INPUT A 2 1 11 VCC 2/14 OUTPUT B GATE B GROUND GATE A OUTPUT A VND670SP THERMAL DATA Symbol Rthj-case Rthj-amb (*) Parameter Thermal resistance junction-case (per channel) Thermal resistance junction-ambient Value 1.4 50 (MAX) (MAX) Unit °C/W °C/W (*) When mounted using the recommended pad size on FR-4 board (See AN515 Application Note). ELECTRICAL CHARACTERISTICS (VCC=9V up to 18V; -40°C<Tj<150°C; unless otherwise specified) POWER Symbol VCC RON Is Vgate Vgs,cl Parameter Operating supply voltage On state resistance Supply current Gate output voltage Gate output clamp voltage Test Conditions Min 5.5 Typ Max 36 50 Unit V mΩ 26 30 15 mΩ mΑ 6.8 40 8.5 8.0 µA V V Min Typ 50 45 50 40 160 230 0.5 2.6 1.0 2.2 Max 150 135 150 120 500 1200 2 10 5.0 10 Unit µs µs µs µs V/ms V/ms µs µs µs µs 150 600 1800 µs Min Typ Max 5.5 36 30 43 45 Unit V V A 150 170 200 °C VCC-41 V 5.5 V ILOAD=12A ILOAD=12A; Tj=25oC ON state OFF state Igs=-1 mA 5.0 6.0 SWITCHING (VCC=13V, RLOAD =1.1Ω) Symbol tD(on) tD(off) tr tf (dVOUT/dt)on (dVOUT/dt)off tdong trg tdoffg tfg tdel Parameter Turn-on delay time Turn-off delay time Output voltage rise time Output voltage fall time Turn-on voltage slope Turn-off voltage slope VgsTurn-on delay time Vgs rise time VgsTurn-off delay time Vgs fall time External MOSFET turn-on dead time Test Conditions Input rise time < 1µs (see fig. 1) C1=4.7nF Break to ground configuration (see fig. 2) (see fig. 3) PROTECTION AND DIAGNOSTIC Symbol VUSD VOV ILIM TTSD Parameter Undervoltage shut-down Overvoltage shut-down Current limitation Thermal shut-down temperature Vocl Output turn-off clamp voltage Vsat External MOSFET saturation voltage detection threshold Test Conditions VIN = 3.25 V ILOAD=12A, L=6mH VCC-55 2.5 4.2 3/14 1 VND670SP ELECTRICAL CHARACTERISTICS (continued) PWM Symbol Vpwl Ipwl Vpwh Ipwh Vpwhhyst Vpwcl Vpwtest Ipwtest Parameter PWM low level Test Conditions voltage PWM pin current PWM high level Vpw=1.5V voltage PWM pin current PWM hysteresis voltage Vpw=3.25V PWM clamp voltage Min Typ Max Unit 1.5 V 1 µA 3.25 V 10 µA V V 0.5 VCC+0.3 VCC+0.7 VCC+1.0 -5.0 -3.5 -2000 -3.5 -2.0 -500 -2.0 -0.5 V V µA Test Conditions Min Typ Max 1.5 VIN=1.5 V 1 3.25 Ipw = 1 mA Ipw = -1 mA Test mode PWM pin voltage Test mode PWM pin current Vpwtest = -2.0 V LOGIC INPUT (INA/INB) Symbol VIL IINL VIH IINH VIHYST IIN=1mA 0.5 6.0 6.8 8.0 Unit V µA V µA V V IIN=-1mA -1.0 -0.7 -0.3 V Parameter Test Conditions Normal operation Min Typ Max Unit VENL Enable low level voltage 1.5 V IENL Enable pin current (DIAGX/ENX pin acts as an input pin) VEN= 1.5 V Normal operation VENH Enable high level voltage IENH Enable pin current VICL Parameter Input low level voltage Input current Input high level voltage Input current Input hysteresis voltage Input clamp voltage VIN=3.25 V 10 ENABLE (LOGIC I/O PIN) Symbol VEHYST Enable hysteresis voltage VENCL Enable clamp voltage VDIAG Enable output low level voltage 1 µA (DIAGX/ENX pin acts as an input pin) VEN= 3.25 V Normal operation 3.25 V (DIAGX/ENX pin acts as an input pin) IEN=1mA 0.5 6.0 6.8 8.0 V IEN=-1mA Fault operation -1.0 -0.7 -0.3 V 0.4 V (DIAGX/ENX pin acts as an input pin) IEN=1.6 mA 4/14 2 10 µA V VND670SP WAVEFORMS AND TRUTH TABLE TRUTH TABLE IN NORMAL OPERATING CONDITIONS In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the device. This pin must be externally pulled high. INA INB DIAGA/ENA DIAGB/ENB OUTA OUTB GATEA GATEB 1 1 0 0 X 1 0 X X 1 0 1 0 X X X 1 0 1 1 1 1 0 1 1 0 0 1 1 1 1 0 0 0 1 1 H H L L L H L L L H L H L L L L H L L L H H L L H L L L H L H L L L L H Comment Brake to VCC Clockwise Counter cw Brake to GND Stand by HSA only MOSA only HSB only MOSB only PWM pin usage: In all cases, a “0” on the PWM pin will turn-off both GATEA and GATEB outputs. When PWM rises back to “1”, GATEA or GATEB turn on again depending on the input pin state. TYPICAL APPLICATION CIRCUIT FOR DC TO 10KHz PWM OPERATION +5V +5V R1 R1 VCC Rprot Rprot 1K 1K DIAGB/ENB DIAGA/EN A VND670SP Rprot 1K GND OUTA PWM OUTB Rgnd (*) Rprot 1K Rprot INA INB GATEA UP 1K GATEB M DOWN External Power Mos A External Power Mos B (*) Reverse battery protection: - series relay in VCC line: Rgnd=0 Ohms - series fuse in VCC line with antiparallel diode between ground and VCC: Rgnd=10 Ohms. Layout hints: The connection between GND pin of the VN670SP and the Power MOSFET SOURCE connections should be kept short enough to ensure that the dynamic difference between these two points never exceed 1V for the bridge to operate properly. 5/14 VND670SP TYPICAL APPLICATION CIRCUIT FOR A 20KHZ PWM OPERATION +5V +5V R1 R1 VCC Rprot Rprot 1K 1K DIAGB/ENB DIAGA/ENA VND670SP Rprot 1K OUTA INA OUTB Rgnd(*) Rprot 1K Rprot PWM INB UP GATEA GATEB M D1 D2 DOWN 27Ω 27Ω External Power Mos A External Power Mos B (*) Reverse battery protection: - series relay in VCC line: Rgnd=0 Ohms - series fuse in VCC line with antiparallel diode between ground and VCC: Rgnd=10 Ohms. 6/14 1K VND670SP WAVEFORMS AND TRUTH TABLE (CONTINUED) In case of a fault condition the DIAGX/ENX pin is considered as an output pin by the device. The fault conditions are: - overtemperature on one or both high sides; - short to battery condition on the output (saturation detection on the external connected Power MOSFET). Possible origins of fault conditions may be: OUTA is shorted to ground ---> overtemperature detection on high side A. OUTA is shorted to VCC ---> external Power MOSFET saturation detection (driven by GATEA). When a fault condition is detected, the user can know which power element is in fault by monitoring the INA, INB, DIAGA/ ENA and DIAGB/ENB pins. In any case, when a fault is detected, the faulty half bridge is latched off. To turn-on the respective output (GATEX or OUTX) again, the input signal must rise from low to high level. TRUTH TABLE IN FAULT CONDITIONS (detected on OUTA) INA INB DIAGA/ENA DIAGB/ENB OUTA OUTB GATEA GATEB 1 1 0 1 OPEN H L L 1 0 0 1 OPEN OPEN L L 0 1 0 1 OPEN H L L 0 0 0 1 OPEN OPEN L L X X 0 0 OPEN OPEN L L 1 X 0 0 OPEN OPEN L L 0 X 0 0 OPEN OPEN L L X 1 0 1 OPEN H L L X 0 0 1 OPEN OPEN L L Fault Information Protection Action TEST MODE The PWM pin allows to test the load connection between two half-bridges. In the test mode (Vpwm=-2V) the external Power Mos gate drivers are disabled. The INA or INB inputs allow to turn-on the High Side A or B, respectively, in order to connect one side of the load at VCC voltage. The check of the voltage on the other side of the load allow to verify the continuity of the load connection. In case of load disconnection the DIADX/ENX pin corresponding to the faulty output is pulled down. 7/14 VND670SP ELECTRICAL TRANSIENT REQUIREMENTS ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 Class C E 8/14 1 Test Level Test Level Test Level Test Level Test Levels I II III IV Delays and Impedance -25V +25V -25V +25V -4V +26.5V -50V +50V -50V +50V -5V +46.5V -75V +75V -100V +75V -6V +66.5V -100V +100V -150V +100V -7V +86.5V 2ms, 10Ω 0.2ms, 10Ω 0.1µs, 50Ω 0.1µs, 50Ω 100ms, 0.01Ω 400ms, 2Ω Test Levels Result Test Levels Result Test Levels Result Test Levels Result I II III IV C C C C C C C C C C C E C C C C C E C C C C C E Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. VND670SP Figure 1: Test conditions for High Side switching times measurement. VOUTA, B 90% 80% (dVOUT/dt)off (dVOUT/dt)on 10% t VINA, B td(off) tf td(on) tr t Figure 2: Test conditions for external Power MOSFET switching times measurement. VgsA, B 90% 80% 20% 10% Vpw tdong tdoffg trg t tfg t Figure 3: Definition of the external Power MOSFET turn-on dead time tdel INA INB OUTA VgsA tdel 9/14 1 VND670SP Waveforms NORMAL OPERATION (DIAGA/ENA=1, DIAGB/EN B=1) DIAGA/ENA DIAGB/ENB INA INB PWM OUTA OUTB GATE A GATEB NORMAL OPERATION (DIAGA/EN A=1, DIAGB/ENB=0 and DIAGA/ENA=0, DIAGB/ENB=1) DIAGA/ENA DIAGB/ENB INA INB PWM OUTA OUTB GATE A GATEB CURRENT LIMITATION/THERMAL SHUTDOWN or OUTA SHORTED TO GROUND INA INB ILIM IOUTA TTSD Tj DIAGA/ENA DIAGB/ENB GATEA GATEB normal operation 10/14 OUTA shorted to ground normal operation VND670SP Waveforms (Continued) OUTA shorted to VCC and undervoltage shutdown INA INB OUTA OUTB GATE A GATEB DIAGB/ENB DIAGA/ENA normal operation OUTA shorted to VCC normal operation undervoltage shutdown Load disconnection test (INA=1, PWM=-2V) INA INB PWM (test mode) OUTA OUTB GATEA GATE B DIAGA/ENA DIAGB/ENB load connected load disconnected load connected back 11/14 1 VND670SP PowerSO-10™ MECHANICAL DATA mm. DIM. MIN. A A (*) A1 B B (*) C C (*) D D1 E E2 E2 (*) E4 E4 (*) e F F (*) H H (*) h L L (*) α α (*) inch TYP 3.35 3.4 0.00 0.40 0.37 0.35 0.23 9.40 7.40 9.30 7.20 7.30 5.90 5.90 MAX. MIN. 3.65 3.6 0.10 0.60 0.53 0.55 0.32 9.60 7.60 9.50 7.60 7.50 6.10 6.30 0.132 0.134 0.000 0.016 0.014 0.013 0.009 0.370 0.291 0.366 0.283 0.287 0.232 0.232 1.35 1.40 14.40 14.35 0.049 0.047 0.543 0.545 1.80 1.10 8º 8º 0.047 0.031 0º 2º TYP. 1.27 0.050 1.25 1.20 13.80 13.85 0.053 0.055 0.567 0.565 0.50 0.002 1.20 0.80 0º 2º 0.070 0.043 8º 8º (*) Muar only POA P013P B 0.10 A B 10 H E E2 E4 1 SEATING PLANE e B DETAIL "A" A C 0.25 h D = D1 = = = SEATING PLANE A F A1 A1 L DETAIL "A" α 12/14 1 MAX. 0.144 0.142 0.004 0.024 0.021 0.022 0.0126 0.378 0.300 0.374 300 0.295 0.240 0.248 P095A VND670SP PowerSO-10™ SUGGESTED PAD LAYOUT TUBE SHIPMENT (no suffix) 14.6 - 14.9 CASABLANCA B 10.8- 11 MUAR C 6.30 C A A 0.67 - 0.73 10 9 1 9.5 2 3 B 0.54 - 0.6 All dimensions are in mm. 8 7 4 5 1.27 Base Q.ty Bulk Q.ty Tube length (± 0.5) 6 Casablanca Muar 50 50 1000 1000 532 532 A B C (± 0.1) 10.4 16.4 4.9 17.2 0.8 0.8 TAPE AND REEL SHIPMENT (suffix “13TR”) REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (± 0.1) P D (± 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) All dimensions are in mm. 24 4 24 1.5 1.5 11.5 6.5 2 End Start Top No components Components No components cover tape 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed 13/14 1 VND670SP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 2002 STMicroelectronics - Printed in ITALY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 14/14 1