2SJ529(L),2SJ529(S) Silicon P Channel MOS FET High Speed Power Switching ADE-208-654A (Z) 2nd. Edition June 1, 1998 Features • Low on-resistance R DS(on) = 0.12 Ω typ. • 4 V gete drive devices • High speed switching Outline DPAK–2 4 4 D 1 2 G 1 2 S 3 3 1. Gate 2. Drain 3. Source 4. Drain 2SJ529(L),2SJ529(S) Absolute Maximum Ratings (Ta = 25°C) Item Symbol Ratings Unit Drain to source voltage VDSS –60 V Gate to source voltage VGSS ±20 V Drain current ID –10 A –40 A –10 A –10 A 8.5 mJ 20 W Drain peak current I D(pulse) Body-drain diode reverse drain current I DR Avalenche current Avalenche energy I AP Note1 Note3 EAR Note3 Note2 Channel dissipation Pch Channel temperature Tch 150 °C Storage temperature Tstg –55 to +150 °C Note: 2 1. PW ≤ 10µs, duty cycle ≤ 1 % 2. Value at Tc = 25°C 3. Value at Tch = 25°C, Rg ≥ 50 Ω 2SJ529(L),2SJ529(S) Electrical Characteristics (Ta = 25°C) Item Symbol Min Typ Max Unit Test Conditions Drain to source breakdown voltage V(BR)DSS –60 — — V I D = –10mA, VGS = 0 Gate to source breakdown voltage V(BR)GSS ±20 — — V I G = ±100µA, VDS = 0 Zero gate voltege drain current I DSS — — –10 µA VDS = –60 V, VGS = 0 Gate to source leak current I GSS — — ±10 µA VGS = ±16V, VDS = 0 Gate to source cutoff voltage VGS(off) –1.0 — –2.0 V I D = –1mA, VDS = –10V Static drain to source on state RDS(on) — 0.12 0.16 Ω I D = –5A, VGS = –10V Note4 resistance RDS(on) — 0.17 0.24 Ω I D = –5A, VGS = –4V Note4 Forward transfer admittance |yfs| 4.5 7.5 — S I D = –5A, VDS = –10V Input capacitance Ciss — 580 — pF VDS = –10V Output capacitance Coss — 300 — pF VGS = 0 Reverse transfer capacitance Crss — 85 — pF f = 1MHz Turn-on delay time t d(on) — 10 — ns VGS = –10V, ID = –5A Rise time tr — 40 — ns RL = 6Ω Turn-off delay time t d(off) — 85 — ns Fall time tf — 60 — ns Body–drain diode forward voltage VDF — –1.2 — V I F = –10A, VGS = 0 Body–drain diode reverse recovery time t rr — 60 — ns I F = –10A, VGS = 0 diF/ dt = 50A/µs Note: Note4 4. Pulse test 3 2SJ529(L),2SJ529(S) Main Characteristics Power vs. Temperature Derating –100 I D (A) Drain Current 30 20 10 50 100 Case Temperature 150 200 Tc (°C) –20 0 = O pe –0.5 10 m s ra tio n –2 Operation in this area is limited by R DS(on) µs µs (1 (T sh ot ) c= 25 ) –0.2 Ta = 25 °C –0.1 –0.1 –0.3 –1 –3 –10 –30 –100 Drain to Source Voltage V DS (V) Typical Transfer Characteristics –10 –10 V –5 V V DS = –10 V Pulse Test –4 V ID Pulse Test (A) –3.5 V –6 –3 V –4 –2 –2.5 V Drain Current I D (A) –8 C –5 Typical Output Characteristics –10 PW D –10 –1 10 10 s m Channel Dissipation –50 0 Drain Current Maximum Safe Operation Area 1 Pch (W) 40 –8 –6 –4 Tc = 75 °C 25 °C –2 –25 °C VGS = –2 V 0 4 –2 –4 –6 Drain to Source Voltage –8 –10 V DS (V) 0 –1 –2 –3 Gate to Source Voltage –4 –5 V GS (V) 2SJ529(L),2SJ529(S) Drain to Source Saturation Voltage vs. Gate to Source Voltage –0.8 I D = –5 A –0.6 –0.4 –2 A –0.2 0 –1 A –4 –8 –12 Static Drain to Source on State Resistance R DS(on) ( Ω) Gate to Source Voltage –16 0.1 0 –40 I D = –5 A –2 A V GS = –4 V –1 A –5 A –1, –2 A –10 V 0 40 80 Case Temperature VGS = –4 V 0.2 0.1 –10 V 0.05 0.02 Pulse Test 0.01 –0.1 –0.3 V GS (V) 0.4 0.2 0.5 –20 Static Drain to Source on State Resistance vs. Temperature 0.5 Pulse Test 0.3 Drain to Source On State Resistance R DS(on) ( Ω ) Pulse Test 120 Tc (°C) 160 –1 –3 Drain Current –10 –30 –100 I D (A) Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |y fs | (S) Drain to Source Saturation Voltage V DS(on) (V) –1.0 Static Drain to Source on State Resistance vs. Drain Current 1 20 10 Ta = –25 °C 5 25 °C 2 75 °C 1 0.5 0.1 –0.1 –0.2 V DS = –10 V Pulse Test –0.5 –1 –2 –5 –10 Drain Current I D (A) 5 2SJ529(L),2SJ529(S) Reverse Recovery Time trr (ns) 500 Body–Drain Diode Reverse Recovery Time 2000 Ciss Capacitance C (pF) 200 100 50 20 500 200 Crss 100 50 Coss 10 20 di / dt = 50 A / µs VGS = 0, Ta = 25 °C 10 0 –20 –40 I D = –10 A V DS V GS –60 –80 –100 0 –4 –12 V DD = –10 V –25 V –50 V 8 16 Gate Charge –8 –16 24 32 Qg (nc) –20 40 1000 Switching Time t (ns) V DD = –10 V –25 V –50 V V GS (V) 0 Gate to Source Voltage V DS (V) 0 –10 –20 –30 –40 –50 Drain to Source Voltage V DS (V) Dynamic Input Characteristics Drain to Source Voltage VGS = 0 f = 1 MHz 1000 5 –0.1 –0.2 –0.5 –1 –2 –5 –10 Reverse Drain Current I DR (A) 6 Typical Capacitance vs. Drain to Source Voltage Switching Characteristics V GS = –10 V, V DD = –30 V Pw = 5 µs, duty < 1 % 300 t d(off) 100 tf 30 tr t d(on) 10 3 1 –0.1 –0.2 –0.5 –1 Drain Current –2 I D (A) –5 –10 2SJ529(L),2SJ529(S) Repetitive Avalanche Energy EAR (mJ) –10 Maximum Avalanche Energy vs. Channel Temperature Derating Reverse Drain Current vs. Source to Drain Voltage Reverse Drain Current I DR (A) Pulse Test –8 –6 –10 V V GS = 0, 5 V –4 –5 V –2 0 –0.4 –0.8 –1.2 Source to Drain Voltage –1.6 –2.0 20 I AP = –10 A V DD = –25 V duty < 0.1 % Rg > 50 Ω 16 12 8 4 0 25 V SD (V) 50 100 125 150 Channel Temperature Tch (°C) Avalanche Test Circuit V DS Monitor 75 Avalanche Waveform EAR = L 1 2 • L • I AP • 2 I AP Monitor VDSS VDSS – V DD V (BR)DSS I AP Rg D. U. T V DS VDD ID Vin –15 V 50Ω 0 VDD 7 2SJ529(L),2SJ529(S) Normalized Transient Thermal Impedance vs. Pulse Width Normalized Transient Thermal Impedance γ s (t) 3 Tc = 25°C 1 D=1 0.5 0.3 0.1 0.2 0.1 0.05 θ ch – c(t) = γ s (t) • θ ch – c θ ch – c = 6.25 °C/W, Tc = 25 °C 0.02 e uls 1 0.03 0.0 PDM P ot D= h 1s PW T PW T 0.01 10 µ 100 µ 1m 10 m 100 m Pulse Width 10 PW (S) Switching Time Test Circuit Waveform Vout Monitor Vin Monitor 1 Vin 10% D.U.T. RL 90% Vin –10 V 50Ω V DD = –30 V Vout td(on) 8 90% 90% 10% 10% tr td(off) tf 2SJ529(L),2SJ529(S) 9.5 ± 0.5 1.2 Max 16.2 ± 0.5 3.1 ± 0.5 2.29 ± 0.5 0.55 ± 0.1 L type 1.2 typ 2.29 ± 0.5 2.5 ± 0.5 4.7 ± 0.5 2.3 ± 0.5 0.55 ± 0.1 1.15 ± 0.1 0.8 ± 0.1 2.29 ± 0.5 2.29 ± 0.5 5.5 ± 0.5 6.5 ± 0.5 5.4 ± 0.5 1.15 ± 0.1 0.8 ± 0.1 1.7 ± 0.5 2.3 ± 0.2 0.55 ± 0.1 5.5 ± 0.5 6.5 ± 0.5 5.4 ± 0.5 1.7 ± 0.5 Package Dimensions (Unit: mm) S type 0 ~ 0.25 0.55 ± 0.1 Hitachi EIAJ ( L type) EIAJ ( S type) JEDEC DPAK–2 SC–63 SC–64 — 9 2SJ529(L),2SJ529(S) Cautions 1. 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Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. 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