H7N0310LD, H7N0310LS, H7N0310LM Silicon N Channel MOS FET High Speed Power Switching ADE-208-1422C(Z) 4th. Edition Aug. 2002 Features • Low on-resistance • RDS(on) = 8 mΩ typ. • Low drive current Outline LDPAK 4 4 4 D 1 G 1 2 2 3 H7N0310LS 3 S H7N0310LD 1 2 3 H7N0310LM 1. Gate 2. Drain 3. Source 4. Drain H7N0310LD, H7N0310LS, H7N0310LM Absolute Maximum Ratings (Ta = 25°C) Item Symbol Ratings Unit Drain to source voltage VDSS 30 V Gate to source voltage VGSS ±20 V Drain current ID 30 A 120 A 30 A 50 W Note 1 Drain peak current ID(pulse) Body-drain diode reverse drain current IDR Channel dissipation Pch Channel to Case Thermal Impedance θch-c 2.5 °C/W Channel temperature Tch 150 °C Storage temperature Tstg –55 to +150 °C Notes: 1. PW ≤ 10µs, duty cycle ≤ 1 % 2. Value at Tc = 25°C Rev.3, Aug. 2002, page 2 of 12 Note 2 H7N0310LD, H7N0310LS, H7N0310LM Electrical Characteristics (Ta = 25°C) Item Symbol Min Typ Max Unit Test Conditions V ID = 10 mA, VGS = 0 Drain to source breakdown voltage V(BR)DSS 30 — — Gate to source breakdown voltage V(BR)GSS ±20 — — Gate to source leak current IGSS — — ±10 µA VGS = ±16 V, VDS = 0 Zero gate voltege drain current IDSS — — 10 µA VDS = 30 V, VGS = 0 Gate to source cutoff voltage VGS(off) 1.0 — 2.5 V ID = 1 mA, VDS = 10 V Static drain to source on state RDS(on) — 8.0 10 mΩ ID = 15 A, VGS = 10 V — 13 19 mΩ ID = 15 A, VGS = 5 V 21 35 — S ID = 15 A, VDS = 10 V resistance Forward transfer admittance |yfs| IG = ±100 µA, VDS = 0 Note1 Note1 Note1 Input capacitance Ciss — 1400 — pF VDS = 10 V Output capacitance Coss — 380 — pF VGS = 0 Reverse transfer capacitance Crss — 210 — pF f = 1 MHz Total gate charge Qg — 24 — nc VDD = 10 V Gate to source charge Qgs — 4.8 — nc VGS = 10 V Gate to drain charge Qgd — 4.6 — nc ID = 30 A Turn-on delay time td(on) — 21 — ns VGS = 10 V, ID = 15 A Rise time tr — 250 — ns RL = 0.67 Ω Turn-off delay time td(off) — 55 — ns Rg = 4.7 Ω Fall time tf — 16 — ns Body–drain diode forward voltage VDF — 0.90 — V IF = 30 A, VGS = 0 — 35 — ns IF = 30 A, VGS = 0 diF/ dt = 50 A/µs Body–drain diode reverse recovery trr time Note1 Notes: 1. Pulse test Rev.3, Aug. 2002, page 3 of 12 H7N0310LD, H7N0310LS, H7N0310LM Main Characteristics Power vs. Temperature Derating Maximum Safe Operation Area 500 I D (A) 10 µs 60 100 10 Drain Current Channel Dissipation Pch (W) 80 40 20 Op PW era tio 1 0.1 50 100 Case Temperature 150 200 n =1 0m s Operation in this area is limited by R DS(on) Tc (°C) 0.01 0.1 0.3 1 3 10 30 100 Drain to Source Voltage V DS (V) Typical Output Characteristics 50 Typical Transfer Characteristics 50 10 V V DS = 10 V Pulse Test 4V Pulse Test (A) 6V 30 ID 40 3.5 V Drain Current I D (A) DC Tc = 25°C 1 shot Pulse 0 Drain Current 10 0 1 m µs s 20 10 VGS = 3 V 40 30 20 25°C 10 Tc = 75°C −25°C 0 2 4 6 Drain to Source Voltage Rev.3, Aug. 2002, page 4 of 12 8 V DS (V) 10 0 1 2 3 Gate to Source Voltage 5 4 V GS (V) H7N0310LD, H7N0310LS, H7N0310LM Static Drain to Source on State Resistance vs. Drain Current 100 Pulse Test 50 0.4 0.2 10 A 5A 0.1 0 Static Drain to Source on State Resistance R DS(on) (m Ω) I D = 20 A 4 8 12 Gate to Source Voltage 16 20 V GS (V) Static Drain to Source on State Resistance vs. Temperature 40 Pulse Test 32 24 16 I D = 5 A, 10 A 20 A V GS = 5 V 8 10 V 0 −40 Drain to Source On State Resistance R DS(on) (m Ω) 0.3 Pulse Test 5 A, 10 A, 20 A 0 40 80 120 160 Case Temperature Tc (°C) 20 VGS = 5 V 10 10 V 5 2 1 0.1 0.2 0.5 1 2 5 10 20 50 100 Drain Current I D (A) Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |yfs| (S) V DS(on) (V) 0.5 Drain to Source Voltage Drain to Source Saturation Voltage vs. Gate to Source Voltage 100 Tc = −25°C 30 10 75°C 25°C 3 1 0.3 0.1 0.1 V DS = 10 V Pulse Test 0.3 1 3 10 30 100 Drain Current I D (A) Rev.3, Aug. 2002, page 5 of 12 H7N0310LD, H7N0310LS, H7N0310LM Typical Capacitance vs. Drain to Source Voltage Body-Drain Diode Reverse Recovery Time 500 3000 Capacitance C (pF) 10000 Reverse Recovery Time trr (ns) 1000 200 100 50 20 10 0.1 Ciss 1000 Coss 300 Crss 100 30 di / dt = 50 A / µs V GS = 0, Ta = 25°C VGS = 0 f = 1 MHz 10 0 0.3 1 3 10 30 100 Reverse Drain Current I DR (A) 20 10 0 12 8 VDD = 25 V 10 V 5V 8 16 24 32 Gate Charge Qg (nc) Rev.3, Aug. 2002, page 6 of 12 4 0 40 20 30 40 50 Switching Characteristics tr Switching Time t (ns) V DS V DD = 25 V 10 V 5V 16 V GS (V) V GS 40 30 500 20 I D = 30 A Gate to Source Voltage Drain to Source Voltage V DS (V) Dynamic Input Characteristics 50 10 Drain to Source Voltage V DS (V) 200 100 t d(off) 50 t d(on) 20 tf 10 V GS = 10 V, V DS = 10 V Rg = 4.7 Ω, duty < 1 % 5 2 5 10 20 0.1 0.2 0.5 1 Drain Current I D (A) 50 100 H7N0310LD, H7N0310LS, H7N0310LM Reverse Drain Current vs. Source to Drain Voltage Reverse Drain Current I DR (A) 50 40 10 V 30 V GS = 0 5V 20 10 Pulse Test 0 0.4 0.8 1.2 Source to Drain Voltage 1.6 2.0 V SD (V) Normalized Transient Thermal Impedance vs. Pulse Width Normalized Transient Thermal Impedance γ s (t) 3 Tc = 25°C 1 D=1 0.5 0.3 0.1 0.03 0.2 θch − c(t) = γs (t) • θch − c θch − c = 2.5°C/ W, Tc = 25°C 0.1 0.05 0.02 e 1 0.0 puls t o h 1s PDM D= PW T PW T 0.01 10 µ 100 µ 1m 10 m 100 m 1 10 Pulse Width PW (s) Rev.3, Aug. 2002, page 7 of 12 H7N0310LD, H7N0310LS, H7N0310LM Switching Time Test Circuit Switching Time Waveform Vout Monitor Vin Monitor Rg 90% D.U.T. RL Vin Vin 10 V V DS = 10 V Vout 10% 10% 90% td(on) Rev.3, Aug. 2002, page 8 of 12 tr 10% 90% td(off) tf H7N0310LD, H7N0310LS, H7N0310LM Package Dimensions • H7N0310LD Unit: mm 2.54 ± 0.5 (1.4) 2.54 ± 0.5 11.0 ± 0.5 10.0 0.2 0.86 +– 0.1 11.3 ± 0.5 1.37 ± 0.2 1.3 ± 0.2 4.44 ± 0.2 1.3 ± 0.15 + 0.3 – 0.5 8.6 ± 0.3 10.2 ± 0.3 2.49 ± 0.2 0.4 ± 0.1 Hitachi Code JEDEC JEITA Mass (reference value) LDPAK (L) — — 1.4 g Rev.3, Aug. 2002, page 9 of 12 H7N0310LD, H7N0310LS, H7N0310LM • H7N0310LS Unit: mm 7.8 7.0 (1.5) 0.3 10.0 +– 0.5 0.2 0.1 +– 0.1 2.2 2.49 ± 0.2 0.2 0.86 +– 0.1 2.54 ± 0.5 0.3 3.0 +– 0.5 1.3 ± 0.2 2.54 ± 0.5 8.6 ± 0.3 (1.5) 1.37 ± 0.2 7.8 6.6 1.3 ± 0.2 0.4 ± 0.1 Hitachi Code JEDEC JEITA Mass (reference value) Rev.3, Aug. 2002, page 10 of 12 1.7 (1.4) 4.44 ± 0.2 10.2 ± 0.3 LDPAK (S)-(1) — — 1.3 g H7N0310LD, H7N0310LS, H7N0310LM • H7N0310LM Unit: mm 2.54 ± 0.5 7.8 7.0 (2.3) 0.3 10.0 +– 0.5 0.2 0.1 +– 0.1 2.2 2.49 ± 0.2 0.2 0.86 +– 0.1 2.54 ± 0.5 1.7 7.8 6.6 1.3 ± 0.2 0.3 5.0 +– 0.5 1.3 ± 0.2 8.6 ± 0.3 (1.5) 1.37 ± 0.2 (1.4) 4.44 ± 0.2 10.2 ± 0.3 0.4 ± 0.1 Hitachi Code JEDEC JEITA Mass (reference value) LDPAK (S)-(2) — — 1.35 g Rev.3, Aug. 2002, page 11 of 12 H7N0310LD, H7N0310LS, H7N0310LM Disclaimer 1. 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(Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://www.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-2735-9218 Fax : <852>-2730-0281 URL : http://semiconductor.hitachi.com.hk Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan. Colophon 6.0 Rev.3, Aug. 2002, page 12 of 12