SUPERTEX HV62106X

HV62106
64-Channel Gray-Shade Display Column Driver
Ordering Information
Package Options*
Device
Die in wafer form
Die in waffle pack
HV62106
HV62106XW
HV62106X
*Consult factory for availability of bumped die.
General Description
Features
Not recommended for new designs.
5V CMOS inputs
64 outputs per device
The HV62106 is a 64-channel column driver IC designed for gray
shade flat panel displays. Using Supertex’s unique HVCMOS®
technology, it is capable of providing gray shading by pulse width
modulation (PWM) conversion.
Up to 60V output voltage
Capable of 4 output pulse widths
PWM gray shade conversion
A high level on the chip select input enables the IC to load data
into a set of input data latches. This input data, in two groups of
two, are latched into the input data latches on both edges of the
Shift Clock. The data stored in these input data latches is
transferred to a set of output data latches on the rising edge of
Load Count. After the input data registers are full, a chip select
output signal is provided for enabling the next IC in the chain.
Two 2-bit data buses
28 MHz data throughput rate
Pin-programmable shift direction (DIR)
Integrated high-voltage CMOS technology
Optimized layout for COG use
A master binary counter is reset with a high level on Load Count
and is incremented on the rising edge of Count Clock. The data
stored in the output data latches is compared to the contents of
the master counter. The output of the comparator drives the high
voltage output devices. The higher the binary number in the
output data latches, the longer the pulse width will be on the
corresponding output.
DIR is a shift-direction-select input which is provided to interchange the direction of the latched data inputs. When the DIR
input is high, CS2 becomes chip select input and data is latched
into the data latches in the sequence of HVOUT1 to HVOUT64.
When the DIR input is low, CS1 becomes chip select input and
data is latched into the data latches in the sequence of HVOUT64
to HVOUT1. DIN1 and DIN2 load in data for odd number of outputs.
DIN3 and DIN4 load in data for even number of outputs.
Absolute Maximum Ratings
Supply voltage, VDD
-0.5V to +7.5V
Supply voltage, VPP
-0.5V to +70V
Logic input levels
Operating temperature range
Storage temperature range
-0.5V to VDD + 0.5V
-40°C to +85°C
-65°C to +150°C
Note:
All voltages are referenced to GND.
12-111
12
HV62106
Electrical Characteristics
(Over recommended conditions of VDD = 5V, VPP = 60V, TA = 25°C unless otherwise noted)
Low Voltage DC Characteristics
Symbol
Parameter
Min
Max
Units
Conditions
IDD
VDD supply current
10
mA
fSC = 7MHz, fCC = 3MHz
IDDQ
Quiescent VDD supply current
1
mA
All VIN = GND
IIH
High-level input current
10
µA
VIH = VDD
IIL
Low-level input current
-10
µA
VIL = GND
IOH
High-level output current
-1
mA
IOL
Low-level output current
1
mA
High Voltage DC Characteristics
Symbol
Parameter
IPPQ
Quiescent VPP supply current
VOH
High-level output
VOL
Low-level output
Min
Max
Units
100
µA
All HVOUT low or high
V
IOUT = -12mA
8
V
IOUT = 15mA
Max
Units
50
Conditions
AC Characteristics (Logic Timing)
Symbol
Parameter
Min
fSC
Shift clock frequency
7
MHz
fDIN
Data In frequency
7
MHz
fCC
Count clock frequency
3
MHz
tWA
Chip select pulse width
80
ns
tSS
Chip select set-up time
20
ns
tHS
Chip select hold time
40
ns
tDS
Data to shift clock set-up time
-10
tDH
Data to shift clock hold time
30
ns
tWLC
Load count pulse width
160
ns
tDLCC
Load count to count clock delay
70
ns
tDSL
Shift clock to load count delay
200
ns
tCSC
Shift clock cycle time
143
ns
tDLC
Load count to HVOUT delay
tWCC
Count clock pulse width
160
ns
tCCC
Count clock cycle time
333
ns
tDCC
Count clock to HVOUT delay
tWSC
Shift clock pulse width
70
ns
tWD
Data in pulse width
60
ns
30
1.5
1.5
12-112
Conditions
ns
µs
µs
CL = 15pF // RL = 10MΩ
CL = 15pF // RL = 10MΩ
HV62106
Recommended Operating Conditions
Symbol
Parameter
Min
Max
Units
VPP
High voltage supply
0
60
V
VDD
Logic supply voltage
4.5
5.5
V
VIL
Low-level input voltage
0
1
V
VIH
High-level input voltage
VDD-1
VDD
V
fSC
Shift clock frequency
7
MHz
fCC
Count clock frequency
3
MHz
TA
Operating temperature
+85
°C
-40
Conditions
Pad Definitions
Pad #
Name
2-5
18 -21
DIN1 - DIN4
I
Inputs for binary-format parallel data
(DIN2 and DIN4 are the most significant bits)
23, 33
Shift Clock
I
Latching data on both edges
24, 32
CS1
I/O
Input when DIR = 0; Output when DIR = 1
10, 22
CS2
I/O
Output when DIR = 0; Input when DIR = 1
8, 15
I/O
Load Count
Function
I
Initiates the conversion
Controls the data shift directions
26, 30
DIR
I
27, 29
GND
—
Logic ground
14, 28
HVGND
—
High voltage ground
VPP
—
High voltage supply
HVOUT1 – 64
O
High voltage outputs
VDD
—
Logic supply voltage
1, 41
42-105
25, 31
6, 17
Count Clock
(GCLK)
I
Input for incrementing the master counter for the green pixel
7, 16
Count Clock
(RCLK)
I
Input for incrementing the master counter for the red pixel
Function Table
Sequence
1
Function
2
Load data from
data bus
Load counter
3
Counting/conversion
4
Next cycle
Data-In
(D1 - D4)
H/L
CS1/
CS2
X
X
H/L
CS2/
CS1
X
Shift
Clock
L
X
X
L
X
X
X
12-113
Load
Count
L
Count Clock
(RCLK, GCLK)
H
HVOUT
L
H
L
L
H/L
H
L
HV62106
Functional Block Diagram
DIN (3, 4)
DIN (1, 2)
2
VPP
2
2
> Data
CS2
Data
2
> Latch
Latch
Comparator
Logic
HVOUT1
HVOUT3
HVOUT5
L/T
•
•
•
2
2
> Data
DIR
>
2
Data
> Latch
Latch
≈
≈
≈
Comparator
≈
Logic
HVOUT2
HVOUT4
HVOUT6
L/T
•
•
•
≈
≈
≈
Logic
L/T
HVOUT63
Logic
L/T
HVOUT64
2
> Data
2
2
Data
> Latch
Latch
Comparator
2
2
> Data
2
Data
> Latch
Comparator
>
Latch
Shift
Clock
CS1
Load
Count
Count
Clock
(GCLK, RCLK)
L/T = Level Translator
Input and Output Equivalent Circuits
VDD
VDD
VPP
Input
Data Out
GND
GND
Logic Inputs
HVOUT
HVGND
Logic Data Output
12-114
High Voltage Outputs
HV62106
Timing Diagrams
tWA
Current Loading Cycle
CS1/2
Next Loading Cycle
50%
tHS
Shift
Clock
1
2
SET
1
Data
In
SET
2
3
SET
3
SET
4
16
≈ ≈ ≈
tSS
SET
5
SET
30
1
SET
31
SET
32
2
SET
1
SET
2
tCSC
≈ ≈
16
tWSC
SET
30
tDS
SET
31
2
tDH
SET
32
SET
1
SET
2
SET
3
≈
≈
Data
In
1
≈ ≈
Shift
Clock
tWD
Shift
Clock
Next Loading Cycle
≈
≈
50%
≈
Current Loading Cycle
≈
≈
≈
≈
CS2/1
tWLC
50%
50%
tWCC
tDLCC
tDSL
Count
Clock
(RCLK,
GCLK)
≈
Load
Count
50%
50%
≈
50%
tCCC
tDLC
HVOUT
10%
tDCC
12-115
≈
≈
90%