TI DRV201A

DRV201A
www.ti.com
SLVSBN6 – JUNE 2013
VOICE COIL MOTOR DRIVER FOR CAMERA AUTO FOCUS
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FEATURES
1
•
•
•
•
•
•
Configurable for Linear or PWM Mode VCM
Current Generation
High Efficiency PWM Current Control for VCM
Advanced Ringing Compensation
Integrated 10-bit D/A Converter for VCM
Current Control
Protection
– Open and Short-Circuit Detection
– Undervoltage Lockout (UVLO)
– Thermal Shutdown
– Internal Current Limit for VCM Driver
– 4-kV ESD-HBM
I2C Interface
•
•
•
•
•
•
Improved PWM-to-Linear Mode Settling Time
vs. DRV201
Improved EMC Performance vs. DRV201
Operating Temperature Range: -40ºC to 85ºC
6-Ball WCSP Package With 0.4-mm Pitch
Max Die Size: 0.806 mm x 1.49 mm
Max Package Height: 0.3 mm
APPLICATIONS
•
•
•
•
•
•
Cell Phone Auto Focus
Digital Still Camera Auto Focus
Iris and Exposure Control
Security Cameras
Web and PC Cameras
Actuator Controls
DESCRIPTION
The DRV201A is an advanced voice coil motor driver for camera auto focus. It has an integrated D/A converter
for setting the VCM current. VCM current is controlled with a fixed frequency PWM controller or a linear mode
driver. Current generation can be selected via I2C register. The DRV201A has an integrated sense resistor for
current regulation and the current can be controlled through I2C.
When changing the current in the VCM, the lens ringing is compensated with an advanced ringing compensation
function. Ringing compensation reduces the needed time for auto focus significantly. The device also has VCM
short and open protection functions.
FUNCTIONAL BLOCK DIAGRAM
Cin
POR
10-bit
DAC
DIGITAL
GATE CONTROL
REFERENCE
PWM
OSCILLATOR
ERROR AMPLIFIER
VBAT
ISOURCE
VCM
REGISTERS
RINGING
COMPENSATION
SCL
ISINK
I2C
Rsense
SDA
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
DRV201A
SLVSBN6 – JUNE 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
TA
PACKAGE
-40°C to 85°C
(1)
(2)
(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
YMB (non-coated)
DRV201AYMBR
201A YMDS
YMB (coated)
DRV201AYMBRB
201AB YMDS
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
DEVICE INFORMATION
NanoFree YMB PACKAGE
(BOTTOM VIEW)
I
SOURCE
SCL
SDA
GND
C
B
A
NanoFree YMB PACKAGE
(TOP VIEW)
201A
YMDS
201AB
YMDS
NON-COATED
COATED
2
VBAT
I
SINK
NanoFree YMB PACKAGE
(TOP VIEW)
1
YMB package package markings:
YM
D
S
0
= YEAR / MONTH DATE CODE
= DAY OF LASER MARK
= ASSEMBLY SITE CODE
= Pin A1 (Filled Solid)
The coated package option has a backside polymer coating that is 40µm thick. The final package heights of both
the packages are the same for both options. This coating helps minimize edge chipping or die cracking during
assembly and manufacturing.
TERMINAL FUNCTIONS
TERMINAL
2
I/O
DESCRIPTION
NAME
NO.
VBAT
2A
Power
GND
1A
Ground
I_SOURCE
2B
Voice coil positive terminal
I_SINK
1B
Voice coil negative terminal
SCL
2C
I
SDA
1C
I/O
I2C serial interface clock input
I2C serial interface data input/output (open drain)
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VBAT, ISOURCE, ISOURCE pin voltage range
(1)
(2)
Voltage range at SDA, SCL
VALUE
UNIT
–0.3 to 5.5
V
–0.3 to 3.6
V
Continuous total power dissipation
θJA
Junction-to-ambient thermal resistance (3)
TJ
TA
Tstg
Internally limited
130
°C/W
Operating junction temperature
-40 to 125
°C
Operating ambient temperature
-40 to 85
°C
Storage temperature
-55 to 150
°C
ESD rating
(1)
(2)
(3)
(HBM) Human body model
±4000
(CDM) Charged device model
±500
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
This thermal data is measured with high-K board (4-layer board).
ELECTRICAL CHARACTERISTICS
Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient
temperature range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.5
3.7
4.8
UNIT
INPUT VOLTAGE
VBAT
Input supply voltage
VUVLO
Undervoltage lockout threshold
VHYS
Undervoltage lockout hysteresis
VBAT rising
VBAT falling
2.2
2
50
V
V
100
250
mV
INPUT CURRENT
ISHUTDOWN
Input supply current shutdown,
includes switch leakage currents
MAX: VBAT = 4.4 V
0.15
1
µA
ISTANDBY
Input supply current standby, includes
switch leakage currents
MAX: VBAT = 4.4 V
120
200
µA
STARTUP, MODE TRANSITIONS, AND SHUTDOWN
t1
Shutdown to standby
100
µs
t2
Standby to active
100
µs
t3
Active to standby
t4
Shutdown time
Active or standby to shutdown
0.5
100
µs
1
ms
VCM DRIVER STAGE
Resolution
IRES
10
Relative accuracy
Differential nonlinearity
10
-1
1
Zero code error
Offset error
0
At code 32
LSB
mA
3
mA
% of
FSR
Gain error
±3
Gain error drift
0.3
0.4
%/°C
Offset error drift
0.3
0.5
%/°C
IMAX
Maximum output current
ILIMIT
Average VCM current limit
(1)
bits
-10
102.3
See
(1)
110
160
mA
240
mA
During short circuit condition driver current limit comparator will trip and short is detected and driver goes into STANDBY and short flag
is set high in the status register.
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ELECTRICAL CHARACTERISTICS (continued)
Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient
temperature range of 25°C) (unless otherwise noted)
PARAMETER
IDETCODE
Minimum VCM code for OPEN and
SHORT detection
fSW
Switching frequency
VDRP
Internal dropout
LVCM
VCM inductance
RVCM
VCM resistance
TEST CONDITIONS
See
(2)
Selectable through CONTROL register
See
MIN
TYP
MAX
256
UNIT
mA
0.5
4
(3)
MHz
0.4
V
30
150
µH
11
22
Ω
LENS MOVEMENT CONTROL
tset1
Lens settling time
±10% error band
tset2
Lens settling time
±10% error band
VCM resonance frequency
fVCM
(2)
(3)
4
VCM resonance frequency tolerance
2/fVCM
ms
1/fVCM
ms
50
150
When 1/fVCM compensation is used
-10
10
When 2/fVCM compensation is used
-30
30
Hz
%
When testing VCM open or short this is the recommended minimum VCM code (in dec) to be used.
This is the voltage that is needed for the feedback resistor and high side driver. It should be noted that the maximum VCM resistance is
limited by this voltage and supply voltage. E.g. 3-V supply maximum VCM resistance is: RVCM = (VBAT – VDRP)/IVCM = (3 V - 0.4
V)/102.3 mA = 25.4 Ω.
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ELECTRICAL CHARACTERISTICS (continued)
Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient
temperature range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
V = 1.8 V, SCL
-4.25
4.25
V = 1.8 V, SDA
-1
1
UNIT
LOGIC I/Os (SDA AND SCL)
IIN
Input leakage current
RPullUp
I2C pull-up resistors
VIH
Input high level
VIL
Input low level
tTIMEOUT
SCL timeout for shutdown detection
RPD
Pull down resistor at SCL line
SDA and SCL pins
See
(4)
See
(5)
4.7
fSCL
kΩ
1.17
3.6
0
0.63
0.5
1
500
2
I C clock frequency
µA
V
V
ms
kΩ
400
kHz
INTERNAL OSCILLATOR
fOSC
Internal oscillator
20°C ≤ TA ≤ 70°C
-3
3
%
Frequency accuracy
-40°C ≤ TA ≤ 85°C
-5
5
%
THERMAL SHUTDOWN
TTRIP
(4)
(5)
Thermal shutdown trip point
140
°C
During shutdown to standby transition VIH low limit is 1.28 V.
During shutdown to standby transition VIL high limit is 0.51 V.
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PARAMETER MEASUREMENT INFORMATION
DRV201A
VBAT ISOURCE
VCM
Vin
Cin
SCL
ISINK
SDA
GND
To /From a
controller
List of components:
• Cin - Panasonic ECJ0EB1A105M
• VCM - Mitsumi VCM KAF-V85S60
• Actuator size: 8.5 x 8.5 x 3.4 (mm)
• Lens in the VCM: M6 (Pitch: 0.35)
• Weight: 75 mg
• TTL: 4.2 mm
• FB: 1.1 mm
6
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TYPICAL CHARACTERISTICS
Figure 1. Lens Positions With and Without Ringing
Compensation With 100-µm Step on the Lens Position
Figure 2. Lens Positions With and Without Ringing
Compensation With 100-µm Step on the Lens Position,
Zoomed In
Figure 3. Lens Positions With and Without Ringing
Compensation With 30-µm Step on the Lens Position
Figure 4. Lens Positions With and Without Ringing
Compensation With 30-µm Step on the Lens Position,
Zoomed In
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FUNCTIONAL DESCRIPTION
The DRV201A is intended for high performance autofocus in camera modules. It is used to control the current in
the voice coil motor (VCM). The current in the VCM generates a magnetic field which forces the lens stack
connected to a spring to move. The VCM current and thus the lens position can be controlled via the I2C
interface and an auto focus function can be implemented.
The DRV201A offers a higher level of performance than the DRV201 in two areas. First, the transition between
PWM and linear modes is free of any resonance. This allows faster image capture after achieving focus in the
PWM mode. The other performance enhancement is in the area of EMC performance. When operating in PWM
mode, transitions were significantly slowed down resulting in lower conducted and radiated noise versus the
DRV201.
The device connects to a video processor or image sensor through a standard I2C interface which supports up to
400-kbit/s data rate. The digital interface supports IO levels from 1.8 V to 3.3 V. All pins have 4-kV HBM ESD
rating.
When SCL is low for at least 0.5 ms, the device enters SHUTDOWN mode. If SCL goes from low to high the
driver enters STANDBY mode in less than 100 μs and default register values are set as shown in Figure 5.
ACTIVE mode is entered whenever the VCM_CURRENT register is set to something else than zero.
Vbat
t1
ISC/SCL
DAC
mode
t2
SHUTDOWN
=0
0
=0
STANDBY
t4
t3
ACTIVE
STANDBY
SHUTDOWN
Figure 5. Power Up and Down Sequence
VCM current can be controlled via an I2C interface and VCM_CURRENT registers. Lens stack is connected to a
spring which causes a dampened ringing in the lens position when current is changed. This mechanical ringing is
compensated internally by generating an optimized ramp whenever the current value in the VCM_CURRENT
register is changed. This enables a fast autofocus algorithm and pleasant user experience.
Current in the VCM can be generated with a linear or PWM control. In linear mode the high side PMOS is
configured as a current source and current is set by the VCM_CURRENT control register. In PWM control the
VCM is driven with a half bridge driver. With PWM control the VCM current is increased by connecting the VCM
between VBAT and GND through the high side PMOS and then released to a ‘freewheeling’ mode through the
sense resistor and low side NMOS. PWM mode switching frequency can be selected from 0.5 MHz up to 4 MHz
through a CONTROL register. PWM or linear mode can be selected with the PWM/LIN bit in the MODE register.
8
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MODES OF OPERATION
SHUTDOWN If the driver detects SCL has a DC level below 0.63 V for duration of at least 0.5 ms, the driver will
enter shutdown mode. This is the lowest power mode of operation. The driver will remain in shutdown for
as long as SCL pin remain low.
STANDBY If SCL goes from low to high the driver enters STANDBY mode and sets the default register values.
In this mode registers can be written to through the I2C interface. Device will be in STANDBY mode when
VCM_CURRENT register is set to zero. From ACTIVE mode the device will enter STANDBY if the
SW_RST bit of the CONTROL register is set. In this case all registers will be reset to default values.
STANDBY mode is entered from ACTIVE mode if any of the following faults occur: Over
temperature protection fault (OTPF), VCM short (VCMS), or VCM open (VCMO). When
STANDBY mode is entered due to a fault condition current register is cleared.
ACTIVE The device is in ACTIVE mode whenever the VCM_CURRENT control is set to something else than
zero through the I2C interface. In ACTIVE mode VCM driver output stage is enabled all the time resulting
in higher power consumption. The device remains in active mode until the SW_RST bit in the CONTROL
register is set, SCL is pulled low for duration of 0.5 ms, VCM_CURRENT control is set to zero, or any of
the following faults occur: Over temperature protection fault (OTPF), VCM short (VCMS), or VCM open
(VCMO). If active mode is entered after fault the status register is automatically cleared.
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VCM DRIVER OUTPUT STAGE OPERATION
Current in the VCM can be controlled with a linear or PWM mode output stage. Output stage is enabled in
ACTIVE mode which can be controlled through VCM_CURRENT control register and the output stage mode is
selected from MODE register bit PWM/LIN.
In linear mode the output PMOS is configured to a high side current source and current can be controlled from a
VCM_CURRENT registers.
In PWM control the VCM is driven with a half bridge driver. With PWM control the VCM current is increased by
connecting the VCM between VBAT and GND through the high side PMOS and then released to a ‘freewheeling’
mode through the sense resistor and low side NMOS. Current in the VCM is sensed with a 1-Ω sense resistor
which is connected into an error amplifier input where the other input is controlled by the 10-bit DAC output.
PWM mode switching frequency can be selected from 0.5 MHz up to 4 MHz through a CONTROL register. PWM
or linear mode can be selected with the PWM/LIN bit in the MODE register.
RINGING COMPENSATION
VCM current can be controlled via an I2C interface and VCM_CURRENT registers. Lens stack is connected to a
spring which causes a dampened ringing in the lens position when current is changed. This mechanical ringing is
compensated internally by generating an optimized ramp whenever the current value in the VCM_CURRENT
register is changed. This enables a fast auto focus algorithm and pleasant user experience.
Ringing compensation is dependent on the VCM resonance frequency and this can be controlled via
VCM_FREQ register (07h) from 50 Hz up 150 Hz. Table 1 shows the VCM_FREQ register setting for each
resonance frequency in 1-Hz steps. If more accurate resonance frequency is available, the control value can be
calculated with Equation 1.
Ringing compensation is designed in a way that it can tolerate ±30% frequency variation in the VCM resonance
frequency when 2/fVCM compensation is used and ±10% variation with 1/fVCM so only statistical data from the
VCM is needed in production.
10
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Table 1. VCM Resonance Frequency Control Register (07h) Table
VCM
Resonance
Frequency
[Hz]
VCM_FREQ[7:0] (07h)
DEC
BIN
VCM
Resonance
Frequency
[Hz]
VCM_FREQ[7:0] (07h)
DEC
BIN
VCM
Resonance
Frequency
[Hz]
VCM_FREQ[7:0] (07h)
DEC
BIN
50
0
0
84
154
10011010
118
220
11011100
51
7
111
85
157
10011101
119
222
11011110
52
14
1110
86
160
10100000
120
223
11011111
53
21
10101
87
162
10100010
121
224
11100000
54
27
11011
88
165
10100101
122
226
11100010
55
34
100010
89
167
10100111
123
227
11100011
56
40
101000
90
170
10101010
124
228
11100100
57
46
101110
91
172
10101100
125
229
11100101
58
52
110100
92
174
10101110
126
231
11100111
59
58
111010
93
177
10110001
127
232
11101000
60
63
111111
94
179
10110011
128
233
11101001
61
68
1000100
95
181
10110101
129
234
11101010
62
73
1001001
96
183
10110111
130
235
11101011
63
78
1001110
97
185
10111001
131
236
11101100
64
83
1010011
98
187
10111011
132
238
11101110
65
88
1011000
99
189
10111101
133
239
11101111
66
92
1011100
100
191
10111111
134
240
11110000
67
96
1100000
101
193
11000001
135
241
11110001
68
101
1100101
102
195
11000011
136
242
11110010
69
105
1101001
103
197
11000101
137
243
11110011
70
109
1101101
104
198
11000110
138
244
11110100
71
113
1110001
105
200
11001000
139
245
11110101
72
116
1110100
106
202
11001010
140
246
11110110
73
120
1111000
107
204
11001100
141
247
11110111
74
124
1111100
108
205
11001101
142
248
11111000
75
127
1111111
109
207
11001111
143
249
11111001
76
130
10000010
110
208
11010000
144
250
11111010
77
134
10000110
111
210
11010010
145
251
11111011
78
137
10001001
112
212
11010100
146
251
11111011
79
140
10001100
113
213
11010101
147
252
11111100
80
143
10001111
114
215
11010111
148
253
11111101
81
146
10010010
115
216
11011000
149
254
11111110
82
149
10010101
116
217
11011001
150
255
11111111
83
152
10011000
117
219
11011011
-
-
-
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User Example 1
In Figure 6, lens settling time and settling window shows how lens control is defined. Below is an example case
how the lens is controlled and what settling time is achieved:
Measured VCM resonance frequency = 100 Hz
• According to Table 1, VCM_FREQ[7:0] = ‘10111111’ (reg 0x07h)
VCM resonance frequency, fVCM, variation is within ±10% (min 90 Hz … max 110 Hz)
• 1/fVCM ringing compensation is used : RING_MODE = ‘1’ (reg 0x06h)
Stepping the lens by 50 µm
• The lens is settled into a ±5-µm window within 10 ms (1/fVCM)
User Example 2
If the case is otherwise exactly the same, but VCM resonance frequency cannot be guaranteed to stay at more
than ±30% variation, slower ringing compensation should be used:
Measured VCM resonance frequency = 100 Hz
• According to Table 1, VCM_FREQ[7:0] = ‘10111111’ (reg 0x07h)
VCM resonance frequency, fVCM, variation is within ±30% (min 70 Hz … max 130 Hz)
• 2/fVCM ringing compensation is used : RING_MODE = ‘0’ (reg 0x06h)
Stepping the lens by 50 µm
• The lens is settled into a ±5-µm window within 20 ms (2/fVCM)
±10% step
size window
Lens position
step size
settling time
Time
Figure 6. Lens Settling Time and Settling Window
12
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I2C BUS OPERATION
The I2C bus is a communications link between a controller and a series of slave terminals. The link is established
using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is
sourced from the controller in all cases where the serial data line is bi-directional for data communication
between the controller and the slave terminals. Each device has an open drain output to transmit data on the
serial data line. An external pull-up resistor must be placed on the serial data line to pull the drain output high
during data transmission.
The DRV201A hosts a slave I2C interface that supports data rates up to 400 kbit/s and auto-increment
addressing and is compliant to I2C standard 3.0.
DRV201A supports four different read and two different write operations; single read from a defined location,
single read from a current location, sequential read starting from a defined location, sequential read from current
location, single write to a defined location, sequential write starting from a defined location. All different read and
write operations are described below.
Single Write to a Defined Location
Figure 7 shows the format of a single write to a defined register. First, the master issues a start condition
followed by a seven-bit I2C address. Next, the master writes a zero to conduct a write operation. Upon receiving
an acknowledge from the slave, the master writes the eight-bit register number across the bus. Following a
second acknowledge, DRV201A sets the I2C register to a defined value and the master writes the eight-bit data
value across the bus. Upon receiving a third acknowledge, DRV201A auto increments the internal I2C register
number by one and the master issues a stop condition. This action concludes the register write.
ACK
M+1
DATA
STOP
REGISTER NUMBER
M
REGISTER NUMBER M
ACK
DRV201A ADDRESS 0
0 0 0 1 1 1 0
ACK
START
CURRENT REGISTER NUMBER K
SINGLE WRITE TO A DEFINED LOCATION
Figure 7. Single Write
Single Read from a Defined Location and Current Location
Figure 8 shows the format of a single read from a defined location. First, the master issues a start condition
followed by a seven-bit I2C address. Next, the master writes a zero to conduct a write operation. Upon receiving
an acknowledge from the slave, the master writes the eight-bit register number across the bus. Following a
second acknowledge, DRV201A sets the internal I2C register number to a defined value. Then the master issues
a repeat start condition and a seven-bit I2C address followed by a one to conduct a read operation. Upon
receiving a third acknowledge, the master releases the bus to the DRV201A. The DRV201A then writes the
eight-bit data value from the register across the bus. The master acknowledges receiving this byte and issues a
stop condition. This action concludes the register read.
1
DATA
M+1
ACK
STOP
DRV201A ADDRESS
0 0 0 1 1 1 0
ACK
REGISTER NUMBER
M
ACK
0
REGISTER NUMBER M
START
DRV201A ADDRESS
0 0 0 1 1 1 0
ACK
START
CURRENT REGISTER NUMBER K
Figure 8. Single Read from a Defined Location
Figure 9 shows the single read from the current location. If the read command is issued without defining the
register number first, DRV201A writes out the data from the current register from the device memory.
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DRV201A ADDRESS 1
0 0 0 1 1 1 0
ACK
STOP
DATA
K+2
ACK
START
REGISTER NUMBER K+1
ACK
STOP
DRV201A ADDRESS 1
0 0 0 1 1 1 0
ACK
START
CURRENT REGISTER NUMBER K
DATA
Figure 9. Single Read from the Current Location
Sequential Read and Write
Sequential read and write allows simple and fast access to DRV201A registers. Figure 10 shows sequential read
from a defined location. If the master doesn’t issue a stop condition after giving ACK, DRV201A auto increments
the register number and writes the data from the next register.
REGISTER NUMBER M+L-1
DATA
M+L
ACK
STOP
DATA
K+2
ACK
REGISTER NUMBER M+1
ACK
DRV201A ADDRESS 1
0 0 0 1 1 1 0
ACK
REGISTER NUMBER
M
ACK
REGISTER NUMBER M
START
DRV201A ADDRESS 0
0 0 0 1 1 1 0
ACK
START
CURRENT REGISTER NUMBER K
DATA
L bytes of DATA
Figure 10. Sequential Read from a Defined Location
Figure 11 shows the sequential write. If the master doesn’t issue a stop condition after giving ACK, DRV201A
auto increments it’s register by one and the master can write to the next register.
DATA
DATA
REGISTER NUMBER M+L-1
M+L
ACK
STOP
REGISTER NUMBER
M
M+2
ACK
0
REGISTER NUMBER M+1
ACK
0 0 0 1 1 1 0
REGISTER NUMBER M
ACK
DRV201A ADDRESS
ACK
START
CURRENT REGISTER NUMBER K
DATA
L bytes of DATA
Figure 11. Sequential Write
If read is started without writing the register value first, DRV201A writes out data from the current location. If the
master doesn’t issue a stop condition after giving ACK, DRV201A auto increments the I2C register and writes out
the data. This continues until the master issues a stop condition. This is shown in Figure 12.
DATA
REGISTER NUMBER K+L-1
DATA
K+L
ACK
STOP
DATA
K+2
ACK
1
REGISTER NUMBER K+1
ACK
DRV201A ADDRESS
0 0 0 1 1 1 0
ACK
START
CURRENT REGISTER NUMBER K
L bytes of DATA
Figure 12. Sequential Read Starting from a Current Location
I2C Device Address, Start and Stop Condition
Data transmission is initiated with a start bit from the controller as shown in Figure 13. The start condition is
recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon
reception of a start bit, the device will receive serial data on the SDA input and check for valid address and
control information. SDA data is latched by DRV201A on the rising edge of the SCL line. If the appropriate device
address bits are set for the device, DRV201A issues the ACK by pulling the SDA line low on the next falling edge
after 8th bit is latched. SDA is kept low until the next falling edge of the SCL line.
14
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Data transmission is completed by either the reception of a stop condition or the reception of the data word sent
to the device. A stop condition is recognized as a low to high transition of the SDA input during the high portion
of the SCL signal. All other transitions of the SDA line must occur during the low portion of the SCL signal. An
acknowledge is issued after the reception of valid address, sub-address and data words. Reference Figure 14.
...
SDA
SCL
1
2
3
4
5
START CONDITION
6
7
8
...
9
STOP CONDITION
ACKNOWLEDGE
2
Figure 13. I C Start/Stop/Acknowledge Protocol
tLOW
tr
tH(STA)
tf
SCL
tH(STA)
tH(DAT)
tHIGH
tS(DAT)
tS(STO)
tS(STA)
SDA
t(BUF)
P
S
S
P
Figure 14. I2C Data Transmission Protocol
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DATA TRANSMISSION TIMING
VBAT = 3.6 V ±5%, TA = 25ºC, CL = 100 pF (unless otherwise noted)
PARAMETER
f(SCL)
TEST CONDITIONS
Serial clock frequency
Bus Free Time Between Stop and Start Condition
tSP
Tolerable spike width on bus
tLOW
SCL low time
tHIGH
SCL high time
SDA → SCL setup time
tS(STA)
Start condition setup time
tS(STO)
Stop condition setup time
tH(DAT)
SDA → SCL hold time
tH(STA)
Start condition hold time
tr(SCL)
Rise time of SCL Signal
tf(SCL)
Fall time of SCL Signal
tr(SDA)
Rise time of SDA Signal
tf(SDA)
Rise time of SDA Signal
16
TYP
100
tBUF
tS(DAT)
MIN
SCL = 100 KHz
4.7
SCL = 400 KHz
1.3
SCL = 100 KHz
MAX
400
SCL = 400 KHz
4.7
SCL = 400 KHz
1.3
KHz
µs
50
SCL = 100 KHz
UNIT
ns
µs
SCL = 100 KHz
4
µs
SCL = 400 KHz
600
ns
SCL = 100 KHz
250
SCL = 400 KHz
100
ns
SCL = 100 KHz
4.7
SCL = 400 KHz
600
ns
SCL = 100 KHz
4
µs
SCL = 400 KHz
600
SCL = 100 KHz
0
3.45
SCL = 400 KHz
0
0.9
SCL = 100 KHz
4
SCL = 400 KHz
600
µs
ns
µs
ns
SCL = 100 KHz
1000
SCL = 400 KHz
300
SCL = 100 KHz
300
SCL = 400 KHz
300
SCL = 100 KHz
1000
SCL = 400 KHz
300
SCL = 100 KHz
300
SCL = 400 KHz
300
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µs
ns
ns
ns
ns
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SLVSBN6 – JUNE 2013
REGISTER ADDRESS MAP
DEFAULT
VALUE
REGISTER
ADDRESS (HEX)
NAME
DESCRIPTION
1
01
not used
2
02
CONTROL
0000 0010
Control register
3
03
VCM_CURRENT_MSB
0000 0000
Voice coil motor MSB current control
4
04
VCM_CURRENT_LSB
0000 0000
Voice coil motor LSB current control
5
05
STATUS
0000 0000
Status register
6
06
MODE
0000 0000
Mode register
7
07
VCM_FREQ
1000 0011
VCM resonance frequency
CONTROL REGISTER (CONTROL)
Address – 0x02h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
not used
not used
not used
not used
not used
not used
EN_RING
RESET
READ/WRITE
R
R
R
R
R
R
R/W
R/W
RESET VALUE
0
0
0
0
0
0
1
0
FIELD NAME
BIT DEFINITION
Forced software reset (reset all registers to default values) and device goes into STANDBY. RESET
bit is automatically cleared when written high.
RESET
0 – inactive
1 – device goes to STANDBY
Enables ringing compensation.
EN_RING
0 – disabled
1 – enabled
VCM MSB CURRENT CONTROL REGISTER (VCM_CURRENT_MSB)
Address – 0x03h
DATA BIT
D7
D6
D5
D4
D3
D2
FIELD NAME
not used
not used
not used
not used
not used
not used
VCM_CURRENT[9:8]
READ/WRITE
R
R
R
R
R
R
R/W
RESET VALUE
0
0
0
0
0
0
FIELD NAME
D1
D0
0
0
BIT DEFINITION
VCM current control
00 0000 0000b – 0 mA
00 0000 0001b – 0.1 mA
00 0000 0010b – 0.2 mA
…
11 1111 1110b – 102.2 mA
VCM_CURRENT[9:8]
11 1111 1111b – 102.3 mA
NOTE
When setting the current in DRV201A both
VCM_CURRENT_MSB
and
VCM_CURRENT_LSB
registers have to be updated. DRV201A starts updates the
current after LSB register write is completed.
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VCM LSB CURRENT CONTROL REGISTER (VCM_CURRENT_LSB)
Address – 0x04h
DATA BIT
D7
D6
D5
FIELD NAME
D4
D3
D2
D1
D0
0
0
0
VCM_CURRENT[7:0]
READ/WRITE
R/W
RESET VALUE
0
0
0
0
FIELD NAME
0
BIT DEFINITION
VCM current control
00 0000 0000b – 0 mA
00 0000 0001b – 0.1 mA
00 0000 0010b – 0.2 mA
…
11 1111 1110b – 102.2 mA
VCM_CURRENT[7:0]
11 1111 1111b – 102.3 mA
NOTE
When setting the current in DRV201A both
VCM_CURRENT_MSB
and
VCM_CURRENT_LSB
registers have to be updated. DRV201A starts updates the
current after LSB register write is completed.
STATUS REGISTER (STATUS) (1)
Address – 0x05h
(1)
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
not used
not used
not used
TSD
VCMS
VCMO
UVLO
OVC
READ/WRITE
R
R/WR
R
R
R
R
R
R
RESET VALUE
0
0
0
0
0
0
0
0
Status bits are cleared when device changes it’s state from standby to active. If TSD was tripped the device goes into Standby and will
not allow the transition into Active until the device cools down and TSD is cleared.
FIELD NAME
Over current detection
UVLO
Undervoltage Lockout
VCMO
Voice coil motor open detected
VCMS
Voice coil motor short detected
TSD
18
BIT DEFINITION
OVC
Thermal shutdown detected
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MODE REGISTER (MODE)
Address – 0x06h
DATA BIT
D7
D6
D5
D4
D3
D2
PWM_FREQ[2:0]
D1
D0
PWM/LIN
RING_MOD
E
FIELD NAME
not used
not used
not used
READ/WRITE
R
R
R
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
0
0
0
0
D2
D1
D0
0
1
1
FIELD NAME
BIT DEFINITION
Ringing compensation settling time
RING_MODE
0 – 2x(1/fVCM)
1 – 1x(1/fVCM)
Driver output stage in linear or PWM mode
PWM/LIN
0 – PWM mode
1 – Linear mode
Output stage PWM switching frequency
000 – 0.5 MHz
001 – 1 MHz
010 – N/A
PWM_FREQ[2:0]
011 – 2 MHz
100 – N/A
101 – 4.8 MHz
110 – 6.0 MHz
111 – 4 MHz
VCM RESONANCE FREQUENCY REGISTER (VCM_FREQ)
Address – 0x07h
DATA BIT
D7
D6
D5
D4
FIELD NAME
READ/WRITE
RESET VALUE
D3
VCM_FREQ[7:0]
R/W
1
0
0
FIELD NAME
0
0
BIT DEFINITION
VCM mechanical ringing frequency for the ringing compensation can be selected with the below
formula. The formula gives the VCM_FREQ[7:0] register value in decimal which should be rounded to
the nearest integer.
VCM_FREQ[7:0]
VCM _ FREQ = 383 -
19200
Fres
(1)
Default VCM mechanical ringing frequency is 76.4 Hz.
VCM _ FREQ = 383 -
19200
= 131.69 Þ 132 Þ '1000 0011'
76.4
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(2)
19
DRV201A
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YMB PACKAGE DIMENSIONS
MAX
UNIT
Length
DIMENSION
MIN
TYP
1.49
mm
Width
0.806
mm
Height (1)
0.278
0.289
0.3
mm
Ball pitch
0.39
0.4
0.41
mm
4.8
6
7.2
µm
0.39
0.4
0.41
mm
Ball height
Coating thickness (2)
(1)
(2)
20
Height tolerances valid for both coated and non-coated packages.
Coating thickness only applies to DRV201AYMBRB (coated) package option.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
DRV201AYMBR
ACTIVE
PICOSTAR
YMB
6
3000
Green (RoHS
& no Sb/Br)
Call TI
Level-1-260C-UNLIM
-40 to 85
201A
DRV201AYMBRB
PREVIEW
PICOSTAR
YMB
6
3000
Green (RoHS
& no Sb/Br)
Call TI
Level-1-260C-UNLIM
-40 to 85
201AB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jun-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DRV201AYMBR
Package Package Pins
Type Drawing
SPQ
PICOST
AR
3000
YMB
6
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
8.4
Pack Materials-Page 1
0.91
B0
(mm)
K0
(mm)
P1
(mm)
1.59
0.36
4.0
W
Pin1
(mm) Quadrant
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jun-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV201AYMBR
PICOSTAR
YMB
6
3000
210.0
185.0
35.0
Pack Materials-Page 2
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