HUFA76413DK8T_F085
N-Channel Logic Level UltraFET® Power MOSFET
60V, 4.8A, 56mΩ
General Description
These N-Channel power MOSFETs are manufactured using the innovative UltraFET® process. This advanced process technology achieves the lowest possible onresistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy
in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for
use in applications where power efficiency is important,
such as switching regulators, switching convertors, motor
drivers, relay drivers, low-voltage bus switches, and power
management in portable and battery-operated products.
Applications
• Motor and Load Control
• Powertrain Management
Features
•
•
•
•
•
•
150°C Maximum Junction Temperature
UIS Capability (Single Pulse and Repetitive Pulse)
Ultra-Low On-Resistance rDS(ON) = 0.049Ω, VGS = 10V
Ultra-Low On-Resistance rDS(ON) = 0.056Ω, VGS = 5V
Qualified to AEC Q101
RoHS Compliant
D1 (8)
D1 (7)
D2 (6)
D2 (5)
SO-8
S1 (1)
G1 (2)
S2 (3)
G2 (4)
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDSS
VGS
ID
Parameter
Drain to Source Voltage
Ratings
60
Units
V
Gate to Source Voltage
±16
V
5.1
A
4.8
A
1
A
Drain Current
Continuous (TC = 25oC, VGS = 10V)
Continuous (TC = 25oC, VGS = 5V)
Continuous (TC = 125oC, VGS = 5V, RθJA = 228oC/W)
Pulsed
EAS
PD
TJ, TSTG
Single Pulse Avalanche Energy (Note 1)
Power dissipation
Figure 4
A
260
mJ
2.5
Derate above 25oC
0.02
Operating and Storage Temperature
W
W/oC
oC
-55 to 150
Thermal Characteristics
50
o
Thermal Resistance Junction to Ambient SO-8 (Note 3)
191
o
Thermal Resistance Junction to Ambient SO-8 (Note 4)
228
oC/W
RθJA
Thermal Resistance Junction to Ambient SO-8 (Note 2)
RθJA
RθJA
C/W
C/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
©2010 Fairchild Semiconductor Corporation
HUFA76413DK8T_F085 Rev. C1
1
www.fairchildsemi.com
HUFA76413DK8T_F085 N-Channel Logic Level UltraFET® Power MOSFET
October 2010
Device Marking
76413DK8
Device
HUFA76413DK8T_F085
Package
SO-8
Reel Size
330mm
Tape Width
12mm
Quantity
2500 units
Electrical Characteristics TA = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
V
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
VDS = 50V
VGS = 0V
VGS = ±16V
TA = 150oC
60
-
-
-
-
1
-
-
250
-
-
±100
nA
V
µA
On Characteristics
VGS(TH)
Gate to Source Threshold Voltage
rDS(ON)
Drain to Source On Resistance
VGS = VDS, ID = 250µA
1
-
3
-
0.041
0.049
ID = 4.8A, VGS = 5V
-
0.048
0.056
-
0.091
0.106
-
620
-
-
180
-
pF
-
30
-
pF
18
23
nC
-
10
13
nC
ID = 5.1A, VGS = 10V
ID = 4.8A, VGS = 5V
TA = 150oC
Ω
Dynamic Characteristics
CISS
Input Capacitance
CRSS
Reverse Transfer Capacitance
Qg(5)
Total Gate Charge at 5V
Qgs
Gate to Source Gate Charge
COSS
Output Capacitance
Qg(TOT)
Total Gate Charge at 10V
Qg(TH)
Threshold Gate Charge
Qgd
Gate to Drain “Miller” Charge
Switching Characteristics
VDS = 25V, VGS = 0V,
f = 1MHz
VGS = 0V to 10V
VGS = 0V to 5V
VGS = 0V to 1V
VDD = 30V
ID = 4.8A
Ig = 1.0mA
pF
-
0.6
0.8
nC
-
1.8
-
nC
-
5
-
nC
(VGS = 5V)
tON
Turn-On Time
-
-
44
ns
td(ON)
Turn-On Delay Time
-
10
-
ns
tr
Rise Time
ns
td(OFF)
Turn-Off Delay Time
tf
tOFF
-
19
-
-
45
-
ns
Fall Time
-
27
-
ns
Turn-Off Time
-
-
108
ns
V
VDD = 30V, ID = 1A
VGS = 5V, RGS = 16Ω
Drain-Source Diode Characteristics
ISD = 4.8A
-
-
1.25
ISD = 2.4A
-
-
1.0
V
Reverse Recovery Time
ISD = 4.8A, dISD/dt = 100A/µs
-
-
43
ns
Reverse Recovered Charge
ISD = 4.8A, dISD/dt = 100A/µs
-
-
55
nC
VSD
Source to Drain Diode Voltage
trr
QRR
Notes:
1: Starting TJ = 25°C, L = 20mH, IAS = 5.1A
2: RθJA is 50 oC/W when mounted on a 0.5 in2 copper pad on FR-4 at 1 second.
3: RθJA is 191 oC/W when mounted on a 0.027 in2 copper pad on FR-4 at 1000 seconds.
4: RθJA is 228 oC/W when mounted on a 0.006 in2 copper pad on FR-4 at 1000 seconds.
HUFA76413DK8T_F085 Rev. C1
2
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HUFA76413DK8T_F085 N-Channel Logic Level UltraFET® Power MOSFET
Package Marking and Ordering Information
1.2
6
-ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
VGS = 10V, RθJA=50oC/W
4
2
0.2
VGS = 5V, RθJA=228oC/W
0
0
0
25
50
75
100
125
150
25
50
TA , AMBIENT TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
75
100
125
TA, CASE TEMPERATURE (oC)
150
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
4
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
ZθJA, NORMALIZED
THERMAL IMPEDANCE
1
0.1
RθJA=50oC/W
PDM
VGS = 10V
t1
0.01
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.001
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
IDM, PEAK CURRENT (A)
300
RθJA=50oC/W
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
100
TA = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 5V
I = I25
175 - TA
150
VGS = 10V
10
2
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
HUFA76413DK8T_F085 Rev. C1
3
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HUFA76413DK8T_F085 N-Channel Logic Level UltraFET® Power MOSFET
Typical Characteristics TA = 25°C unless otherwise noted
200
15
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
100
100µs
10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10ms
1
SINGLE PULSE
TJ = MAX RATED
TA = 25oC
10
STARTING TJ = 25oC
STARTING TJ = 150oC
1
0.2
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
0.1
100
Figure 5. Forward Bias Safe Operating Area
10
40
Figure 6. Unclamped Inductive Switching
Capability
25
25
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
20
15
TJ = 150oC
10
TJ =
VGS = 5V
VGS = 10V
ID, DRAIN CURRENT (A)
ID , DRAIN CURRENT (A)
1
tAV, TIME IN AVALANCHE (ms)
TJ = -55oC
25oC
5
VGS = 3.5V
20
15
VGS = 3V
10
TA = 25oC
5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
0
1.5
2.0
2.5
3.0
3.5
4.0
0
0.5
VGS , GATE TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
1.5
2.0
Figure 8. Saturation Characteristics
100
2.0
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
1.0
VDS , DRAIN TO SOURCE VOLTAGE (V)
90
ID = 5.1A
80
70
60
ID = 1A
50
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1.5
1.0
VGS = 10V, ID =5.1A
40
0.5
2
4
6
8
10
-80
Figure 9. Drain to Source On Resistance vs Gate
Voltage and Drain Current
HUFA76413DK8T_F085 Rev. C1
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
4
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HUFA76413DK8T_F085 N-Channel Logic Level UltraFET® Power MOSFET
Typical Characteristics TA = 25°C unless otherwise noted
1.2
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.0
0.8
ID = 250µA
1.1
1.0
0.9
0.6
-80
-40
0
40
80
120
-80
160
-40
TJ, JUNCTION TEMPERATURE (oC)
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
40
80
120
160
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
2000
VGS , GATE TO SOURCE VOLTAGE (V)
10
CISS = CGS + CGD
1000
C, CAPACITANCE (pF)
0
TJ , JUNCTION TEMPERATURE (oC)
CRSS = CGD
100
COSS ≅ CDS + CGD
VDD = 30V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 4.8A
ID = 1A
2
VGS = 0V, f = 1MHz
10
0
0.1
1
10
0
60
5
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
15
20
Qg, GATE CHARGE (nC)
Figure 13. Capacitance vs Drain to Source
Voltage
Figure 14. Gate Charge Waveforms for Constant
Gate Currents
150
VGS = 5V, VDD = 30V, ID = 1A
SWITCHING TIME (ns)
td(OFF)
100
tf
50
tr
td(ON)
0
0
10
20
30
40
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
Figure 15. Switching Time vs Gate Resistance
HUFA76413DK8T_F085 Rev. C1
5
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HUFA76413DK8T_F085 N-Channel Logic Level UltraFET® Power MOSFET
Typical Characteristics TA = 25°C unless otherwise noted
VDS
BVDSS
tP
L
VDS
VARY tP TO OBTAIN
IAS
+
RG
REQUIRED PEAK IAS
VDD
VDD
-
VGS
DUT
tP
IAS
0V
0
0.01Ω
tAV
Figure 16. Unclamped Energy Test Circuit
Figure 17. Unclamped Energy Waveforms
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 18. Gate Charge Test Circuit
Figure 19. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
RL
tr
VDS
tf
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
VGS
50%
50%
PULSE WIDTH
VGS
0
Figure 20. Switching Time Test Circuit
HUFA76413DK8T_F085 Rev. C1
10%
Figure 21. Switching Time Waveforms
6
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HUFA76413DK8T_F085 N-Channel Logic Level UltraFET® Power MOSFET
Test Circuits and Waveforms
RθJA = 103.2 - 24.3
250
Rθβ, RθJA (oC/W)
(T
–T )
JM
A
P DM = ----------------------------RθJA
300
(EQ. 1)
* ln(AREA)
228 oC/W - 0.006in2
200
191 oC/W - 0.027in2
150
100
50
In using surface mount devices such as the SO-8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of PDM is complex
and influenced by many factors:
Rθβ = 46.4 - 21.7 * ln(AREA)
0
0.001
0.01
0.1
1
AREA, TOP COPPER AREA (in2) PER DIE
Figure 22. Thermal Resistance vs Mounting
Pad Area
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 22
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 22 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.
R θ JA = 103.2 – 24.3 ln ( Area )
(EQ. 2)
The dual die SO-8 package introduces an additional thermal
coupling resistance, RθB. Equation 3 describes RθB as a
function of the top copper mouting pad area.
R θ B = 46.4 – 21.7 ln ( Area )
(EQ. 3)
The thermal coupling resistance vs. copper area is also
graphically depicted in Figure 22.
HUFA76413DK8T_F085 Rev. C1
7
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HUFA76413DK8T_F085 N-Channel Logic Level UltraFET® Power MOSFET
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
rev April 2002
LDRAIN
DPLCAP
10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
RSLC2
5
51
ESLC
EVTHRES
+ 19 8
+
LGATE
GATE
1
11
+
17
EBREAK 18
-
50
RDRAIN
6
8
ESG
DBREAK
+
LDRAIN 2 5 1e-9
LGATE 1 9 1.34e-9
LSOURCE 3 7 0.59e-9
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 67.4
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
DRAIN
2
5
EVTEMP
RGATE + 18 22
9
20
21
16
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RLSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 22.5e-3
RGATE 9 20 2.2
RLDRAIN 2 5 10
RLGATE 1 9 13.4
RLSOURCE 3 7 5.9
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 15.3e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
S1A
12
S2A
13
8
14
13
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
14
+
+
6
8
EGS
19
VBAT
5
8
EDS
-
IT
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*180),2.5))}
.MODEL DBODYMOD D (IS = 8e-13 RS = 1.58e-2 TRS1 = 1e-3 TRS2 = 3e-6 XTI=3.2 CJO = 8e-10 TT = 3.2e-8 M = 0.54)
.MODEL DBREAKMOD D (RS = 1.18 TRS1 = 2e-3 TRS2 = -2.6e-5)
.MODEL DPLCAPMOD D (CJO = 5.7e-10 IS = 1e-30 N = 10 M = 0.87)
.MODEL MMEDMOD NMOS (VTO = 1.68 KP = 2 IS =1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.2)
.MODEL MSTROMOD NMOS (VTO = 2.05 KP =35 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.48 KP = 0.04 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 22 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.15e-3 TC2 = -7.5e-7)
.MODEL RDRAINMOD RES (TC1 = 8.5e-3 TC2 = 1.2e-5)
.MODEL RSLCMOD RES (TC1 = 3e-2 TC2 = 5.3e-7)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.4e-3 TC2 = -7e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.5e-3 TC2 = 2e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -5.0 VOFF= -1.0)
VON = -1.0 VOFF= -5.0)
VON = -0.2 VOFF= 0.2)
VON = 0.2 VOFF= -0.2)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
HUFA76413DK8T_F085 Rev. C1
8
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HUFA76413DK8T_F085 N-Channel Logic Level UltraFET® Power MOSFET
PSPICE Electrical Model
.SUBCKT HUFA76413DK8T 2 1 3 ;
CA 12 8 7.8e-10
CB 15 14 9.8e-10
CIN 6 8 5.8e-10
LDRAIN
DPLCAP
c.ca n12 n8 = 7.8e-10
c.cb n15 n14 = 9.8e-10
c.cin n6 n8 = 5.8e-10
10
RLDRAIN
RSLC1
51
RSLC2
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
ISCL
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
GATE
1
EVTEMP
RGATE + 18 22
9
20
21
11
DBODY
16
MWEAK
6
EBREAK
+
17
18
-
MMED
MSTRO
RLGATE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
DBREAK
50
-
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 1.34e-9
l.lsource n3 n7 = 0.59e-9
DRAIN
2
5
CIN
8
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
S1A
S2A
res.rbreak n17 n18 = 1, tc1 = 1.15e-3, tc2 = -7.5e-7
12
15
14
13
res.rdrain n50 n16 = 22.5e-3, tc1 = 8.5e-3, tc2 = 1.2e-5
13
8
res.rgate n9 n20 = 2.2
S1B
S2B
res.rldrain n2 n5 = 10
13
CB
res.rlgate n1 n9 = 13.4
CA
+ 14
+
res.rlsource n3 n7 = 5.9
6
5
res.rslc1 n5 n51= 1e-6, tc1 = 3e-2, tc2 =5.3e-7
EGS
EDS 8
8
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 15.3e-3, tc1 = 1e-3, tc2 =1e-6
res.rvtemp n18 n19 = 1, tc1 = -1.5e-3, tc2 = 2e-7
res.rvthres n22 n8 = 1, tc1 = -1.4e-3, tc2 = -7e-6
RBREAK
17
18
RVTEMP
19
IT
VBAT
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 67.4
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/180))** 2.5))
}
}
HUFA76413DK8T_F085 Rev. C1
9
www.fairchildsemi.com
HUFA76413DK8T_F085 N-Channel Logic Level UltraFET® Power MOSFET
SABER Electrical Model
REV April 2002
template HUFA76413DK8T n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 8e-13, rs = 1.58e-2, trs1 = 1e-3, trs2 = 3e-6, xti = 3.2, cjo = 8e-10, tt = 3.2e-8, m = 0.54)
dp..model dbreakmod = (rs = 1.18, trs1 = 2e-3, trs2 = -2.6e-5)
dp..model dplcapmod = (cjo = 5.7e-10, isl =10e-30, nl =10, m = 0.87)
m..model mmedmod = (type=_n, vto = 1.68, kp = 2, is =1e-30, tox=1)
m..model mstrongmod = (type=_n, vto = 2.05, kp = 35, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.48, kp = 0.04, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.0, voff = -1.0)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.0, voff = -5.0)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.2, voff = 0.2)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.2)
th
CTHERM1 th 8 8.5e-4
CTHERM2 8 7 1.8e-3
CTHERM3 7 6 5.0e-3
CTHERM4 6 5 1.3e-2
CTHERM5 5 4 4.0e-2
CTHERM6 4 3 1.5e-1
CTHERM7 3 2 7.5e-1
CTHERM8 2 tl 3
RTHERM1
CTHERM1
8
RTHERM2
RTHERM1 th 8 3.5e-2
RTHERM2 8 7 6.0e-1
RTHERM3 7 6 2
RTHERM4 6 5 8
RTHERM5 5 4 18
RTHERM6 4 3 20
RTHERM7 3 2 23
RTHERM8 2 tl 25
RTHERM3
SABER Thermal Model
RTHERM4
CTHERM2
7
CTHERM3
6
SABER thermal model HUFA76413DK8T
Copper Area = 0.493in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 =8.5e-4
ctherm.ctherm2 8 7 =1.8e-3
ctherm.ctherm3 7 6 =5.0e-3
ctherm.ctherm4 6 5 =1.3e-2
ctherm.ctherm5 5 4 =4.0e-2
ctherm.ctherm6 4 3 =1.5e-1
ctherm.ctherm7 3 2 =7.5e-1
ctherm.ctherm8 2 tl =3
CTHERM4
5
RTHERM5
CTHERM5
4
RTHERM6
CTHERM6
3
rtherm.rtherm1 th 8 =3.5e-2
rtherm.rtherm2 8 7 =6.0e-1
rtherm.rtherm3 7 6 =2
rtherm.rtherm4 6 5 =8
rtherm.rtherm5 5 4 =18
rtherm.rtherm6 4 3 =20
rtherm.rtherm7 3 2 =23
rtherm.rtherm8 2 tl =25
}
RTHERM7
CTHERM7
2
RTHERM8
CTHERM8
tl
HUFA76413DK8T_F085 Rev. C1
JUNCTION
10
CASE
www.fairchildsemi.com
HUFA76413DK8T_F085 N-Channel Logic Level UltraFET® Power MOSFET
SPICE Thermal Model
REV April 2002
HUFA76413DK8T
Copper Area = 0.493in2
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Quiet Series™
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Saving our world, 1mW/W/kW at a time™
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Rev. I48
HUFA76413DK8T_F085 Rev. C1
11
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HUFA76413DK8T_F085 N-Channel Logic Level UltraFET® Power MOSFET
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