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SEMICONDUCTOR APPLICATION NOTE
Prepared by: Garth Nash
Applications Engineering
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ABSTRACT
The fundamental design concepts for phase-locked loops
implemented with integrated circuits are outlined. The
necessary equations required to evaluate the basic loop
performance are given in conjunction with a brief design
example.
The parameters in Figure 1 are defined and will be used
throughout the text.
θi(s)
θe(s)
+
–
INTRODUCTION
H(s)
The purpose of this application note is to provide the
electronic system designer with the necessary tools to design
and evaluate Phase-Locked Loops (PLL) configured with
integrated circuits. The majority of all PLL design problems
can be approached using the Laplace Transform technique.
Therefore, a brief review of Laplace is included to establish a
common reference with the reader. Since the scope of this
article is practical in nature all theoretical derivations have
been omitted, hoping to simplify and clarify the content. A
bibliography is included for those who desire to pursue the
theoretical aspect.
θi(s)
θe(s)
θo(s)
G(s)
H(s)
Phase Input
Phase Error
Output Phase
Product of the Individual Feed
Forward Transfer Functions
Product of the Individual Feedback
Transfer Functions
Figure 1. Feedback System
Using servo theory, the following relationships can be
obtained.2
PARAMETER DEFINITION
The Laplace Transform permits the representation of the
time response f(t) of a system in the complex domain F(s).
This response is twofold in nature in that it contains both
transient and steady state solutions. Thus, all operating
conditions are considered and evaluated. The Laplace
transform is valid only for positive real time linear parameters;
thus, its use must be justified for the PLL which includes both
linear and nonlinear functions. This justification is presented
in Chapter Three of Phase Lock Techniques by Gardner.1
θi(s)
fi
1
(s)
e(s) 1 G(s) H(s) i
(1)
G(s)
o(s) (s)
1 G(s) H(s) i
(2)
These parameters relate to the functions of a PLL as shown
in Figure 2.
θe(s)
Phase Detector
fo
N
θo(s)
Filter
θo(s)/N
VCO/VCM
Programmable
Counter (÷N)
Figure 2. Phase Locked Loop
REV 0
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θo(s)
G(s)
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fo
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The phase detector produces a voltage proportional to the
phase difference between the signals θi and θo/N. This voltage
upon filtering is used as the control signal for the VCO/VCM
(VCM – Voltage Controlled Multivibrator).
Since the VCO/VCM produces a frequency proportional to
its input voltage, any time variant signal appearing on the
control signal will frequency modulate the VCO/VCM. The
output frequency is
fo = N fi
(3)
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during phase lock. The phase detector, filter, and VCO/VCM
compose the feed forward path with the feedback path
containing the programmable divider. Removal of the
programmable counter produces unity gain in the feedback
path (N = 1). As a result, the output frequency is then equal to
that of the input.
Various types and orders of loops can be constructed
depending upon the configuration of the overall loop transfer
function. Identification and examples of these loops are
contained in the following two sections.
These two terms are used somewhat indiscriminately in
published literature, and to date there has not been an
established standard. However, the most common usage will
be identified and used in this article.
The type of a system refers to the number of poles of the
loop transfer function G(s) H(s) located at the origin. Example:
G(s) H(s) 10
s(s 10)
(4)
This is a type one system since there is only one pole at the
origin.
The order of a system refers to the highest degree of the
polynomial expression
1 + G(s) H(s) = 0
Various inputs can be applied to a system. Typically, these
include step position, velocity, and acceleration. The response
of type 1, 2, and 3 systems will be examined with the various
inputs.
θe(s) represents the phase error that exists in the phase
detector between the incoming reference signal θi(s) and the
feedback θo(s)/N. In evaluating a system, θe(s) must be
examined in order to determine if the steady state and
transient characteristics are optimum and/or satisfactory. The
transient response is a function of loop stability and is covered
in the next section. The steady state evaluation can be
simplified with the use of the final value theorem associated
with Laplace. This theorem permits finding the steady state
system error θe(s) resulting from the input θi(s) without
transforming back to the time domain.3
Simply stated
Lim [θ(t)] = Lim [sθe(s)]
t→
s→o
( 10 )
Where
TYPE — ORDER
let
ERROR CONSTANTS
∆ C.E.
(5)
which is termed the Characteristic Equation (C.E.). The
roots of the characteristic equation become the closed loop
poles of the overall transfer function.
Example:
G(s) H(s) 10
s(s 10)
(6)
10
0
s(s 10)
(7)
therefore
C.E. = s(s +10) +10
C.E. = s2 + 10s + 10
(8)
(9)
( 11 )
The input signal θi(s) is characterized as follows:
Step position: θi(t) = Cp t ≥ 0
( 12 )
C
Or, in Laplace notation: i(s) sp
( 13 )
where Cp is the magnitude of the phase step in radians. This
corresponds to shifting the phase of the incoming reference
signal by Cp radians:
Step velocity: θi(t) = Cvt t ≥ 0
( 14 )
Or, in Laplace notation: i(s) Cv
( 15 )
s2
where Cv is the magnitude of the rate of change of phase in
radians per second. This corresponds to inputting a frequency
that is different than the feedback portion of the VCO
frequency. Thus, Cv is the frequency difference in radians per
second seen at the phase detector.
Step acceleration: θi(t) = Cat2 t ≥ 0
Or, in Laplace notation: i(s) then
1 G(s) H(s) 1 1
e(s) (s)
1 G(s) H(s) i
2 Ca
s3
( 16 )
( 17 )
Ca is the magnitude of the frequency rate of change in radians
per second per second. This is characterized by a time variant
frequency input.
Typical loop G(s) H(s) transfer functions for types 1, 2, and 3
are:
Type 1
G(s) H(s) K
s(s a)
( 18 )
which is a second order polynomial. Thus, for the given G(s)
H(s), we obtain a type 1 second order system.
2
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Type 2
G(s) H(s) K(s a)
s2
( 19 )
Type 3
G(s) H(s) K(s a)(s b)
s3
( 20 )
The final value of the phase error for a type 1 system with a
step phase input is found by using Equations 11 and 13.
e(s) Freescale Semiconductor, Inc...
1
K
1 s(sa)
Cp
s
(s a)Cp
(s2 as K)
( 21 )
sa
e(t ) Lim s
Cp 0
2 as K
s
s→o
illustrates how the closed loop poles (roots of the
characteristic equation) vary with loop gain. For stability, all
poles must lie in the left half of the s-plane. The relationship of
the system poles and zeroes then determine the degree of
stability. The root locus contour can be determined by using
the following guidelines.2
Rule 1 – The root locus begins at the poles of G(s) H(s)
(K = 0) and ends at the zeroes of G(s) H(s)
(K = ∞), where K is loop gain.
Rule 2 – The number of root loci branches is equal to the
number of poles or number of zeroes, whichever
is greater. The number of zeroes at infinity is the
difference between the number of finite poles and
finite zeroes of G(s) H(s).
Rule 3 – The root locus contour is bounded by asymptotes
whose angular position is given by:
( 22 )
(2n 1)
; n 0, 1, 2, ...
#P #Z
( 23 )
Where #P (#Z) is the number of poles (zeroes).
Thus, the final value of the phase error is zero when a step
position (phase) is applied.
Similarly, applying the three inputs into type 1, 2, and 3
systems and utilizing the final value theorem, the following
table can be constructed showing the respective steady state
phase errors.
Table 1. Steady State Phase Errors for Various System
Types
Type 1
Type 2
Type 3
Step Position
Zero
Zero
Zero
Step Velocity
Constant
Zero
Zero
Step
Acceleration
Continually
Increasing
Constant
Zero
A zero phase error identifies phase coherence between the
two input signals at the phase detector.
A constant phase error identifies a phase differential
between the two input signals at the phase detector. The
magnitude of this differential phase error is proportional to the
loop gain and the magnitude of the input step.
A continually increasing phase error identifies a time rate
change of phase. This is an unlocked condition for the phase
loop.
Using Table 1, the system type can be determined for
specific inputs. For instance, if it is desired for a PLL to track a
reference frequency (step velocity) with zero phase error, a
minimum of type 2 is required.
Rule 4 – The intersection of the asymptotes is positioned
at the center of gravity C.G.:
C.G. P Z
#P #Z
Where ΣP (ΣZ) denotes the summation of the
poles (zeroes).
Rule 5 – On a given section of the real axis, root loci may
be found in the section only if the #P + #Z to the
right is odd.
Rule 6 – Breakaway points from negative real axis is
given by:
dK 0
ds
( 25 )
Again, where K is the loop gain variable factored from the
characteristic equation.
Example:
The root locus for a typical loop transfer function is
found as follows:
G(s) H(s) K
s(s 4)
( 26 )
The root locus has two branches (Rule 2) which begin at
s = 0 and s = –4 and ends at the two zeroes located at infinity
(Rule 1). The asymptotes can be found according to Rule 3.
Since there are two poles and no zeroes, the equation
becomes:
STABILITY
The root locus technique of determining the position of
system poles and zeroes in the s-plane is often used to
graphically visualize the system stability. The graph or plot
( 24 )
2n 1 2
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for n 0
2
3 for n 1
2
( 27 )
3
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The position of the intersection according to the Rule 4 is:
s P Z #P #Z
( 4 0) (0)
20
( 28 )
s –2
The breakaway point, as defined by Rule 6, can be found by
first writing the characteristic equation.
The response of this type 1, second order system to a step
input, is shown in Figure 4. These curves represent the phase
response to a step position (phase) input for various damping
ratios. The output frequency response as a function of time to
a step velocity (frequency) input is also characterized by the
same set of figures.
C.E. 1 G(s) H(s) 0
K
s2 4s K 0
s(s 4)
( 29 )
Now solving for K yields
K = –s2 –4s
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ζ ( 30 )
Taking the derivative with respect to s and setting it equal to
zero, then determines the breakaway point.
θ 9 =!"% ,"('#('%&#"!&
1
dK d ( s2 4s)
ds
ds
( 31 )
dK 2s 4 0
ds
( 32 )
or
s = –2
( 33 )
is the point of departure. Using this information, the root locus
can be plotted as in Figure 3.
The second order characteristic equation, given by
Equation 29, has be normalized to a standard form2
s2 + 2ζωns + ω2n
ω8=
Figure 4. Type 1 Second Order Step Response
4ω
&+ #'"' π
The overshoot and stability as a function of the damping
ratio ξ is illustrated by the various plots. Each response is
plotted as a function of the normalized time ωnt. For a given ξ
and a lock-up time t, the ωn required to achieve the desired
results can be determined. Example:
ω8
!'% " %)'+
( 34 )
where the damping ratio ξ = COS φ (0° ≤ φ ≤ 90°) and ωn is the
natural frequency as shown in Figure 3.
Assume
φ
σ
%*+ #"!'
ξ = 0.5
error < 10%
for t > 1ms
From ξ = 0.5 curve error is less than 10% of final value for all
time greater than ωnt = 4.5. The required ωn can then be found
by:
ωnt = 4.5
&+ #'"' π
( 35 )
or
Figure 3. Type 1 Second Order Root Locus Contour
4
n 4.5 4.5 4.5krads
t
0.001
( 36 )
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ξ is typically selected between 0.5 and 1 to yield optimum
overshoot and noise performance.
Example:
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(s a)k
s2
( 37 )
This is a type 2 second order system. A zero is added to
provide stability. (Without the zero, the poles would move
along the jω axis as a function of gain and the system would at
all times be oscillatory in nature.) The root locus shown in
Figure 5 has two branches beginning at the origin with one
asymptote located at 180 degrees. The center of gravity is
s = a; however, with only one asymptote, there is no
intersection at this point. The root locus lies on a circle
centered at s = –a and continues on all portions of the
negative real axis to left of the zero. The breakaway point is
s = –2a.
Õ
-
<B:6-80
-
ω8
φ
4ω
38.
θ 9 =!"% ,"('#('%$(!+
G(s) H(s) ζ Another common loop transfer function takes the form:
σ
ω8=
Figure 6. Type 2 Second Order Step Response
these design constraints is now illustrated. It is desired for the
system to have the following specifications:
Figure 5. Type 2 Second Order Root Locus Contour
The respective phase or output frequency response of this
type 2 second order system to a step position (phase) or
velocity (frequency) input is shown in Figure 6. As illustrated in
the previous example, the required ωn can be determined by
the use of the graph when ξ and the lock-up time are given.
BANDWIDTH
Output Frequency
2.0MHz to 3.0MHz
Frequency Steps
100KHz
Phase Coherent Frequency Output
—
Lock-Up Time Between Channels
1ms
Overshoot
<20%
NOTE: These specifications characterize a system function
similar to a variable time base generator or a frequency
synthesizer
From the given specifications, the circuit parameters shown
in Figure 7 can now be determined.
The –3dB bandwidth of the PLL is given by:
3dB n1 22 2 42 44
12 ( 38 )
for a type 1 second order4 system, and by:
–3dB n1 22 2 42 44
12
( 39 )
The devices used to configure the PLL are:
Frequency-Phase Detector
MC4044/4344
Voltage Controlled Multivibrator (VCM)
MC4024/4324
Programmable Counter
MC4016/4316
The forward and feedback transfer functions are given by:
for a type 2 second order1 system.
PHASE-LOCKED LOOP DESIGN EXAMPLE
The design of a PLL typically involves determining the type
of loop required, selecting the proper bandwidth, and
establishing the desired stability. A fundamental approach to
G(s) = Kp Kf Ko
where
Kn = 1/N
H(s) = Kn
( 40 )
( 41 )
The programmable counter divide ratio Kn can be found
from Equation 3.
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Phase Detector
Kp
fi
Filter
Kf
VCM
Ko
fo
Programmable
Counter Kn
f min
f min
N min o
o
2MHz 20
100KHz
fi
fstep
( 42 )
f max
3MHz 30
N max o
100KHz
fstep
( 43 )
Kn 1 to 1
20
30
( 44 )
The operating range of the MC4024/4324 VCM must cover
2MHz to 3MHz. Selecting the VCM control capacitor
according to the rules contained on the data sheet yields
C = 100pF. The desired operating range is then centered
within the total range of the device. The input voltage versus
output frequency is shown in Figure 8.
) )/.
°
A°
A°
A°
°
Kv 4MHz 1.5MHz 2 radsV
5V 3.6V
Ko 11.2sx10
6
radsV
( 47 )
The s in the denominator converts the frequency
characteristics of the VCM to phase, i.e., phase is the integral
of frequency.
The gain constant for the MC4044/4344 phase detector is
found by5
DFHigh UFLow
2.3V 0.9V 0.111Vrad
4
2(2)
( 48 )
Since a type 2 system is required (phase coherent output)
the loop transfer function must take the form of Equation 19.
The parameters thus far determined include Kp, Ko, Kn leaving
only Kf as the variable for design. Writing the loop transfer
function and relating it to Equation 19
Kp Kp Kv K n Kf
s
K(s a)
s2
( 49 )
Thus, Kf must take the form
a
Kf s s
( 50 )
in order to provide all of the necessary poles and zeroes for the
required G(s) H(s). The circuit shown in Figure 9 yields the
desired results.
%
19>= "('#(' %$(!+ @
Figure 8. MC4324 Input Voltage versus Output
Frequency (100pF Feedback Capacitor)
K
Ko sv
%
B
Figure 9. Active Filter Design
The transfer function of the VCM is given by:
6
( 46 )
Thus
G(s)H(s) A°
Where Kv is the sensitivity in radians per second per volt.
From the curve in Figure 8, Kv is found by taking the reciprocal
of the slope.
Kv = 11.2 x 106 rad/s/V
A type 2 system is required to produce a phase coherent
output relative to the input (See Table 1). The root locus
contour is shown in Figure 5 and the system step response is
illustrated by Figure 6.
) 38 !#(')"')"'&
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Figure 7. Phase-Locked Loop Circuit Parameters
( 45 )
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Kf is expressed by
0.5 Kp Kv
R Cs 1
for largeA
Kf 2
R1Cs
R1CN
( 51 )
where A is voltage gain of the amplifier.
and
R1, R2, and C are then the variables used to establish the
overall loop characteristics.
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The MC4044/4344 provides the active circuitry required to
configure the filter Kf. An additional low current high β buffering
device or FET can be used to boost the input impedance, thus
minimizing the leakage current from the capacitor C between
sample updates. As a result, longer sample periods are
achievable.
Since the gain of the active filter circuitry in the
MC4044/4344 is not infinite, a gain correction factor Kc must
be applied to Kf in order to properly characterize the function.
Kc is found experimentally to be Kc = 0.5.
Kfc Kf Kc 0.5
R2RCs1Cs 1
n2
0.5 Kp Kv R2
R1N
( 57 )
2n
( 58 )
With the use of an active filter whose open loop gain (A) is
large (Kc = 1), Equations 57 and 58 become
Kp Kv
R1CN
n2
Kp Kv R 2
R1N
( 59 )
2n
( 60 )
The percent overshoot and settling time are now used to
determine ωn. From Figure 6, it is seen that a damping ratio ζ =
0.8 will produce a peak overshoot less than 20% and will settle
within 5% at ωnt = 4.5. The required lock-up time is 1ms.
( 52 )
n 4.5 4.5 4.5krads
t
0.001
(For large gain, Equation 51 applies.)
The PLL circuit diagram is shown in Figure 11 and its
Laplace representation in Figure 10.
( 61 )
Rewriting Equation 57
The loop transfer function is
G(s) H(s) = Kp Kfc Ko Kn
G(s)H(s) Kp(0.5)
R1C ( 53 )
R2RCs1Cs 1
Ksv
N1 0.5 Kp Kv
n2N
( 62 )
( 54 )
The characteristic equation takes the form
(0.5) (0.111) (11.2 x 106)
(4500)2 (30)
C.E. 1 G(s) H(s) 0
s2 0.5 Kp Kv R2
R1N
s
0.5 Kp Kv
R1CN
R1C = 0.00102
( 55 )
Relating Equation 55 to the standard form given by
Equation 34
s2 0.5 Kp Kv R2
R1N
s
(Maximum overshoot occurs at Nmax which is minimum loop
gain)
Let
C = 0.5µF
Then
R1 0.00102 2.04k
0.5 x 10-6
Use
R1 = 2kΩ
0.5 Kp Kv
R1CN
= s2 + 2ζωns + ωn2
( 56 )
Equating like coefficients yields
θi(s)
+
Kp = 0.111V/rad
R Cs 1
Kf 2
2R1Cs
6
Ko 11.2
s * 10 radsV
θo(s)
–
Kn 1 to 1
30
20
Figure 10. Laplace Representation of Diagram in Figure 11.
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)
)
5
13
%
%
5
:
%
5
#&
19
089=0< :-;=< 0?=0;8-6 =9 =20 Freescale Semiconductor, Inc...
#
#
#
#
#
#
#
#
Figure 11. Circuit Diagram of Type 2 Phase-Locked Loop
R1 is typically selected greater than 1kΩ.
Solving for R2 in Equation 58
2 n R1N
2
R2 Kp Kv (0.5)
C n
( 63 )
N = 20
ωn = 5.64krad/s
ζ = 0.961
N = 30
ωn = 4.61krad/s
ζ = 0.785
2(0.8)
(0.5 x 10-6)(4.5k)
5
= 711Ω
Use R2 = 680Ω
All circuit parameters have now been determined and the
PLL can be properly configured.
Since the loop gain is a function of the divide ratio Kn, the
closed loop poles will vary its position as Kn varies. The root
locus shown in Figure 12 illustrates the closed loop pole
variation.
The loop was designed for the programmable counter
N = 30. The system response for N = 20 exhibits a wider
bandwidth and larger damping factor, thus reducing both
lock-up time and percent overshoot (see Figure 14).
8
Figure 12. Root Locus Variation
NOTE: The type 2 second order loop was illustrated as a
design sample because it provides excellent performance for
both type 1 and 2 applications. Even in systems that do not
require phase coherency, a type 2 loop still offers an optimum
design.
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EXPERIMENTAL RESULTS
Since the frequency is proportional to the VCM control
voltage, the PLL frequency response can be observed with an
oscilloscope by monitoring pin 2 of the VCM. The average
frequency response as calculated by the Laplace method is
found experimentally by smoothing this voltage at pin 2 with a
simple RC filter whose time constant is long compared to the
phase detector sampling rate, but short compared to the PLL
response time. With the programmable counter set at 29 the
quiescent control voltage at pin 2 is approximately 4.37 volts.
Upon changing the counter divide ratio to 30, the control
voltage increases to 4.43 volts as shown in Figure 14. A similar
transient occurs when stepping the programmable counter
from 21 to 20. Figure 14 illustrated that the experimental
results obtained from the configured system follows the
predicted results shown in Figure 13. Linearity is maintained
for phase errors less than 2π, i.e. there is no cycle slippage at
the phase detector.
)
!&'##%" '"
)
)
!&'##%" '"
)
) ).7
7<.7
Figure 14. VCM Control Voltage (Frequency) Transient
Figure 15 is a theoretical plot of the VCM control voltage
transient as calculated by a computer program. The computer
program is written with the parameters of Equations 58 and 59
(type 2) as the input variables and is valid for all damping ratios
of ζ ≤ 1.0. The program prints or plots control voltage transient
versus time for desired settings of the programmable counter.
The lock-up time can then be readily determined as the
various parameters are varied. (If stepping from a higher
divide ratio to a lower one, the transient will be negative.)
Figures 14 and 15 also exhibit a close correlation between
experimental and analytical results.
! "('#('%$(!+ @
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Figure 13 shows the theoretical transient frequency
response of the previously designed system. The curve
N = 30 illustrates the frequency response when the
programmable counter is stepped from 29 to 30, thus
producing a change in the output frequency from 2.9MHz to
3.0MHz. An overshoot of 18% is obtained and the output
frequency is within 5kHz of the final value one millisecond after
the applied step. The curve N = 20 illustrates the output
frequency change as the programmable counter is stepped
from 21 to 20.
SUMMARY
! &'## %" '" This application note describes the basic control system
techniques required for phase-locked loop design. Criteria for
the selection of the optimum type of loop and methods for
establishing the desired performance characteristics are
presented. A design example is illustrated in a step-by-step
approach along with the comparison of the experimental and
analytical results.
&=0: 8:>=
! &'## %" '" ! ' 7<
Figure 13. Frequency-Time Response
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*THE PARAMETERS LISTED BELOW APPLY TO THE FOLLOWING PLOT
PHASE DETECTOR GAIN CONSTANT
VCM GAIN CONSTANT
FILTER INPUT RESISTOR
FILTER FEEDBACK RESISTOR
FILTER CAPACITOR
DIVIDER VALUE
REFERENCE FREQUENCY
OUTPUT FREQUENCY CHANGE
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P2 = 0.111
V2 = 1.12 E+7
R3 = 3900 (R1C = 2k)
R4 = 680
P1 = 0.111 VOLTS PER RADIAN
V1 =1.12 E+7 RAD PER VOLT
R1 = 3900 OHMS (R1C = 2k)
R2 = 680 OHMS
C1 = 0.5 MICROFARADS
N1-N2 = 29 – 30
F1 = 100000 CPS
F5 = 100000 CPS
C2 = 0.5
N3-N4 = 21 – 20
F2 (F6) = 100000 (100000)
PLOT OF FUNCTIONS
(NOTE: Y(T) IS ‘+’, Z(T) IS ‘*’, AND ‘’ IS COMMON)
FOR T:
FOR FCTS:
TOP = 0
LEFT = 0
BOTTOM = 0.0015
RIGHT = 0.12
INCREMENT = 0.0005
INCREMENT = 0.002
Figure 15. VCM Control Signal Transient
10
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Bibliography
1. Topic: Type Two System Analysis
Gardner, F. M., Phase Lock Techniques, Wiley, New York, Second Edition, 1967
2. Topic: Root Locus Techniques
Kuo, B. C., Automatic Control Systems, Prentice-Hall, Inc., New Jersey, 1962
3. Topic: Laplace Techniques
McCollum, P. and Brown, B., Laplace Transform Tables and Theorems, Holt, New York, 1965
4. Topic: Type One System Analysis
Truxal, J. G., Automatic Feedback Control System Synthesis, McGraw-Hill, New York, 1955
Freescale Semiconductor, Inc...
5. Topic: Phase Detector Gain Constant
DeLaune, Jon, MTTL and MECL Avionics Digital Frequency Synthesizer, AN532
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