2SK1334 Silicon N Channel MOS FET REJ03G0932-0200 (Previous: ADE-208-1271) Rev.2.00 Sep 07, 2005 Application High speed power switching Features • • • • • Low on-resistance High speed switching Low drive current No secondary Breakdown Suitable for switching regulator and DC-DC converter Outline RENESAS Package code: PLZZ0004CA-A (Package name: UPAK R ) 3 D 2 1 1. Gate 2. Drain 3. Source 4. Drain G 4 S Note: Marking is “BY”. *UPAK is a trademark of Renesas Technology Corp. Rev.2.00 Sep 07, 2005 page 1 of 6 2SK1334 Absolute Maximum Ratings (Ta = 25°C) Symbol Ratings Unit Drain to source voltage Item VDSS 200 V Gate to source voltage VGSS ±20 V 1 A 2 A Drain current ID Drain peak current ID(pulse) Body to drain diode reverse drain current *1 IDR Channel dissipation Pch *2 1 A 1 W °C °C Channel temperature Tch 150 Storage temperature Tstg –55 to +150 Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1% 2. When using the alumina ceramic board (12.5 × 20 × 0.7 mm) Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Symbol V(BR)DSS Min 200 Typ — Max — Unit V Gate to source breakdown voltage Gate to source leak current V(BR)GSS IGSS ±20 — — — — ±10 V µA IG = ±100 µA, VDS = 0 VGS = ±16 V, VDS = 0 Zero gate voltage drain current Gate to source cutoff voltage IDSS VGS(off) — 2.0 — — 50 4.0 µA V VDS = 160 V, VGS = 0 ID = 1 mA, VDS = 10 V Static drain to source on state resistance RDS(on) — — 2.5 4.5 3.8 7.0 Ω Ω ID = 0.5 A, VGS = 10 V * 3 ID = 2 A, VGS = 10 V * Forward transfer admittance Input capacitance |yfs| Ciss 0.4 — 0.6 80 — — S pF Output capacitance Reverse transfer capacitance Coss Crss — — 40 7 — — pF pF ID = 0.5 A, VDS = 10 V * VDS = 10 V, VGS = 0, f = 1 MHz Turn-on delay time Rise time td(on) tr — — 5 8 — — ns ns Turn-off delay time Fall time td(off) tf — — 10 7 — — ns ns Body to drain diode forward voltage Body to drain diode reverse recovery time VDF trr — — 1.0 75 — — V ns Notes: 3. Pulse test Rev.2.00 Sep 07, 2005 page 2 of 6 Test conditions ID = 10 mA, VGS = 0 3 3 ID = 0.5 A, VGS = 10 V, RL = 60 Ω IF = 1 A, VGS = 0 IF = 1 A, VGS = 0, diF/dt = 50 A/µs 2SK1334 Main Characteristics Maximum Safe Operation Area Power vs. Temperature Derating 5 Test Condition: When using alumina ceramic board (12.5 × 20 × 0.7 mm) a are ) s i th (on 10 in R DS n µs tio d by 10 a r e ite 0 p P 1 m µ O li W m s is = s D 10 C O m pe s (1 ra tio Sh n ot (T ) C = 25 °C ) Ta = 25°C 2 Drain Current ID (A) Channel Dissipation Pch (W) 1.2 0.8 0.4 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0 50 100 1 150 2.0 2.0 10 V Pulse Test Drain Current ID (A) 8V 7V 1.6 6V 1.2 0.8 5V 0.4 VGS = 3 V 1.6 VDS = 10 V Pulse Test 1.2 0.8 0.4 75°C TC = 25°C –25°C 4V 8 12 16 20 2 0 6 4 10 8 Drain to Source Voltage VDS (V) Gate to Source Voltage VGS (V) Drain to Source Saturation Voltage vs. Gate to Source Voltage Static Drain to Source on State Resistance vs. Drain Current Pulse Test 16 12 ID = 2 A 8 4 1A 0.5 A 4 8 12 16 Drain to Source Voltage VGS (V) Rev.2.00 Sep 07, 2005 page 3 of 6 20 Static Drain to Source on State Resistance RDS (on) (Ω) Drain to Source Saturation Voltage VDS (on) (V) 4 20 0 300 1,000 Typical Transfer Characteristics Typical Output Characteristics 0 100 30 Drain to Source Voltage VDS (V) Ambient Temperature Ta (°C) Drain Current ID (A) 10 3 50 Pulse Test 20 10 VGS = 10 V 5 15 V 2 1 0.5 0.05 0.1 0.2 0.5 1 2 Drain Current ID (A) 5 Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance yfs (S) Static Drain to Source on State Resistance vs. Temperature 10 ID = 2 A VGS = 10 V Pulse Test 8 1A 6 0.5 A 4 2 0 –40 0 80 40 120 160 5 VDS = 10 V Pulse Test 2 –25°C TC = 25°C 75°C 1 0.5 0.2 0.1 0.05 0.1 2 Drain Current ID (A) Reverse Recovery Time vs. Reverse Drain Current Typical Capacitance vs. Drain to Source Voltage 5 1,000 500 VGS = 0 f = 1 MHz di/dt = 50 A/µs, Ta = 25°C VGS = 0 200 100 50 20 100 Ciss Coss 10 10 Crss 5 0.05 1 0.1 1 0.5 0.2 2 5 10 0 300 200 100 16 12 VGS ID = 1 A VDS 8 VDD = 150 V 100 V 50 V 4 0 0 2 4 6 8 Gate Charge Qg (nc) Rev.2.00 Sep 07, 2005 page 4 of 6 50 10 100 VGS = 10 V, VDD = 30 V PW = 2 µs, duty < 1% 50 Switching Time t (ns) 20 VDD = 150 V 100 V 400 50 V 40 Switching Characteristics Gate to Source Voltage VGS (V) Dynamic Input Characteristics 500 30 20 Drain to Source Voltage VDS (V) Reverse Drain Current IDR (A) Drain to Source Voltage VDS (V) 1 0.5 0.2 Case Temperature TC (°C) Capacitance C (pF) Reverse Recovery Time t rr (ns) Static Drain to Source on State Resistance RDS (on) (Ω) 2SK1334 20 tf td (off) 10 tr 5 td (on) 2 1 0.05 0.1 0.2 0.5 1 2 Drain Current ID (A) 5 2SK1334 Reverse Drain Current vs. Source to Drain Voltage Reverse Drain Current IDR (A) 2.0 Pulse Test 1.6 1.2 0.8 10 V, 15 V 0.4 VGS = 0, –5 V 0 0 0.4 0.8 1.2 1.6 2.0 Source to Drain Voltage VSD (V) Rev.2.00 Sep 07, 2005 page 5 of 6 2SK1334 Package Dimensions RENESAS Code Package Name MASS[Typ.] PLZZ0004CA-A UPAK / UPAKV 0.050g 1.5 1.5 3.0 1.5 ± 0.1 0.44 Max 2.5 ± 0.1 4.25 Max (1.5) 0.44 Max (0.2) 0.53 Max 0.48 Max 0.8 Min φ1 0.4 4.5 ± 0.1 1.8 Max Unit: mm (2.5) SC-62 (0.4) JEITA Package Code Ordering Information Part Name 2SK1334BYTL-E Quantity 1000 pcs Shipping Container φ178 mm Real, 12 mm Emboss taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.2.00 Sep 07, 2005 page 6 of 6 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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