IRFPS40N60K

PD - 94384A
SMPS MOSFET
IRFPS40N60K
Applications
l Hard Switching Primary or PFC Switch
l Switch Mode Power Supply (SMPS)
l Uninterruptible Power Supply
l High Speed Power Switching
l Motor Drive
HEXFET® Power MOSFET
VDSS
RDS(on) typ.
ID
0.110 Ω
40A
600V
Benefits
Low Gate Charge Qg results in Simple
Drive Requirement
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
l Enhanced Body Diode dv/dt Capability
Absolute Maximum Ratings
l
SUPER TO-247AC
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current 
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt ƒ
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case )
Max.
Units
40
24
160
570
4.5
± 30
7.5
-55 to + 150
A
W
W/°C
V
V/ns
300
°C
Avalanche Characteristics
Symbol
EAS
IAR
EAR
Parameter
Single Pulse Avalanche Energy‚
Avalanche Current
Repetitive Avalanche Energy
Typ.
Max.
Units
–––
–––
–––
600
40
57
mJ
A
mJ
Typ.
Max.
Units
–––
0.24
–––
0.22
–––
40
°C/W
Thermal Resistance
Symbol
RθJC
RθCS
RθJA
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Parameter
Junction-to-Case†
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient†
1
10/20/04
IRFPS40N60K
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
RDS(on)
VGS(th)
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
IDSS
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
∆V(BR)DSS/∆TJ
Min. Typ. Max. Units
Conditions
600 ––– –––
V
VGS = 0V, ID = 250µA
––– 0.63 ––– V/°C Reference to 25°C, ID = 1mA†
––– 0.110 0.130
Ω
VGS = 10V, ID = 24A „
3.0
––– 5.0
V
VDS = V GS, ID = 250µA
––– ––– 50
VDS = 600V, VGS = 0V
µA
––– ––– 250
VDS = 480V, VGS = 0V, TJ = 125°C
––– ––– 100
VGS = 30V
nA
––– ––– -100
VGS = -30V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
Min.
21
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
–––
–––
–––
47
110
97
60
7970
750
75
9440
200
260
Max. Units
Conditions
–––
S
VDS = 50V, ID = 24A
330
ID = 38A
84
nC
VDS = 480V
150
VGS = 10V, See Fig. 6 and 13 „
–––
VDD = 300V
–––
I
D = 38A
ns
–––
RG = 4.3Ω
–––
VGS = 10V,See Fig. 10 „
–––
VGS = 0V
–––
VDS = 25V
–––
pF
ƒ = 1.0MHz, See Fig. 5
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 480V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 480V …
Diode Characteristics
Symbol
IS
VSD
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 
Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
ISM
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
––– ––– 40
MOSFET symbol
showing the
A
G
––– ––– 160
integral reverse
S
p-n junction diode.
––– ––– 1.5
V
TJ = 25°C, IS = 38A, VGS = 0V „
––– 630 950
TJ = 25°C
IF = 38A
ns
––– 730 1090
TJ = 125°C
di/dt = 100A/µs „
––– 14
20
TJ = 25°C
µC
––– 17
25
TJ = 125°C
––– 39
58
A
TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature.(See Fig. 11)
‚ Starting TJ = 25°C, L = 0.84mH, RG = 25Ω,
IAS = 38A, (See Figure 12a)
ƒ ISD ≤ 38A, di/dt ≤ 224A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C
2
„ Pulse width ≤ 300µs; duty cycle ≤ 2%.
… Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
† Rθ is measured at TJ approximately 90°C
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IRFPS40N60K
1000
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
100
10
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
1
0.1
4.5V
0.01
10
4.5V
1
20µs PULSE WIDTH
Tj = 25°C
20µs PULSE WIDTH
Tj = 150°C
0.001
0.1
0.1
1
10
100
0.1
1
VDS, Drain-to-Source Voltage (V)
10
100
VDS, Drain-to-Source Voltage (V)
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
3.5
1000
I D = 38A
3.0
T J= 150 ° C
10
TJ = 25 °C
1
0.1
V DS= 50V
20µs PULSE WIDTH
0.01
4
6
8
10
11
13
V GS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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15
2.5
(Normalized)
R DS(on) , Drain-to-Source On Resistance
I D, Drain-to-Source Current (A)
100
2.0
1.5
1.0
0.5
V GS = 10V
0.0
-60
-40
-20
0
20
40
60
TJ , Junction Temperature
80
100
120
140
( ° C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
160
IRFPS40N60K
100000
12
VGS
C
iss
C
rss
C
oss
= 0V,
f = 1 MHZ
=C +C , C
SHORTED
gs
gd
ds
=C
gd
=C +C
ds
gd
VDS = 480V
VDS = 300V
VDS = 120V
10
Ciss
VGS , Gate-to-Source Voltage (V)
C, Capacitance(pF)
10000
I D = 38A
1000
Coss
100
Crss
10
7
5
2
0
1
10
100
0
1000
50
100
150
200
250
QG, Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
1000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
I SD , Reverse Drain Current (A)
100
T J= 150 ° C
10
TJ = 25 °C
1
V GS = 0 V
0.6
0.9
1.3
V SD,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
1msec
1
10msec
Tc = 25°C
Tj = 150°C
Single Pulse
0.1
0.1
0.2
100µsec
10
1.6
1
10
100
1000
10000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFPS40N60K
VGS
D.U.T.
RG
30
I D , Drain Current (A)
RD
V DS
40
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
20
Fig 10a. Switching Time Test Circuit
10
VDS
90%
0
25
50
75
100
TC , Case Temperature
125
150
( ° C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
(Z thJC )
1
D = 0.50
0.1
Thermal Response
0.20
0.10
0.05
0.01
0.02
0.01
P DM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D =
2. Peak T
0.001
0.00001
0.0001
0.001
0.01
t1/ t 2
J = P DM x Z thJC
+TC
0.1
1
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFPS40N60K
1200
5.0
EAS , Single Pulse Avalanche Energy (mJ)
960
TOP
17A
24A
BOTTOM
38A
VGS(th) Gate threshold Voltage (V)
ID
720
480
240
4.5
4.0
ID = 250µA
3.5
3.0
2.5
2.0
0
25
50
75
100
125
150
( ° C)
Starting Tj, Junction Temperature
-75
-50
-25
0
25
50
75
100
125 150
T J , Temperature ( °C )
Fig 12a. Maximum Avalanche Energy
Vs. Drain Current
Fig 14. Threshold Voltage Vs. Temperature
15V
V(BR)DSS
DRIVER
L
VDS
D.U.T
RG
+
- VDD
IAS
20V
tp
tp
A
0.01Ω
I AS
Fig 12b. Unclamped Inductive Test Circuit
Fig 12c. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
50KΩ
12V
VGS V
.2µF
.3µF
D.U.T.
+
V
- DS
QGS
QGD
VG
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 13a. Gate Charge Test Circuit
6
Charge
Fig 13b. Basic Gate Charge Waveform
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IRFPS40N60K
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
ƒ
+
‚
-
-
„
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRFPS40N60K
SUPER TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
0.13 [.005]
16.10 [.632]
15.10 [.595]
2X R 3.00 [.118]
2.00 [.079]
0.25 [.010]
5.50 [.216]
4.50 [.178]
A
B A
13.90 [.547]
13.30 [.524]
2.15 [.084]
1.45 [.058]
1.30 [.051]
0.70 [.028]
16.10 [.633]
15.50 [.611]
4
20.80 [.818]
19.80 [.780]
4
C
1
2
3
B
14.80 [.582]
13.80 [.544]
5.45 [.215]
2X
Ø 1.60 [.063]
MAX.
4.25 [.167]
3.85 [.152]
3X
1.60 [.062]
1.45 [.058]
0.25 [.010]
B A
3X
E
E
1.30 [.051]
1.10 [.044]
2.35 [.092]
1.65 [.065]
S ECT ION E-E
NOTES :
1. DIMENS IONING AND TOLERANCING PER AS ME Y14.5M-1994.
2. DIMENS IONS ARE S HOWN IN MILLIMETERS [INCHES ]
3. CONT ROLLING DIMENS ION: MILLIMETER
4. OUTLINE CONFORMS T O JEDEC OUT LINE T O-274AA
LEAD AS S IGNMENT S
MOS FET
1 - GAT E
2 - DRAIN
3 - S OURCE
4 - DRAIN
IGBT
1 - GATE
2 - COLLECT OR
3 - EMIT T ER
4 - COLLECT OR
Super-247™ Part Marking Information
EXAMPLE: THIS IS AN IRFPS37N50A WITH
ASSEMBLY LOT CODE A8B9
INTERNATIONAL RECTIFIER
LOGO
PART NUMBER
IRFPS37N50A
A8B9
0020
ASSEMBLY LOT CODE
TOP
DATE CODE
(YYWW)
YY = YEAR
WW = WEEK
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.10/04
8
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