TBB1012 Twin Built in Biasing Circuit MOS FET IC UHF/VHF RF Amplifier REJ03G1245-0200 Rev.2.00 Aug 22, 2006 Features • • • • • • • Small SMD package CMPAK-6 built in twin BBFET; To reduce using parts cost & PC board space. Very useful for total tuner cost reduction. Suitable for World Standard Tuner RF amplifier. High gain Low noise Low output capacitance Power supply voltage: 5 V Outline RENESAS Package code: PTSP0006JA-A (Package name: CMPAK-6) 6 5 4 2 3 1 Notes: 1. Drain(1) 2. Source 3. Drain(2) 4. Gate-1(2) 5. Gate-2 6. Gate-1(1) 1. Marking is “MM“. 2. TBB1012 is individual type number of Renesas TWIN BBFET. Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate1 to source voltage Symbol VDS VG1S Gate2 to source voltage VG2S Drain current ID Channel power dissipation PchNote3 Channel temperature Tch Storage temperature Tstg Notes: 3. Value on the glass epoxy board (50mm × 40mm × 1mm). Rev.2.00 Aug 22, 2006 page 1 of 13 Ratings 6 +6 –0 +6 –0 30 250 150 –55 to +150 Unit V V V mA mW °C °C TBB1012 Electrical Characteristics • FET1 (Ta = 25°C) Item Drain to source breakdown voltage Gate1 to source breakdown voltage Gate2 to source breakdown voltage Gate1 to source cutoff current Gate2 to source cutoff current Gate1 to source cutoff voltage Gate2 to source cutoff voltage Drain current Symbol V(BR)DSS Min 6 Typ — Max — Unit V Test Conditions ID = 200 µA, VG1S = VG2S = 0 V(BR)G1SS +6 — — V IG1 = +10 µA, VG2S = VDS = 0 V(BR)G2SS +6 — — V IG2 = +10 µA, VG1S = VDS = 0 IG1SS — — +100 nA VG1S = +5 V, VG2S = VDS = 0 IG2SS — — +100 nA VG2S = +5 V, VG1S = VDS = 0 VG1S(off) 0.5 0.8 1.1 V VDS = 5 V, VG2S = 4 V, ID = 100 µA VG2S(off) 0.4 0.7 1.0 V VDS = 5 V, VG1S = 5 V, ID = 100 µA ID(op) 12 16 20 mA |yfs| 27 32 38 mS Input capacitance Ciss 1.2 1.6 2.0 pF Output capacitance Coss 0.7 1.1 1.5 pF Power gain PG 15 20.5 25 dB Noise figure NF — 1.95 2.7 dB Forward transfer admittance VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 100 kΩ VDS = 5 V, VG1 = 5 V, VG2S = 4 V, f = 1 kHz, RG = 100 kΩ VDS = 5 V, VG1 = 5 V, VG2S = 4 V, f = 1 MHz, RG = 100 kΩ VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 100 kΩ, f = 900 MHz • FET2 (Ta = 25°C) Item Drain to source breakdown voltage Gate1 to source breakdown voltage Gate2 to source breakdown voltage Gate1 to source cutoff current Gate2 to source cutoff current Gate1 to source cutoff voltage Gate2 to source cutoff voltage Drain current Symbol V(BR)DSS Min 6 Typ — Max — Unit V Test Conditions ID = 200 µA, VG1s = VG2S = 0 V(BR)G1SS +6 — — V IG1 = +10 µA, VG2S = VDS = 0 V(BR)G2SS +6 — — V IG2 = +10 µA, VG1S = VDS = 0 IG1SS — — +100 nA VG1S = +5 V, VG2S = VDS = 0 IG2SS — — +100 nA VG2S = +5 V, VG1S = VDS = 0 VG1S(off) 0.5 0.8 1.1 V VDS = 5 V, VG2S = 4 V, ID = 100 µA VG2S(off) 0.4 0.7 1.0 V VDS = 5 V, VG1S = 5 V, ID = 100 µA ID(op) 13 17 21 mA |yfs| 25 30 35 mS Input capacitance Ciss 2.3 2.7 3.1 pF Output capacitance Coss 0.9 1.3 1.7 pF Power gain PG 24 29.5 34 dB Noise figure NF — 0.95 1.6 dB Forward transfer admittance Rev.2.00 Aug 22, 2006 page 2 of 13 VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 82 kΩ VDS = 5 V, VG1 = 5 V, VG2S = 4 V, f = 1 kHz, RG = 82 kΩ VDS = 5 V, VG1 = 5 V, VG2S = 4 V, f = 1 MHz, RG = 82 kΩ VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 82 kΩ, f = 200 MHz TBB1012 DC Biasing Circuit for Operating Characteristic Items (ID(op), |yfs|, Ciss, Coss, NF, PG) • Measurement of FET1 VG2 Gate 2 RG Gate 1(1) Open Drain (1) Open VG1 ID VD A Source • Measurement of FET2 VG2 Gate 2 Open Gate1(2) VG1 I A D Drain (2) Open Source Rev.2.00 Aug 22, 2006 page 3 of 13 VD TBB1012 900 MHz Power Gain, Noise Figure Test Circuit VD VG1 VG2 C4 C6 C5 R2 C3 R1 R3 RFC Output (50 Ω) D G2 L3 Input (50 Ω) L4 G1 S L1 L2 C1 C1, C2 C3 C4 ~ C6 R1 R2 R3 C2 : : : : : : Variable Capacitor (10 pF MAX) Disk Capacitor (1000 pF) Air Capacitor (1000 pF) 100 kΩ 47 kΩ 4.7 kΩ L2: L1: 10 3 3 8 10 26 (φ 1 mm Copper wire) Unit: mm 21 L4: L3: 18 10 10 7 7 29 RFC : φ1 mm Copper wire with enamel 4 turns inside dia 6 mm Rev.2.00 Aug 22, 2006 page 4 of 13 TBB1012 200 MHz Power Gain, Noise Figure Test Circuit 1000 p 47 k Input (50 Ω) VT VG2 VT 1000 p 1000 p 1000 p FET2 47 k 47 k 1000 p L2 L1 10 p max 1000 p 1000 p 36 p RFC 1SV70 1SV70 R1 1000 p V G1 1000 p VD Unit : Resistance (Ω) Capacitance (F) R1 : 82 kΩ L1 : φ1 mm Enameled Copper Wire, Inside dia 10 mm, 2 Turns L2 : φ1 mm Enameled Copper Wire, Inside dia 10 mm, 2 Turns RFC : φ1 mm Enameled Copper Wire, Inside dia 5 mm, 2 Turns Rev.2.00 Aug 22, 2006 Output (50 Ω) page 5 of 13 TBB1012 Main Characteristics • FET1 Typical Output Characteristics Pch* (mW) Maximum Channel Power Dissipation Curve 400 ID (mA) 25 Drain Current Channel Power Dissipation 300 200 100 68 kΩ VG2S = 4 V VDS = VG1 20 82 kΩ 15 100 kΩ 120 kΩ 10 150 kΩ 5 80 RG 0 50 100 150 Ambient Temperature 0 0 200 Ta (°C) 1 2 =1 3 kΩ 4 Drain to Source Voltage 5 (V) VDS * Value on the glass epoxy board (50 mm × 40 mm × 1 mm) Forward Transfer Admittance vs. Gate1 Voltage Drain Current ID (mA) 25 VDS = 5 V VG2S = 4 V RG = 100 kΩ 20 4V 15 3V 10 2V 5 VG2S = 1 V 0 0 1 2 3 4 Gate1 Voltage VG1 5 Forward Transfer Admittance |yfs| (mS) Drain Current vs. Gate1 Voltage 50 VDS = 5 V VG2S =4 V RG = 100 kΩ f = 1 kHz 40 3V 20 10 V G2S = 0 0 (V) 2 3 4 5 (V) Input Capacitance vs. Gate2 to Source Voltage 5 Input Capacitance Ciss (pF) ID (mA) Drain Current 1 Gate1 Voltage VG1 25 20 15 10 VDS = 5 V VG1 = 5 V VG2S = 4 V 0 10 VDS = 5 V VG1 = 5 V RG = 100 kΩ f = 1 MHz 4 3 2 1 0 100 Gate Resistance Rev.2.00 2V 1V 0 Drain Current vs. Gate Resistance 5 4V 30 Aug 22, 2006 1000 RG (kΩ) page 6 of 13 0 1 2 3 Gate2 to Source Voltage VG2S 4 (V) TBB1012 Power Gain vs. Gate Resistance Noise Figure vs. Gate Resistance 5 20 Noise Figure NF (dB) Power Gain PG (dB) 25 15 10 VDS = 5 V VG1 = 5 V VG2S = 4 V f = 900 MHz 5 100 3 2 1 10 1000 1000 Gate Resistance RG (kΩ) Power Gain vs. Gate2 to Source Voltage Noise Figure vs. Gate2 to Source Voltage 25 5 20 4 15 10 VDS = 5 V VG1 = 5 V RG = 100 kΩ f = 900 MHz 5 0 3 2 VDS = 5 V VG1 = 5 V RG = 100 kΩ f = 900 MHz 1 0 1 2 3 4 Gate2 to Source Voltage VG2S (V) Gain Reduction vs. Gate2 to Source Voltage 40 VDS = 5 V VG1 = 5 V RG = 100 kΩ f = 900 MHz 35 30 25 20 15 10 5 0 100 Gate Resistance RG (kΩ) Noise Figure NF (dB) Power Gain PG (dB) 10 Gain Reduction GR (dB) 4 0 0 0 1 2 3 4 Gate2 to Source Voltage VG2S (V) Rev.2.00 VDS = 5 V VG1 = 5 V VG2S = 4 V f = 900 MHz Aug 22, 2006 page 7 of 13 1 2 3 4 Gate2 to Source Voltage VG2S (V) TBB1012 • FET2 Typical Output Characteristics Pch* (mW) Maximum Channel Power Dissipation Curve 25 ID (mA) 400 Drain Current Channel Power Dissipation 300 200 100 VG2S = 4 V VDS = VG1 56 kΩ 68 kΩ 20 82 kΩ 15 100 kΩ 120 kΩ 10 150 kΩ 5 RG = 180 kΩ 0 0 50 100 150 Ambient Temperature 200 0 1 2 3 4 Drain to Source Voltage Ta (°C) 5 (V) VDS * Value on the glass epoxy board (50 mm × 40 mm × 1 mm) Forward Transfer Admittance vs. Gate1 Voltage Drain Current ID (mA) 20 VDS = 5 V VG2S = 4 V RG = 82 kΩ 15 4V 10 2V 5 VG2S = 1 V 0 0 1 2 3 4 Gate1 Voltage VG1 5 Forward Transfer Admittance |yfs| (mS) Drain Current vs. Gate1 Voltage 50 VDS = 5 V VG2S = 4 V RG = 82 kΩ f = 1 kHz 40 4V 30 3V 20 2V 10 0 VG2S = 1 V 0 (V) 4 5 (V) 5 VDS = 5 V VG1 = 5 V VG2S = 4 V 25 20 15 10 5 10 Input Capacitance Ciss (pF) ID (mA) 3 Input Capacitance vs. Gate2 to Source Voltage 30 Drain Current 2 Gate1 Voltage VG1 Drain Current vs. Gate Resistance 4 3 2 VDS = 5 V VG1 = 5 V RG =82 kΩ f = 1 MHz 1 0 100 Gate Resistance Rev.2.00 1 Aug 22, 2006 1000 RG (kΩ) page 8 of 13 0 1 2 3 Gate2 to Source Voltage VG2S 4 (V) TBB1012 Power Gain vs. Gate Resistance Noise Figure vs. Gate Resistance 3 30 Noise Figure NF (dB) Power Gain PG (dB) 35 25 20 VDS = 5 V VG1 = 5 V VG2S = 4 V f = 200 MHz 15 10 100 10 100 1000 Gate Resistance RG (kΩ) Gate Resistance RG (kΩ) Power Gain vs. Gate2 to Source Voltage Noise Figure vs. Gate2 to Source Voltage 5 30 Noise Figure NF (dB) Power Gain PG (dB) 1 1000 35 25 20 15 VDS = 5 V VG1 = 5 V RG = 82 kΩ f = 200 MHz 10 VDS =5 V VG1 =5 V RG =82 kΩ f = 200 MHz 4 3 2 1 0 5 1 2 3 4 Gate2 to Source Voltage VG2S (V) Gain Reduction vs. Gate2 to Source Voltage 50 VDS = 5 V VG1 = 5 V RG = 82 kΩ f = 200 MHz 45 Gain Reduction GR (dB) 2 0 10 40 35 30 25 20 15 10 5 0 0 1 2 3 4 Gate2 to Source Voltage VG2S (V) Rev.2.00 VDS = 5 V VG1 = 5 V VG2S = 4 V f = 200 MHz Aug 22, 2006 page 9 of 13 1 2 3 4 Gate2 to Source Voltage VG2S (V) TBB1012 • FET1 S11 Parameter vs. Frequency .8 S21 Parameter vs. Frequency 1 Scale: 5 / div. 90° 1.5 .6 60° 120° 2 .4 3 30° 150° 4 5 .2 10 .2 0 .4 .6 .8 1 1.5 2 3 45 180° 0° –10 –5 –4 –3 –.2 –30° –150° –.4 –2 –.6 –.8 –120° –1.5 –60° –1 –90° Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 100 kΩ 0.05 to 1.05 GHz (0.05 GHz step) Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 100 kΩ 0.05 to 1.05 GHz (0.05 GHz step) S12 Parameter vs. Frequency S22 Parameter vs. Frequency Scale: 0.05 / div. 90° .8 1 1.5 .6 60° 120° 2 .4 3 30° 150° 4 5 .2 10 180° 0° .2 0 .4 .6 .8 1 1.5 2 3 45 –10 –5 –4 –3 –.2 –30° –150° –.4 –2 –120° –60° –90° Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 100 kΩ 0.05 to 1.05 GHz (0.05 GHz step) Rev.2.00 Aug 22, 2006 page 10 of 13 –.6 –.8 –1.5 –1 Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 100 kΩ 0.05 to 1.05 GHz (0.05 GHz step) TBB1012 • FET2 S11 Parameter vs. Frequency .8 S21 Parameter vs. Frequency 1 Scale: 5 / div. 90° 1.5 .6 60° 120° 2 .4 3 30° 150° 4 5 .2 10 .2 0 .4 .6 .8 1 1.5 2 3 45 180° 0° –10 –5 –4 –3 –.2 –30° –150° –.4 –2 –.6 –.8 –120° –1.5 –60° –1 –90° Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 82 kΩ 0.05 to 1.05 GHz (0.05 GHz step) Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 82 kΩ 0.05 to 1.05 GHz (0.05 GHz step) S12 Parameter vs. Frequency S22 Parameter vs. Frequency Scale: 0.05 / div. 90° .8 1 1.5 .6 60° 120° 2 .4 3 30° 150° 4 5 .2 10 180° 0° .2 0 .4 .6 .8 1 1.5 2 3 45 –10 –5 –4 –3 –.2 –30° –150° –.4 –2 –120° –60° –90° Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 82 kΩ 0.05 to 1.05 GHz (0.05 GHz step) Rev.2.00 Aug 22, 2006 page 11 of 13 –.6 –.8 –1.5 –1 Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 82 kΩ 0.05 to 1.05 GHz (0.05 GHz step) TBB1012 S parameter • FET1 (VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 100 kΩ, Zo = 50 Ω) Freq. (MHz) S11 S21 S12 S22 50 100 150 200 250 300 350 400 450 500 550 600 650 700 Mag 0.994 0.990 0.985 0.978 0.970 0.958 0.946 0.930 0.913 0.894 0.873 0.850 0.826 0.801 Deg -4.3 -8.8 -13.1 -17.6 -22.2 -26.9 -31.7 -36.8 -42.1 -47.7 -53.4 -59.5 -65.8 -72.4 Mag 2.97 2.97 2.97 2.97 2.97 2.96 2.97 2.96 2.95 2.94 2.93 2.91 2.89 2.85 Deg 175.6 171.1 166.7 162.2 157.8 153.1 148.1 143.8 139.0 134.2 129.4 124.3 119.4 114.4 Mag 0.001 0.002 0.002 0.003 0.004 0.005 0.005 0.005 0.005 0.004 0.004 0.003 0.003 0.003 Deg 74.4 89.6 81.5 81.6 77.8 76.9 73.8 72.9 69.4 73.3 73.7 78.4 83.8 113.5 Mag 0.999 0.998 0.997 0.995 0.993 0.992 0.991 0.987 0.982 0.980 0.978 0.973 0.972 0.969 Deg -1.3 -2.8 -4.2 -5.6 -7.0 -8.3 -10.1 -11.0 -12.4 -13.6 -14.8 -16.2 -17.2 -18.5 750 800 850 900 950 1000 0.775 0.749 0.723 0.698 0.674 0.651 -79.2 -86.4 -93.8 -101.4 -109.3 -117.2 2.81 2.77 2.71 2.66 2.59 2.52 109.4 104.3 99.3 94.4 89.4 84.7 0.003 0.005 0.006 0.010 0.012 0.016 151.7 169.5 176.7 176.0 179.6 177.3 0.968 0.967 0.965 0.966 0.965 0.967 -19.6 -20.7 -22.0 -22.9 -24.2 -25.3 • FET2 (VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 82 kΩ, Zo = 50 Ω) Freq (MHz) S11 S21 S12 S22 50 100 150 200 250 300 350 400 450 500 550 600 Mag 0.986 0.983 0.979 0.971 0.963 0.951 0.937 0.923 0.905 0.887 0.868 0.843 Deg -4.8 -10.1 -14.9 -20.0 -25.2 -30.4 -35.9 -41.6 -47.4 -53.7 -60.0 -66.6 Mag 2.96 2.96 2.96 2.95 2.96 2.96 2.96 2.95 2.95 2.93 2.92 2.90 Deg 175.1 169.9 165.0 159.9 154.7 149.6 143.9 139.0 133.8 128.2 122.9 117.3 Mag 0.001 0.002 0.003 0.004 0.004 0.004 0.005 0.005 0.005 0.004 0.004 0.003 Deg 109.6 93.5 77.5 73.2 72.4 69.1 70.2 67.3 66.2 64.6 65.8 71.3 Mag 1.000 0.998 0.998 0.995 0.994 0.992 0.991 0.987 0.982 0.981 0.977 0.973 Deg -1.9 -4.0 -5.9 -8.0 -9.9 -11.9 -14.2 -15.7 -17.7 -19.5 -21.4 -23.3 650 700 750 800 850 900 950 1000 0.821 0.796 0.769 0.744 0.719 0.692 0.669 0.646 -73.6 -80.6 -88.1 -95.9 -103.8 -112.2 -120.7 -129.1 2.88 2.85 2.80 2.76 2.71 2.65 2.58 2.51 111.6 106.1 100.5 94.7 89.2 83.6 78.0 72.8 0.003 0.003 0.003 0.004 0.007 0.010 0.012 0.015 79.4 109.7 139.9 159.6 166.6 166.5 168.6 165.0 0.972 0.969 0.967 0.966 0.964 0.965 0.964 0.966 -25.0 -26.9 -28.6 -30.3 -32.2 -33.7 -35.6 -37.3 Rev.2.00 Aug 22, 2006 page 12 of 13 TBB1012 Package Dimensions JEITA Package Code SC-88 Package Name CMPAK-6 RENESAS Code PTSP0006JA-A D Previous Code CMPAK-6 / CMPAK-6V MASS[Typ.] 0.006g A e Q c E HE LP L A A x M L1 Reference Symbol A3 b S A e A2 A A1 y S S e1 b b1 l1 c1 c b2 A-A Section Pattern of terminal position areas A A1 A2 A3 b b1 c c1 D E e HE L L1 LP x y b2 e1 l1 Q Dimension in Millimeters Min 0.8 0 0.8 0.15 0.1 1.8 1.15 2.0 0.3 0.1 0.2 Nom 0.9 0.25 0.22 0.2 0.13 0.11 2.0 1.25 0.65 2.1 Max 1.1 0.1 1.0 0.3 0.15 2.2 1.35 2.2 0.7 0.5 0.6 0.05 0.05 0.35 1.5 0.9 0.25 Ordering Information Part Name TBB1012MMTL-E Quantity 3000 pcs Shipping Container φ178mm reel, 8mm emboss taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.2.00 Aug 22, 2006 page 13 of 13 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. 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