RQJ0204XGDQA Silicon P Channel MOS FET Power Switching REJ03G1320-0300 Rev.3.00 May 24, 2006 Features • Low on-resistance RDS(on) = 219 mΩ typ (VGS = –4.5 V, ID = –0.8 A) • Low drive current • High speed switching • 2.5 V gate drive Outline RENESAS Package code: PLSP0003ZB-A (Package name: MPAK) 3 D 3 1 2 G 1. Source 2. Gate 3. Drain 2 S 1 Note: Marking is “XG”. Absolute Maximum Ratings (Ta = 25°C) Item Symbol Drain to source voltage VDSS Gate to source voltage VGSS Drain current ID Note1 Drain peak current ID(pulse) Body - drain diode reverse drain current IDR Channel dissipation Pch Note2 Channel temperature Tch Storage temperature Tstg Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1% 2. When using the glass epoxy board (FR-4: 40 x 40 x 1 mm) Rev.3.00 May 24, 2006 page 1 of 6 Ratings –20 +8 / –12 –1.6 –4.0 –1.6 0.8 150 –55 to +150 Unit V V A A A W °C °C RQJ0204XGDQA Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Gate to source breakdown voltage Symbol V(BR)DSS V(BR)GSS V(BR)GSS IGSS IGSS IDSS VGS(off) Min –20 +8 –12 — — — –0.4 Typ — — — — — — — Max — — — +10 –10 –1 –1.4 Unit V V V µA µA µA V Test conditions ID = –10 mA, VGS = 0 IG = +100 µA, VDS = 0 IG = –100 µA, VDS = 0 VGS = +6 V, VDS = 0 VGS = –10 V, VDS = 0 VDS = –20 V, VGS = 0 VDS = –10 V, ID = –1 mA RDS(on) — 219 280 mΩ ID = –0.8 A, VGS = –4.5 VNote3 RDS(on) — 363 510 mΩ ID = –0.8 A, VGS = –2.5 VNote3 Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Turn - on delay time Rise time Turn - off delay time |yfs| Ciss Coss Crss td(on) tr td(off) 1.3 — — — — — — 1.9 153 37 31 14 33 24 — — — — — — — S pF pF pF ns ns ns ID = –0.8 A, VDS = –10 VNote3 Fall time Total gate charge Gate to source charge Gate to drain charge Body - drain diode forward voltage Notes: 3. Pulse test tf Qg Qgs Qgd VDF — — — — — 8 2.2 0.5 0.9 –0.85 — — — — –1.1 ns nC nC nC V Gate to source leak current Drain to source leak current Gate to source cutoff voltage Drain to source on state resistance Rev.3.00 May 24, 2006 page 2 of 6 VDS = –10 V VGS = 0 f = 1 MHz ID = –0.8 A VGS = –4.5 V RL = 12.5 Ω Rg = 4.7 Ω VDD = –10 V VGS = –4.5 V ID = –1.6A IF = –1.6 A, VGS = 0 Note3 RQJ0204XGDQA Main Characteristics Maximum Channel Power Dissipation Curve Maximum Safe Operation Area –100 0.6 0.4 0.2 0 Operation in this area is limited by RDS(on) –10 100 µs 1 PW 0 m s = D 10 C 0 O m pe s ra tio n s m Drain Current ID (A) 0.8 1 Channel Dissipation Pch (W) 1 –1 –0.1 Ta = 25°C 1 Shot Pulse 0 50 100 –0.01 –0.01 150 –0.1 –1 –10 –100 Drain to Source Voltage VDS (V) Ambient Temperature Ta (°C) *When using the glass epoxy board (FR-4: 40 × 40 × 1 mm) Drain Current ID (A) –4 Characteristics –4 –3.2 V –3.4 V –3.6 V –3.8 V –3 Typical Transfer Characteristics (1) –2.8 V –4.0 V –2.6 V –2.4 V –2 –2.2 V –2.0 V –1 Pulse Test Tc = 25°C 0 0 –2 VDS = –10 V Pulse Test –3.0 V Drain Current ID (A) –7 VTypical Output –10 V –6 V –4.5 V VGS = 0 V –4 –6 –8 –3 –2 –1 Tc = 75°C 0 –10 0 Drain to Source Voltage VDS (V) 25°C –25°C –2 –3 –1 –4 –5 Gate to Source Voltage VGS (V) –1 Drain Current ID (A) VDS = –10 V Pulse Test –0.1 –0.01 Tc = 75°C –0.001 25°C –25°C –0.0001 0 –0.5 –1 –1.5 –2 –2.5 –3 Gate to Source Voltage VGS (V) Rev.3.00 May 24, 2006 page 3 of 6 Gate to Source Cutoff Voltage VGS(off) (V) Gate to Source Cutoff Voltage vs. Typical Transfer Characteristics (2) Case Temperature –1.5 VDS = –10 V Pulse Test ID = –10 mA –1 –1 mA –0.5 0 –25 –0.1 mA 0 25 50 75 100 125 150 Case Temperature Tc (°C) –900 Pulse Test Tc = 25°C –800 –700 –600 –500 –400 –300 –1.6 A –0.5 A –200 –100 –0.8 A –0.2 A 0 0 –2 –4 –6 –8 Static Drain to Source on State Resistance vs. Drain Current Drain to Source on State Resistance RDS(on) (mΩ) Drain to Source Saturation Voltage vs. Gate to Source Voltage 10000 Pulse Test Tc = 25°C 1000 VGS = –2.5 V –4.5 V –10 V 100 –10 –0.1 –1 –10 –100 Drain Current ID (A) Static Drain to Source on State Resistance vs. Case Temperature Static Drain to Source on State Resistance vs. Case Temperature 800 400 ID = –1.6 A 700 600 –0.8 A 500 400 –0.5 A 300 –0.2 A 200 Pulse Test VGS = –2.5 V 100 –25 0 25 50 75 Drain to Source on State Resistance RDS(on) (mΩ) Gate to Source Voltage VGS (V) 100 125 150 Pulse Test VGS = –4.5 V ID = –1.6 A 300 –0.8 A –0.5 A 200 –0.2 A 100 –25 0 25 50 75 100 125 150 Case Temperature Tc (°C) Forward Transfer Admittance vs. Drain Current Zero Gate Voltage Drain current vs. Case Temperature 10 Pulse Test VDS = –10 V –25°C 1 25°C 0.1 0.01 –0.01 Tc = 75°C –0.1 –1 Drain Current ID (A) Rev.3.00 May 24, 2006 page 4 of 6 –10 IDSS (nA) Case Temperature Tc (°C) Zero Gate Voltage Drain current Forward Transfer Admittance |yfs| (S) Drain to Source on State Resistance RDS(on) (mΩ) Drain to Source Saturation Voltage VDS(on) (mV) RQJ0204XGDQA –1000 –100 Pulse Test VGS = 0 V VDS = –20 V –10 –1 –0.1 –25 0 25 50 75 100 125 150 Case Temperature Tc (°C) RQJ0204XGDQA Switching Characteristics 0 VDS –10 VDD = –20 V –5 V –10 V –10 V –20 –4 –5 V –8 VDD = –20 V VGS ID = –1.6 A Tc = 25°C –30 0 1 2 3 –12 4 1000 Switching Time t (ns) 0 Gate to Source Voltage VGS (V) Drain to Source Voltage VDS (V) Dynamic Input Characteristics tr td(off) td(on) 10 tf 1 –0.1 6 5 VDD = –10 V VGS = –4.5 V Rg = 4.7 Ω PW = 5 µs 100 Tc = 25°C –1 –10 Gate Charge Qg (nc) Drain Current ID (A) Typical Capacitance vs. Drain to Source Voltage Input Capacitance vs. Gate to Source Voltage 320 1000 300 Ciss 100 Ciss (pF) Ciss, Coss, Crss (pF) VGS = 0 V f = 1 MHz 260 Coss 240 Crss 10 –0 –10 –15 –10 –8 –6 –4 –2 –20 0 2 4 6 8 10 Gate to Source Voltage VGS (V) Reverse Drain Current vs. Source to Drain Voltage Body-Drain Diode Forward Voltage vs. Case Temperature –3 –10V –2 –5V –1 5, 10 V VGS = 0 V –0.4 –0.8 –1.2 –1.6 –2.0 Source to Drain Voltage VSD (V) Rev.3.00 May 24, 2006 page 5 of 6 Body-Drain Diode Forward Voltage VSDF (V) Drain to Source Voltage VDS (V) Pulse Test Tc = 25°C 0 0 VDS = 0 V f = 1 MHz 220 –5 –4 Reverse Drain Current IDR (A) 280 –0.7 VGS = 0 –0.6 –0.5 ID = –10 mA –0.4 –0.3 –1 mA –0.2 –0.1 25 50 75 100 125 Case Temperature Tc (°C) 150 RQJ0204XGDQA Package Dimensions JEITA Package Code SC-59A Package Name MPAK RENESAS Code PLSP0003ZB-A D Previous Code MPAK(T) / MPAK(T)V A Q e E c HE L A MASS[Typ.] 0.011g LP L1 Reference Dimension in Millimeters Symbol Min Nom Max A3 A x M S b A e A2 A e1 A1 S b b1 c1 I1 c b2 A-A Section Pattern of terminal position areas A A1 A2 A3 b b1 c c1 D E e HE L L1 LP x b2 e1 I1 Q Ordering Information Part Name RQJ0204XGDQATL-E Quantity 3000 pcs. Rev.3.00 May 24, 2006 page 6 of 6 Shipping Container φ178 mm reel, 8 mm Emboss taping 1.0 0 1.0 0.35 0.1 2.7 1.35 2.2 0.35 0.15 0.25 1.1 0.25 0.42 0.4 0.13 0.11 1.5 0.95 2.8 1.3 0.1 1.2 0.5 0.15 3.1 1.65 3.0 0.75 0.55 0.65 0.05 0.55 1.95 1.05 0.3 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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