CPMF-1200-S160B Z-FeTTM Silicon Carbide N-Channel Enhancement Mode Bare Die MOSFET Features • • • • • • = 1200 V RDS(on) Qg = 160 mΩ = 47 nC Package D D Industry Leading RDS(on) High Speed Switching Low Capacitances Easy to Parallel Simple to Drive Lead-Free Benefits • • • • VDS Gate Source Source G G SS DIE Higher System Efficiency Reduced Cooling Requirements Avalanche Ruggedness Increase System Switching Frequency Part Number Package CPMF-1200-S160B DIE Applications • • • Solar Inverters Motor Drives Military and Aerospace Maximum Ratings Symbol ID Parameter Continuous Drain Current IDpulse Pulsed Drain Current Value Unit 28 A 18 VGS@20V, TJ = 25˚C 54 A Pulse width tP limited by Tjmax Tj = 25˚C, tp = 1ms Single Pulse Avalanche Energy 500 mJ ID = 10A, VDD = 50 V, L = 9.5 mH EAR Repetitive Avalanche Energy 400 mJ tAR limited by Tjmax IAR Repetitive Avalanche Current 10 A VGS Gate Source Voltage -5/+25 V Ptot Power Dissipation 202 W -55 to +150 ˚C 260 ˚C TL Operating Junction and Storage Temperature Solder Temperature Note: 1. Assumes a thermal resistance junction to case of ≤ 0.62 °C/W. CPMF-1200-S160B Rev. A Note 1 VGS@20V, TJ = 100˚C EAS TJ , Tstg 1 Test Conditions 1 ID = 10A, VDD = 50 V, L = 3 mH tAR limited by Tjmax TJ=25˚C 1.6mm (0.063”) from case for 10s 1 Electrical Characteristics Symbol Parameter Min. V(BR)DSS Drain-Source Breakdown Voltage VGS(th) Gate Threshold Voltage IGSS Gate-Source Leakage Current Ciss Input Capacitance Coss Output Capacitance Crss td(on)i tr td(off)i tfi 2.5 4 0.5 50 5 130 250 Drain-Source On-State Resistance Transconductance V 1.8 Zero Gate Voltage Drain Current gfs Max. Unit 1200 2.1 IDSS RDS(on) Typ. 160 220 190 275 3.7 V μA nA mΩ S 3.4 928 pF VGS = 0V, ID = 100μA VDS = VGS, ID = 1mA, TJ = 25ºC 2 VDS = VGS, ID = 1mA, TJ = 150ºC VDS = 1200V, VGS = 0V, TJ = 25ºC VDS = 1200V, VGS = 0V, TJ = 150ºC VGS = 20V, VDS = 0V VGS = 20V, ID = 10A, TJ = 25ºC VGS = 20V, ID = 10A, TJ = 150ºC VDS= 20V, IDS= 10A, TJ = 25ºC VDS= 20V, IDS= 10A, TJ = 150ºC fig. 3 VDS = 800V fig. 5 f = 1MHz 7.45 Turn-On Delay Time Note VGS = 0V 63 Reverse Transfer Capacitance Test Conditions VAC = 25mV 7 Rise Time 14 Turn-Off Delay Time 46 Fall Time 37 VDD = 800V ns VGS = -2/20V ID = 10A fig. 11 RG = 6.8Ω EON Turn-On Switching Loss (25ºC) (150ºC) 260 225 μJ EOff Turn-Off Switching Loss (25ºC) (150ºC) 120 140 μJ RG Internal Gate Resistance 13.6 Ω L = 856μH Per JEDEC24 Page 27 VGS = 0V, f = 1MHz, VAC = 25mV Note: 2. The recommended on-state VGS is +20V and the recommended off-state VGS is between 0V and -5V Reverse Diode Characteristics Symbol Parameter Vsd Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge Irrm Peak Reverse Recovery Current Typ. Max. 3.5 Unit V 3.1 138 ns 94 nC 1.57 A Test Conditions Note VGS = -5V, IF=5A, TJ = 25ºC VGS = -2V, IF=5A, TJ = 25ºC VGS = -5V, IF=10A, TJ = 25ºC VR = 800V, diF/dt= 100A/μs fig. 12,13 Gate Charge Characteristics Symbol 2 Parameter Typ. Qgs Gate to Source Charge 11.8 Qgd Gate to Drain Charge 21.5 Qg Gate Charge Total 47.1 CPMF-1200-S160B Rev. A Max. Unit nC Test Conditions VDD = 800V ID =10A VGS = -2/20V Per JEDEC24-2 Note fig.8 Typical Performance 60 60 20V V GS= 50 20V V GS= 18V = V GS 50 18V V GS= 40 6V VGS=1 40 6V ID (A) V GS=1 V VGS=14 ID (A) 30 VGS=14V 20 30 VGS=12V 20 VGS=12V 10 VGS=10V 10 VGS=10V 0 0 5 10 15 0 20 0 5 10 VDS (V) 15 20 VDS (V) Fig 1. Typical Output Characteristics TJ = 25ºC Fig 2. Typical Output Characteristics TJ = 150ºC 30 2.00 1.80 25 1.60 Normalized RDS(on) ID (A) 20 TJ = 150°C 15 TJ = 25°C 10 1.40 VGS=20V 1.20 1.00 0.80 5 0.60 0 0 0 2 4 6 8 10 12 14 25 50 75 16 Figure 3. Typical Transfer Characteristics Capacitance (pF) Capacitance Capacitance (pF) Capacitance (F) 10000 10000 Coss Coss 100 100 Crss Crss 10 10 10 50 50 100 100 V VDSV (V) DS(V) DS (V) 150 150 200 200 Ciss Crss 10 CPMF-1200-S160B Rev. A Crss 1 0 0 200 200 400 VDS (V) V 400 600 VDS DS (V)(V) Fig 5A and 5B. Typical Capacitance vs. Drain – Source Voltage 3 VGS = 0VV GS = 0 V f = 1 MHz f = 1 MHz Coss Coss 100 100 1 1 1 Ciss 10001000 Capacitance (pF) VGSV= GS0=V0 V f =f1=MHz 1 MHz 1000 1000 0 0 150 Fig 4. Normalized On-Resistance vs. Temperature Capacitance (F) Ciss Ciss 125 TJ ˚C VGS (V) 10000 10000 100 600 800 800 Typical Performance 400 300 Switching Energy (µJ) Switching Energy (µJ) 350 250 200 150 VGS= -2/20V RG= 11.8Ω Total VDD= 800V ID= 10A 100 VGS= -2/20V RG= 11.8Ω Total VDD= 800V ID= 10A 50 0 0 2 4 6 8 10 12 14 Drain Current (A) Drain Current (A) Fig 6. Inductive Switching Energy(Turn-on) vs ID Fig 7. Inductive Switching Energy(Turn-off) vs ID 20 300 250 Switching Energy (µJ) VGS (V) V GS(V) 15 10 5 ID=10A 0 -5 VDD=800V EON E O FF 150 100 50 0 25 0 10 20 30 Gate Charge (nC) 40 50 Fig 8. Typical Gate Charge Characteristics @ 25°C 4 200 CPMF-1200-S160B Rev. A 50 75 100 125 TJ ˚C Fig 9. Inductive Switching Energy vs. Temp 150 Clamped Inductive Switch Testing Fixture tw pulse duration VGS(on) 90% 90% Input (Vi) 50% 50% 10% 856μH 10% VGS(off) C2D10120D 10A, 1200V SiC Schottky Input Pulse Fall Time Input Pulse Rise Time + 800V 42.3μf - td(on)i iD(on) CMF10120D D.U.T. tfi tri td(off)i 10% 10% Output (iD) 90% 90% iD(off) toff(i) ton(i) Fig 10. Switching Waveform Test Circuit Fig 11. Switching Test Waveform Times trr Qrr= id dt tx ∫ trr Ic tx 10% Irr 10% Vcc 856μH Vcc Vpk CMF10120D D.U.T. + Irr 800V - 42.3μf Diode Recovery Waveforms CMF10120D t2 Erec= id dt t1 ∫ Diode Reverse Recovery Energy t1 t2 Fig 12. Body Diode Recovery Waveform 5 CPMF-1200-S160B Rev. A Fig 13. Body Diode Recovery Test EA = 1/2L x ID2 Fig 14. Avalanche Test Circuit 6 CPMF-1200-S160B Rev. A Fig 15. Theoretical Avalanche Waveform Mechanical Parameters Parameter Typ Unit 3.1 x 3.1 mm 0.93 x 1.18 (x 2) mm 0.84 x 0.60 mm 365 ± 40 µm Frontside (Source) metallization (Al) 4 µm Frontside (Gate) metallization (Al) 4 µm 0.88 / 0.6 µm Die Dimensions (L x W) Exposed Source Pad Metal Dimensions Gate Pad Dimensions Chip Thickness Backside (Drain) metallization (TiNi/Ag) Chip Dimensions Part Number Package CPMF-1200-S160B DIE D D D G GG SS * The levels of environmentally sensitive, persistent biologically toxic (PBT), persistent organic pollutants (POP), or otherwise restricted materials in this product are below the maximum concentration values (also referred to as the threshold limits) permitted for such substances, or are used in an exempted application, in accordance with EU Directive 2002/95/EC on the restriction of the use of certain hazardous substances in electrical and electronic equipment (RoHS), as amended through April 21, 2006. * The die-on-tape method of delivering these SiC die may be considered a means of temporary storage only. Due to an increase in adhesion over time, die stored for an extended period may affix too strongly to the tape. These die should be stored in a temperature-controlled nitrogen dry box soon after receipt. Cree will further recommend that all die be removed from tape to a waffle pack, to a similar storage medium, or used in production within 2 – 3 weeks of delivery to assure 100% release of all die without issues. This product has not been designed or tested for use in, and is not intended for use in, applications implanted into the human body nor in applications in which failure of the product could lead to death, personal injury or property damage, including but not limited to equipment used in the operation of nuclear facilities, life-support machines, cardiac defibrillators or similar emergency medical equipment, aircraft navigation or communication or control systems, air traffic control systems, or weapons systems. Copyright © 2011 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo is a registered trademark of Cree, Inc. 7 CPMF-1200-S160B Rev. A Cree, Inc. 4600 Silicon Drive Durham, NC 27703 USA Tel: +1.919.313.5300 Fax: +1.919.313.5451 www.cree.com/power Applications Information: The Cree SiC DMOSFET has removed the upper voltage limit of silicon MOSFETs. However, there are some differences in characteristics when compared to what is usually expected with high voltage silicon MOSFETs. These differences need to be carefully addressed to get maximum benefit from the SiC DMOSFET. In general, although the SiC DMOSFET is a superior switch compared to its silicon counterparts, it should not be considered as a direct drop-in replacement in existing applications. There are two key characteristics that need to be kept in mind when applying the SiC DMOSFETs; modest transconductance and no turn-off tail. The modest transconductance requires that VGS needs to be 20V to optimize performance. This can be seen the Output and Transfer Characteristics shown in Figures 1-3. The modest transconductance also affects the transition where the device behaves as a voltage controlled resistance to where it behaves as a voltage controlled current source as a function of VDS. The result is that the transition occurs over higher values of VDS than is usually experienced with Si MOSFETs and IGBTs. This might affect the operation anti-desaturation circuits, especially if the circuit takes advantage of the device entering the constant current region at low values of forward voltage. The modest transconductance needs to be carefully considered in the design of the gate drive circuit. The first obvious requirement is that the gate driver be capable of a 22V (or higher) swing. The recommended on state VGS is +20V and the recommended off state VGS is between 0V to -5V. Please carefully note that although the gate voltage swing is higher than typical silicon MOSFETs and IGBTs, the total gate charge of the SiC DMOSFET is considerably lower. In fact, the product of gate voltage swing and gate charge for the SiC DMOSFET is lower than comparable silicon devices. The gate voltage must have a fast dV/dt to achieve fast switching times which indicates that a very low impedance driver is necessary. 2.5V Lastly, the fidelity of the gate drive pulse must be carefully controlled. The nominal threshold voltage is 2.3V and the device is not fully on (dVDS/dt ≈ 0) until the VGS is above 16V. This is a noticeably wider range than what is typically experienced with silicon MOSFETs and IGBTs. The net result of this is that the SiC DMOSFET has a somewhat lower ‘noise margin’. Any excessive ringing that is present on the gate drive signal could cause unintentional turn-on or partial turn-off of the device. The gate resistance should be carefully selected to insure that the gate drive pulse is adequately dampened. To first order, the gate circuit can be approximated as a 8 CPMF-1200-S160B Rev. A R LO O P V P U LS E L LO O P C G ATE As shown, minimizing LLOOP minimizes the value of RLOOP needed for critical dampening. Minimizing LLOOP also minimizes the rise/fall time. Therefore, it is strongly recommended that the gate drive be located as close to the SiC DMOSFET as possible to minimize LLOOP. An external resistance of 6.8 Ω was used to characterize this device. Lower values of external gate resistance can be used so long as the gate pulse fidelity is maintained. In the event that no external gate resistance is used, it is suggested that the gate current be checked to indirectly verify that there is no ringing present in the gate circuit. This can be accomplished with a very small current transformer. A recommended setup is a two-stage current transformer as shown below: The two stage current transformer first stage consists of 10 turns of AWG 30 wire on a small high permeability core. A Ferroxcube 3E27 material is recommended. The second stage is a small wide bandwidth current transformer, such as the Tektronix CT-2. Lastly, a separate source return should be used for the gate drive as shown below: 9 CPMF-1200-S160B Rev. A Stray inductance on source lead causes load di/dt to be fed back into gate drive which causes the following: • Switch di/dt is limited • Could cause oscillation Kelvin gate connection with separate source return is highly recommended LOAD CURRENT 20V 20V R GATE R GATE DRIVE SiC DMOS LOAD CURRENT SiC DMOS DRIVE L STRAY A significant benefit of the SiC DMOSFET is the elimination of the tail current observed in silicon IGBTs. However, it is very important to note that the current tail does provide a certain degree of parasitic dampening during turn-off. Additional ringing and overshoot is typically observed when silicon IGBTs is replaced with SiC DMOSFETs. The additional voltage overshoot can be high enough to destroy the device. Therefore, it is critical to manage the output interconnection parasitics (and snubbers) to keep the ringing and overshoot from becoming problematic. ESD RATINGS 10 ESD Test Total Devices Sampled Resulting Classification ESD-HBM All Devices Passed 1000V 2 (>2000V) ESD-MM All Devices Passed 400V C (>400V) ESD-CDM All Devices Passed 1000V IV (>1000V) CPMF-1200-S160B Rev. A