Cree C2M0040120D SiC Power MOSFET

VDS
1200 V
ID @ 25˚C 60 A
C2M0040120D
Silicon Carbide Power MOSFET
TM
C2M MOSFET Technology
RDS(on)
40 mΩ
N-Channel Enhancement Mode
Features
•
•
•
•
•
•
•
Package
New C2M SiC MOSFET technlogy
High Blocking Voltage with Low On-Resistance
High Speed Switching with Low Capacitances
Easy to Parallel and Simple to Drive
Avalanche Ruggedness
Resistant to Latch-Up
Halogen Free, RoHS Compliant
TO-247-3
Benefits
•
•
•
•
Higher System Efficiency
Reduced Cooling Requirements
Increased Power Density
Increased System Switching Frequency
Applications
•
•
•
•
•
•
Solar Inverters
Switch Mode Power Supplies
High Voltage DC/DC converters
Battery Chargers
Motor Drives
Pulsed Power Applications
Part Number
Package
C2M0040120D
TO-247-3
Maximum Ratings (TC = 25 ˚C unless otherwise specified)
Symbol
Value
Unit
Test Conditions
VDSmax
Drain - Source Voltage
1200
V
VGS = 0 V, ID = 100 μA
VGSmax
Gate - Source Voltage
-10/+25
V
Absolute maximum values
VGSop
Gate - Source Voltage
-5/+20
V
Recommended operational values
ID
Continuous Drain Current
ID(pulse)
PD
TJ , Tstg
1
Parameter
60
40
A
VGS = 20 V, TC = 25˚C
Note
Fig. 19
VGS = 20 V, TC = 100˚C
Pulsed Drain Current
160
A
Pulse width tP limited by Tjmax
Fig. 22
Power Dissipation
330
W
TC=25˚C, TJ = 150 ˚C
Fig. 20
-55 to
+150
˚C
˚C
Operating Junction and Storage Temperature
TL
Solder Temperature
260
Md
Mounting Torque
1
8.8
C2M0040120D Rev. A
1.6mm (0.063”) from case for 10s
Nm
M3 or 6-32 screw
lbf-in
Electrical Characteristics (TC = 25˚C unless otherwise specified)
Symbol
Parameter
V(BR)DSS
Drain-Source Breakdown Voltage
VGS(th)
Gate Threshold Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate-Source Leakage Current
RDS(on)
Min.
Typ.
Max. Unit
1200
VGS = 0 V, ID = 100 μA
2.4
2.8
V
VDS = 10 V, ID = 10mA
1.8
2.0
V
VDS = 10 V, ID = 10mA,TJ = 150 °C
100
μA
VDS = 1200 V, VGS = 0 V
250
nA
VGS = 20 V, VDS = 0 V
1
40
Drain-Source On-State Resistance
52
84
15.1
Transconductance
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
10
Eoss
Coss Stored Energy
82
μJ
EAS
Avalanche Energy, Single Pluse
2
J
EON
Turn-On Switching Energy
1.0
EOFF
Turn Off Switching Energy
0.4
td(on)
Turn-On Delay Time
15
Rise Time
52
Turn-Off Delay Time
26
Fall Time
34
Internal Gate Resistance
1.8
Qgs
Gate to Source Charge
28
Qgd
Gate to Drain Charge
37
Qg
Total Gate Charge
td(off)
tf
RG(int)
VGS = 20 V, ID = 40 A
mΩ
gfs
tr
Test Conditions
V
VGS = 20 V, ID = 40 A, TJ = 150 °C
VDS= 20 V, IDS= 40 A
S
13.2
VDS= 20 V, IDS= 40 A, TJ = 150 °C
1893
VGS = 0 V
150
pF
VDS = 1000 V
Note
Fig. 11
Fig.
4,5,6
Fig. 7
Fig.
17,18
f = 1 MHz
VAC = 25 mV
Fig 16
ID = 40A, VDD = 50V
Fig. 29
mJ
VDS = 800 V, VGS = -5/20 V
ID = 40A, RG(ext) = 2.5Ω, L= 80 μH
Fig. 25
ns
VDD = 800 V, VGS = -5/20 V
ID = 40 A
RG(ext) = 2.5 Ω, RL = 20 Ω
Timing relative to VDS
Per IEC60747-8-4 pg 83
Fig. 27
Ω
f = 1 MHz, VAC = 25 mV
nC
VDS = 800 V, VGS = -5/20 V
ID = 40 A
Per IEC60747-8-4 pg 21
Fig. 12
Test Conditions
Note
115
Reverse Diode Characteristics
Symbol
VSD
Parameter
Diode Forward Voltage
IS
Continuous Diode Forward Current
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
Irrm
Peak Reverse Recovery Current
Typ.
Max.
Unit
3.3
V
VGS = - 5 V, ISD = 20 A, TJ = 25 °C
3.1
V
VGS = - 5 V, ISD = 20 A, TJ = 150 °C
A
TC= 25 °C
Note 1
VGS = - 5 V, ISD = 40 A TJ = 25 °C
VR = 800 V
dif/dt = 1000 A/µs
Note 1
60
54
ns
283
nC
15
A
Fig. 8, 9,
10
Note (1): When using SiC Body Diode the maximum recommended VGS = -5V
Thermal Characteristics
Symbol
2
Parameter
Typ.
Max.
RθJC
Thermal Resistance from Junction to Case
0.34
0.38
RθJC
Thermal Resistance from Junction to Ambient
C2M0040120D Rev. A
40
Unit
°C/W
Test Conditions
Note
Fig. 21
Typical Performance
100
Conditions:
TJ = -55 °C
tp < 200 µs
80
Drain-Source Current, IDS (A)
Conditions:
TJ = 25 °C
tp < 200 µs
VGS = 20 V
VGS = 18 V
60
VGS = 14 V
40
VGS = 12 V
20
VGS = 10 V
0
0.0
2.5
VGS = 20 V
VGS = 18 V
80
VGS = 16 V
Drain-Source Current, IDS (A)
100
5.0
7.5
VGS = 16 V
60
VGS = 12 V
40
VGS = 10 V
20
0
10.0
0.0
2.5
Drain-Source Voltage, VDS (V)
7.5
10.0
Figure 2. Output Characteristics TJ = 25 °C
2.0
Conditions:
TJ = 150 °C
tp < 200 µs
VGS = 16 V
80
Conditions:
IDS = 40 A
VGS = 20 V
tp < 200 µs
1.8
VGS = 14 V
1.6
VGS = 18 V
VGS = 20 V
On Resistance, RDS On (P.U.)
Drain-Source Current, IDS (A)
5.0
Drain-Source Voltage, VDS (V)
Figure 1. Output Characteristics TJ = -55 °C
100
VGS = 14 V
VGS = 12 V
60
VGS = 10 V
40
20
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
0.0
2.5
5.0
7.5
-50
10.0
-25
0
25
Drain-Source Voltage, VDS (V)
100
TJ = 150 °C
80
60
TJ = 25 °C
TJ = -55 °C
40
20
0
125
150
100
VGS = 14 V
80
VGS = 16 V
60
VGS = 18 V
40
VGS = 20 V
20
0
0
20
40
60
80
Drain-Source Current, IDS (A)
Figure 5. On-Resistance vs. Drain Current
For Various Temperatures
3
100
Conditions:
IDS = 40 A
tp < 200 µs
120
On Resistance, RDS On (mOhms)
On Resistance, RDS On (mOhms)
140
Conditions:
VGS = 20 V
tp < 200 µs
120
75
Figure 4. Normalized On-Resistance vs. Temperature
Figure 3. Output Characteristics TJ = 150 °C
140
50
Junction Temperature, TJ (°C)
C2M0040120D Rev. A
100
-50
-25
0
25
50
75
100
125
Junction Temperature, TJ (°C)
Figure 6. On-Resistance vs. Temperature
For Various Gate Voltage
150
Typical Performance
60
Drain-Source Current, IDS (A)
50
-5
-6
Conditions:
VDS = 20 V
tp < 200 µs
-4
VGS = -5 V
-1
0
0
Condition:
TJ = -55 °C
tp < 200 µs
VGS = 0 V
TJ = 150 °C
-20
Drain-Source Current, IDS (A)
40
TJ = 25 °C
30
-2
-3
20
TJ = -55 °C
10
VGS = -2 V
-40
-60
-80
0
0
2
4
6
8
10
12
14
-100
Gate-Source Voltage, VGS (V)
Drain-Source Voltage, VDS (A)
Figure 7. Transfer Characteristic for
Various Junction Temperatures
-5
-4
-3
Drain-Source Current, IDS (A)
VGS = -5 V
-2
-1
0
Condition:
TJ = 25 °C
tp < 200 µs
VGS = 0 V
-6
-5
-4
-3
-2
-1
0
VGS = 0 V
-20
VGS = -2 V
-40
-60
-80
0
Condition:
TJ = 150 °C
tp < 200 µs
VGS = -5 V
Drain-Source Current, IDS (A)
-6
Figure 8. Body Diode Characteristic at -55 ºC
-20
VGS = -2 V
-40
-60
-80
-100
-100
Drain-Source Voltage, VDS (A)
Drain-Source Voltage, VDS (A)
Figure 9. Body Diode Characteristic at 25 ºC
Figure 10. Body Diode Characteristic at 150 ºC
4.0
3.5
Typ
2.5
Min
2.0
1.5
1.0
0.5
0.0
-50
-25
0
25
50
75
100
125
Junction Temperature TJ (°C)
Figure 11. Threshold Voltage vs. Temperature
4
C2M0040120D Rev. A
Conditions:
IDS = 40 A
IGS = 100 mA
VDS = 800 V
TJ = 25 °C
20
Gate-Source Voltage, VGS (V)
Threshold Voltage, Vth (V)
25
Conditions
VDS = 10 V
IDS = 10
0.5mA
mA
3.0
0
150
15
10
5
0
-5
0
20
40
60
80
100
120
Gate Charge, QG (nC)
Figure 12. Gate Charge Characteristics
140
Typical Performance
-6
-5
-4
-3
-2
-1
0
-6
-5
-4
-3
-2
-1
0
0
VGS = 0 V
0
Conditions:
TJ = 25 °C
tp < 200 µs
VGS = 5 V
Drain-Source Current, IDS (A)
-20
-40
VGS = 10 V
VGS = 15 V
-60
VGS = 20 V
-80
-4
-3
-2
-1
-40
-60
VGS = 20 V
-80
VGS = 0 V
Figure 14. 3rd Quadrant Characteristic at 25 ºC
0
100
VGS = 5 V
VGS = 10 V
80
VGS = 20 V
-40
-60
Stored Energy, EOSS (µJ)
-20
VGS = 15 V
Drain-Source Current, IDS (A)
-100
Drain-Source Voltage, VDS (V)
0
Conditions:
TJ = 150 °C
tp < 200 µs
-20
VGS = 15 V
Figure 13. 3rd Quadrant Characteristic at -55 ºC
-5
VGS = 5 V
VGS = 10 V
-100
Drain-Source Voltage, VDS (V)
-6
VGS = 0 V
Drain-Source Current, IDS (A)
Conditions:
TJ = -55 °C
tp < 200 µs
60
40
20
-80
0
0
-100
Drain-Source Voltage, VDS (V)
Ciss
1000
1200
Conditions:
TJ = 25 °C
VAC = 25 mV
f = 1 MHz
1000
Coss
Capacitance (pF)
Capacitance (pF)
800
10000
1000
100
Crss
10
Coss
100
Crss
10
1
0
50
100
Drain-Source Voltage, VDS (V)
150
Figure 17. Capacitances vs. Drain-Source
Voltage (0-200 V)
5
600
Figure 16. Output Capacitor Stored Energy
Conditions:
TJ = 25 °C
VAC = 25 mV
f = 1 MHz
Ciss
400
Drain to Source Voltage, VDS (V)
Figure 15. 3rd Quadrant Characteristic at 150 ºC
10000
200
C2M0040120D Rev. A
200
1
0
200
400
600
Drain-Source Voltage, VDS (V)
800
Figure 18. Capacitances vs. Drain-Source
Voltage (0-1000 V)
1000
Typical Performance
350
Conditions:
TJ ≤ 150 °C
60
Maximum Dissipated Power, Ptot (W)
Drain-Source Continous Current, IDS (DC) (A)
70
50
40
30
20
10
0
Conditions:
TJ ≤ 150 °C
300
250
200
150
100
50
0
-55
-5
45
95
145
-55
-5
Case Temperature, TC (°C)
45
95
145
Case Temperature, TC (°C)
Figure 19. Continuous Drain Current Derating vs.
Case Temperature
Figure 20. Maximum Power Dissipation Derating vs.
Case Temperature
1
100E-3
0.1
0.05
10E-3
0.02
0.01
SinglePulse
1E-3
100 µs
10.00
1 ms
100 ms
1.00
0.10
Conditions:
TC = 25 °C
D = 0,
Parameter: tp
0.01
100E-6
1E-6
10E-6
100E-6
1E-3
Time, tp (s)
10E-3
100E-3
0.1
1
1
100
1000
Figure 22. Safe Operating Area
6
4
Conditions:
TJ = 25 °C
VDD = 800 V
RG(ext) = 2.5 Ω
VGS = -5/+20 V
FWD = C4D20120A
L = 80 μH
4
Conditions:
TJ = 25 °C
VDD = 600 V
RG(ext) = 2.5 Ω
VGS = -5/+20 V
FWD = C4D20120A
L = 80 μH
3.5
3
ETotal
Switching Energy (mJ)
5
Switching Energy (mJ)
10
Drain-Source Voltage, VDS (V)
Figure 21. Transient Thermal Impedance
(Junction - Case)
EOn
3
2
EOff
1
2.5
ETotal
EOn
2
1.5
EOff
1
0.5
0
0
10
20
30
40
50
60
70
80
Drain to Source Current, IDS (A)
Figure 23. Clamped Inductive Switching Energy vs.
Drain Current (VDD = 800V)
6
10 µs
Limited by RDS On
0.3
Drain-Source Current, IDS (A)
Junction To Case Impedance, ZthJC (oC/W)
100.00
0.5
C2M0040120D Rev. A
90
0
0
10
20
30
40
50
60
70
80
Drain to Source Current, IDS (A)
Figure 24. Clamped Inductive Switching Energy vs.
Drain Current (VDD = 600V)
90
Typical Performance
3.0
2.5
Switching Loss (mJ)
2.5
Conditions:
TJ = 25 °C
VDD = 800 V
IDS = 40 A
VGS = -5/+20 V
FWD = C4D20120A
L = 80 μH
ETotal
2.0
EOn
1.5
EOff
1.0
Conditions:
IDS = 40 A
VDD = 800 V
RG(ext) = 2.5 Ω
VGS = -5/+20 V
FWD = C4D20120A
L = 80 µH
2.0
Swithcing Loss (mJ)
3.5
ETotal
1.5
EOn
1.0
EOff
0.5
0.5
0.0
0.0
0
5
10
15
20
25
30
External Gate Resistor RG(ext) (Ohms)
0
25
50
75
100
80
70
tr
60
tf
50
td (off)
40
30
td (on)
20
10
0
0
4
8
12
16
20
External Gate Resistor, RG(ext) (Ohms)
Figure 27. Switching Times vs. RG(ext)
Figure 28. Switching Times Definition
70
Conditons:
VDD = 50 V
Avalanche Current (A)
60
50
40
30
20
10
0
0
25
50
75
100
125
150
Time in Avalanche TAV (us)
Figure 29. Single Avalanche SOA curve
7
C2M0040120D Rev. A
125
Figure 26. Clamped Inductive Switching Energy vs.
Temperature
Conditions:
TJ = 25 °C
VDD = 800 V
RL = 20 Ω
VGS = -5/+20 V
90
Time (ns)
-25
Junction Temperature, TJ (°C)
Figure 25. Clamped Inductive Switching Energy vs. RG(ext)
100
-50
175
200
150
Test Circuit Schematic
L=80 uH
VDC
C4D20120A
20A, 1200V
SiC Schottky
D1
CDC=42.3 uF
D.U.T
C2M0040120D
Q1
Figure 30. Clamped Inductive Switching
Waveform Test Circuit
Q1
L=80
uH
VDC
VGS= - 5V
D.U.T
C2M0040120D
CDC=42.3
uF
Q2
C2M0040120D
Figure 31. Body Diode Recovery Test Circuit
ESD Ratings
8
ESD Test
Total Devices Sampled
Resulting Classification
ESD-HBM
All Devices Passed 1000V
2 (>2000V)
ESD-MM
All Devices Passed 400V
C (>400V)
ESD-CDM
All Devices Passed 1000V
IV (>1000V)
C2M0040120D Rev. A
Package Dimensions
POS
Package TO-247-3
T
V
U
W
Pinout Information:
•
•
•
Pin 1 = Gate
Pin 2, 4 = Drain
Pin 3 = Source
Inches
Millimeters
Min
Max
Min
A
.190
.205
4.83
5.21
A1
.090
.100
2.29
2.54
A2
.075
.085
1.91
2.16
b
.042
.052
1.07
1.33
b1
.075
.095
1.91
2.41
b2
.075
.085
1.91
2.16
b3
.113
.133
2.87
3.38
b4
.113
.123
2.87
3.13
c
.022
.027
0.55
0.68
D
.819
.831
20.80
21.10
D1
.640
.695
16.25
17.65
D2
.037
.049
0.95
1.25
E
.620
.635
15.75
16.13
E1
.516
.557
13.10
14.15
5.10
E2
.145
.201
3.68
E3
.039
.075
1.00
1.90
E4
.487
.529
12.38
13.43
e
.214 BSC
N
3
5.44 BSC
3
L
.780
.800
19.81
20.32
L1
.161
.173
4.10
4.40
ØP
.138
.144
3.51
3.65
Q
.216
.236
5.49
6.00
S
.238
.248
6.04
6.30
T
9˚
11˚
9˚
11˚
U
9˚
11˚
9˚
11˚
V
2˚
8˚
2˚
8˚
W
2˚
8˚
2˚
8˚
Recommended Solder Pad Layout
TO-247-3
9
C2M0040120D Rev. A
Max
Part Number
Package
Marking
C2M0040120D
TO-247-3
C2M0040120
Notes
• RoHS Compliance
The levels of RoHS restricted materials in this product are below the maximum concentration values (also referred
to as the threshold limits) permitted for such substances, or are used in an exempted application, in accordance
with EU Directive 2011/65/EC (RoHS2), as implemented January 2, 2013. RoHS Declarations for this product can
be obtained from your Cree representative or from the Product Documentation sections of www.cree.com.
• REACh Compliance
REACh substances of high concern (SVHCs) information is available for this product. Since the European Chemical Agency (ECHA) has published notice of their intent to frequently revise the SVHC listing for the foreseeable
future,please contact a Cree representative to insure you get the most up-to-date REACh SVHC Declaration.
REACh banned substance information (REACh Article 67) is also available upon request.
•
This product has not been designed or tested for use in, and is not intended for use in, applications implanted into
the human body nor in applications in which failure of the product could lead to death, personal injury or property
damage, including but not limited to equipment used in the operation of nuclear facilities, life-support machines,
cardiac defibrillators or similar emergency medical equipment, aircraft navigation or communication or control
systems, air traffic control systems.
Related Links
•
•
•
C2M PSPICE Models: www.cree.com/power
SiC MOSFET Isolated Gate Driver reference design: www.cree.com/power
Application Considerations for Silicon-Carbide MOSFETs: www.cree.com/power
Copyright © 2014 Cree, Inc. All rights reserved.
The information in this document is subject to change without notice.
Cree, the Cree logo, and Zero Recovery are registered trademarks of Cree, Inc.
10
C2M0040120D Rev. A
Cree, Inc.
4600 Silicon Drive
Durham, NC 27703
USA Tel: +1.919.313.5300
Fax: +1.919.313.5451
www.cree.com/power