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Because the µPD75P0016 supports programming by users, it is suitable for use in prototype testing for system development using the µPD750004, 750006, or 750008 products, and for use in small-lot production. Detailed information about product features and specifications can be found in the following document µPD750008 User's Manual: U10740E FEATURES • Compatible with µPD750008 • Memory capacity: • PROM : 16384 × 8 bits • RAM : 512 × 4 bits • Can operate in same power supply voltage as the mask ROM version µPD750008 • VDD = 2.2 to 5.5 V • Supports QTOP™ microcontroller Remark QTOP Microcontroller is the general name for a total support service that includes imprinting, marking, screening, and verifying one-time PROM single-chip microcontrollers offered by NEC Electronics. ORDERING INFORMATION Part number Package ROM (× 8 bits) µPD75P0016CU 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) µPD75P0016CU-A 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) 16384 µPD75P0016GB-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) 16384 µPD75P0016GB-3BS-MTX-A 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) 16384 Caution On-chip pull-up resistors by mask option cannot be provided. Remark Products with “-A” at the end of the part number are lead-free products. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. U10328EJ3V3DS00 (3rd edition) Date Published August 2005 N CP(K) Printed in Japan The mark shows major revised points. 16384 µPD75P0016 FUNCTION LIST Item Function • 0.95, 1.91, 3.81, 15.3 µs (main system clock: at 4.19 MHz operation) • 0.67, 1.33, 2.67, 10.7 µs (main system clock: at 6.0 MHz operation) • 122 µs (subsystem clock: at 32.768 kHz operation) Instruction execution time On-chip memory PROM 16384 × 8 bits RAM 512 × 4 bits • In 4-bit operation: 8 × 4 banks • In 8-bit operation: 4 × 4 banks General register I/O port CMOS input CMOS I/O N-ch open drain I/O Total 2 8 Connection of on-chip pull-up resistor specifiable by software: 7 18 Direct LED drive capability Connection of on-chip pull-up resistor specifiable by software: 18 8 Direct LED drive capability 13 V withstand voltage 34 Timer 4 channels • 8-bit timer/event counter: 1 channel • 8-bit timer counter: 1 channel • Basic interval timer/watchdog timer: 1 channel • Watch timer: 1 channel Serial interface • 3-wire serial I/O mode ... Switching of MSB/LSB-first • 2-wire serial I/O mode • SBI mode Bit sequential buffer (BSB) 16 bits Clock output (PCL) • Φ, 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation) • Φ, 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation) Buzzer output (BUZ) • 2, 4, 32 kHz (main system clock: at 4.19 MHz operation or subsystem clock: at 32.768 kHz operation) • 2.93, 5.86, 46.9 kHz (main system clock: at 6.0 MHz operation) Vectored interrupt External: 3 Internal: 4 Test input External: 1 Internal: 1 System clock oscillation circuit • Main system clock oscillation ceramic/crystal oscillation circuit • Subsystem clock oscillation crystal oscillation circuit Standby function STOP/HALT mode Operating ambient temperature TA = –40 to +85˚C Supply voltage VDD = 2.2 to 5.5 V Package 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) Data Sheet U10328EJ3V3DS µPD75P0016 TABLE OF CONTENTS 1. PIN CONFIGURATION ........................................................................................................................ 4 2. BLOCK DIAGRAM ............................................................................................................................. 6 3. PIN FUNCTIONS ................................................................................................................................ 7 3.1 3.2 3.3 3.4 4. Port Pins ..................................................................................................................................................... 7 Non-port Pins ............................................................................................................................................. 8 I/O Circuits for Pins ................................................................................................................................... 9 Handling of Unused Pins ........................................................................................................................ 11 SWITCHING BETWEEN MK I AND MK II MODES .......................................................................... 12 4.1 4.2 Differences between Mk I Mode and Mk II Mode ................................................................................... 12 Setting of Stack Bank Selection (SBS) Register ................................................................................... 13 5. DIFFERENCES BETWEEN µPD75P0016 AND µPD750004, 750006, AND 750008 ...................... 14 6. MEMORY CONFIGURATION ........................................................................................................... 15 7. INSTRUCTION SET .......................................................................................................................... 17 8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ................................................... 28 8.1 8.2 8.3 8.4 9. Operation Modes for Program Memory Write/Verify ............................................................................ 28 Steps in Program Memory Write Operation .......................................................................................... 29 Steps in Program Memory Read Operation ........................................................................................... 30 One-Time PROM Screening .................................................................................................................... 31 ELECTRICAL SPECIFICATIONS ..................................................................................................... 32 10. CHARACTERISTIC CURVES (REFERENCE VALUE) .................................................................... 46 11. PACKAGE DRAWINGS .................................................................................................................... 48 12. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 50 APPENDIX A. FUNCTION LIST OF µPD75008, 750008, 75P0016 ....................................................... 52 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................. 54 APPENDIX C. RELATED DOCUMENTS ................................................................................................ 58 Data Sheet U10328EJ3V3DS 3 µPD75P0016 1. PIN CONFIGURATION (Top View) • 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) µPD75P0016CU µPD75P0016CU-A XT1 1 42 VSS XT2 2 41 P40/D0 RESET 3 40 P41/D1 X1 4 39 P42/D2 X2 5 38 P43/D3 P33/MD3 6 37 P50/D4 P32/MD2 7 36 P51/D5 P31/MD1 8 35 P52/D6 P30/MD0 9 34 P53/D7 P81 10 33 P60/KR0 P80 11 32 P61/KR1 P03/SI/SB1 12 31 P62/KR2 P02/SO/SB0 13 30 P63/KR3 P01/SCK 14 29 P70/KR4 P00/INT4 15 28 P71/KR5 P13/TI0 16 27 P72/KR6 P12/INT2 17 26 P73/KR7 P11/INT1 18 25 P20/PTO0 P10/INT0 19 24 P21/PTO1 VPPNote 20 23 P22/PCL VDD 21 22 P23/BUZ Note Directly connect VPP to VDD in the normal operation mode. P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 P53/D7 P52/D6 P51/D5 44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 10 24 P13/TI0 P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P80 P81 P30/MD0 P31/MD1 P32/MD2 11 23 12 13 14 15 16 17 18 19 20 21 22 P33/MD3 NC P43/D3 P42/D2 P41/D1 P40/D0 VSS P50/D4 VPPNote P10/INT0 P11/INT1 P12/INT2 NC µPD75P0016GB-3BS-MTX-A XT1 XT2 RESET X1 X2 µPD75P0016GB-3BS-MTX P73/KR7 P20/PTO0 P21/PTO1 P22/PCL P23/BUZ VDD • 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) Note Directly connect VPP to VDD in the normal operation mode. 4 Data Sheet U10328EJ3V3DS µPD75P0016 PIN IDENTIFICATIONS P00-P03 : Port0 SCK : Serial Clock P10-P13 : Port1 SI : Serial Input P20-P23 : Port2 SO : Serial Output P30-P33 : Port3 SB0, SB1 : Serial Data Bus 0,1 P40-P43 : Port4 RESET : Reset P50-P53 : Port5 TI0 : Timer Input 0 P60-P63 : Port6 PTO0, PTO1 : Programmable Timer Output 0, 1 P70-P73 : Port7 BUZ : Buzzer Clock P80, P81 : Port8 PCL : Programmable Clock KR0-KR7 : Key Return 0-7 INT0, 1, 4 : External Vectored Interrupt 0, 1, 4 VDD : Positive Power Supply INT2 : External Test Input 2 VSS : Ground X1, X2 : Main System Clock Oscillation 1, 2 VPP : Programming Power Supply XT1, XT2 : Subsystem Clock Oscillation 1, 2 NC : No Connection MD0-MD3 : Mode Selection 0-3 D0-D7 : Data Bus 0-7 Data Sheet U10328EJ3V3DS 5 µPD75P0016 2. BLOCK DIAGRAM BIT SEQ. BUFFER (16) BASIC INTERVAL TIMER/ WATCHDOG TIMER PROGRAM COUNTER (14) INTBT SP (8) CY 8-BIT TIMER/EVENT COUNTER #0 TI0/P13 PTO0/P20 INTT0 ALU BANK CLOCKED SERIAL INTERFACE SO/SB0/P02 SCK/P01 P00-P03 PORT1 4 P10-P13 PORT2 4 P20-P23 PORT3 4 P30/MD0-P33/MD3 PORT4 4 P40/D0-P43/D3 PORT5 4 P50/D4-P53/D7 PORT6 4 P60-P63 PORT7 4 P70-P73 PORT8 2 P80, P81 GENERAL REGISTER INTT1 SI/SB1/P03 4 TOUT0 8-BIT TIMER COUNTER #1 PTO1/P21 PORT0 SBS PROGRAM MEMORY (PROM) 16384 × 8 BITS DECODE AND CONTROL DATA MEMORY (RAM) 512 × 4 BITS TOUT0 INTCSI INT0/P10 INT1/P11 INTERRUPT CONTROL INT2/P12 INT4/P00 KR0/P60KR7/P73 8 fx/2N BUZ/P23 WATCH TIMER INTW CLOCK CLOCK OUTPUT DIVIDER CONTROL PCL/P22 6 CPU CLOCK Φ SYSTEM CLOCK GENERATOR SUB MAIN XT1XT2 X1 X2 STAND BY CONTROL Data Sheet U10328EJ3V3DS VPP VDD VSS RESET µPD75P0016 3. PIN FUNCTIONS 3.1 Port Pins Pin name I/O Shared by Function 8-bit I/O When reset I/O circuit type Note 1 This is a 4-bit input port (PORT0). For P01 to P03, on-chip pull-up resistor connections are software-specifiable in 3-bit units. × Input <B> P00 I INT4 P01 I/O SCK P02 I/O SO/SB0 <F>-B P03 I/O SI/SB1 <M>-C P10 I INT0 P11 INT1 P12 INT2 P13 TI0 P20 I/O PTO0 P21 PTO1 P22 PCL P23 BUZ P30 I/O MD0 P31 MD1 P32 MD2 P33 MD3 P40 Note 2 I/O D0 P41 Note 2 D1 P42 Note 2 D2 P43 Note 2 D3 P50 Note 2 I/O D4 P51 Note 2 D5 P52 Note 2 D6 P53 Note 2 D7 P60 I/O KR0 P61 KR1 P62 KR2 P63 KR3 P70 I/O KR4 P71 KR5 P72 KR6 P73 KR7 P80 P81 I/O — — <F>-A This is a 4-bit input port (PORT1). On-chip pull-up resistor connections are softwarespecifiable in 4-bit units. P10/INT0 can select noise elimination circuit. × Input <B>-C This is a 4-bit I/O port (PORT2). On-chip pull-up resistor connections are softwarespecifiable in 4-bit units. × Input E-B This is a programmable 4-bit I/O port (PORT3). Input and output can be specified in single-bit units. On-chip pull-up resistor connections are software-specifiable in 4-bit units. × Input E-B This is an N-ch open-drain 4-bit I/O port (PORT4). In the open-drain mode, withstands up to 13 V. High impedance M-E This is an N-ch open-drain 4-bit I/O port (PORT5). In the open-drain mode, withstands up to 13 V. High impedance M-E This is a programmable 4-bit I/O port (PORT6). Input and output can be specified in single-bit units. On-chip pull-up resistor connections are softwarespecifiable in 4-bit units. Input <F>-A This is a 4-bit I/O port (PORT7). On-chip pull-up resistor connections are softwarespecifiable in 4-bit units. Input <F>-A Input E-B This is a 2-bit I/O port (PORT8). On-chip pull-up resistor connections are softwarespecifiable in 2-bit units. × Notes 1. Circuit types enclosed in brackets indicate Schmitt triggered inputs. 2. Low-level input current leakage increases when input instructions or bit manipulation instructions are executed. Data Sheet U10328EJ3V3DS 7 µPD75P0016 3.2 Non-port Pins Pin name I/O Shared by Function When reset I/O circuit type Note 1 TI0 I P13 External event pulse input to timer/event counter Input <B>-C PTO0 O P20 Timer/event counter output Input E-B P21 Timer counter output Input <F>-A PTO1 PCL P22 Clock output BUZ P23 Outputs any frequency (for buzzer or system clock trimming) P01 Serial clock I/O SO/SB0 P02 Serial data output Serial data bus I/O <F>-B SI/SB1 P03 Serial data input Serial data bus I/O <M>-C SCK I/O INT4 I P00 Edge-triggered vectored interrupt input (Detects both rising and falling edges). INT0 I P10 <B> INT1 P11 Edge-triggered vectored interrupt input With noise eliminator (detected edge is selectable). /asynch selectable INT0/P10 can select noise elimination circuit. Asynch INT2 P12 Rising edge-triggered testable input Input <B>-C Asynch KR0-KR3 I P60-P63 Falling edge-triggered testable input Input <F>-A KR4-KR7 I P70-P73 Falling edge-triggered testable input Input <F>-A X1 I — — — X2 — Ceramic/crystal resonator connection for main system clock. If using an external clock, input it to X1 and input the inverted clock to X2. — Crystal resonator connection for subsystem clock. If using an external clock, input it to XT1 and input the inverted clock to X2. XT1 can be used as a 1-bit (test) input. — — XT1 I XT2 — RESET I — System reset input (low level active) — <B> MD0-MD3 I P30-P33 Mode selection for program memory (PROM) write/verify. Input E-B I/O P40-P43 Data bus pin for program memory (PROM) write/verify. Input M-E D0-D3 D4-D7 P50-P53 VPP Note 2 — — Programmable voltage supply in program memory (PROM) write/verify mode. In normal operation mode, connect directly to VDD. Apply +12.5 V in PROM write/verify mode. — — VDD — — Positive power supply — — VSS — — Ground potential — — Notes 1. Circuit types enclosed in brackets indicate Schmitt triggered inputs. 2. During normal operation, the VPP pin will not operate normally unless connected to VDD pin. 8 Data Sheet U10328EJ3V3DS µPD75P0016 3.3 I/O Circuits for Pins The I/O circuits for the µPD75P0016’s pin are shown in schematic diagrams below. TYPE A TYPE D VDD VDD Data P-ch OUT P-ch IN Output disable N-ch N-ch Push-pull output that can be set to high impedance output (with both P-ch and N-ch OFF). CMOS standard input buffer TYPE B TYPE E-B VDD P.U.R. P.U.R. enable IN P-ch Data IN/OUT Type D Output disable Type A Schmitt trigger input with hysteresis characteristics. P.U.R. : Pull-Up Resistor TYPE B-C TYPE F-A VDD VDD P.U.R. P-ch P.U.R. P.U.R. enable P.U.R. enable P-ch Data IN/OUT Type D IN Output disable Type B P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor (Continued) Data Sheet U10328EJ3V3DS 9 µPD75P0016 TYPE F-B TYPE M-E VDD IN/OUT P.U.R. P.U.R. enable output disable (P) P-ch data N-ch (+13 V) output disable VDD VDD P-ch IN/OUT Input instruction data P.U.R.Note output disable N-ch Voltage limitation (+13 V) circuit output disable (N) Note P.U.R. : Pull-Up Resistor Pull-up resistor that operates only when an input instruction has been executed. (Current flows from VDD to the pins when at low level) TYPE M-C VDD P.U.R. P.U.R. enable P-ch IN/OUT data N-ch output disable P.U.R. : Pull-Up Resistor 10 P-ch Data Sheet U10328EJ3V3DS µPD75P0016 3.4 Handling of Unused Pins Table 3-1. Handling of Unused Pins Pin Recommended connection P00/INT4 Connect to VSS or VDD P01/SCK Individually connect to VSS or VDD via resistor P02/SO/SB0 P03/SI/SB1 Connect to VSS P10/INT0-P12/INT2 Connect to VSS or VDD P13/TI0 P20/PTO0 P21/PTO1 Input mode : individually connect to VSS or VDD via resistor Output mode : open P22/PCL P23/BUZ P30/MD0-P33/MD3 P40/D0-P43/D3 Connect to VSS P50/D4-P53/D7 P60/KR0-P63/KR3 P70/KR4-P73/KR7 Input mode : individually connect to VSS or VDD via resistor Output mode : open P80, P81 XT1Note Note Connect to VSS XT2 Open VPP Make sure to connect directly to VDD Note When the subsystem clock is not used, set SOS. 0 to 1 (not to use the internal feedback resistor). Data Sheet U10328EJ3V3DS 11 µPD75P0016 4. SWITCHING BETWEEN MK I AND MK II MODES Setting a stack bank selection (SBS) register for the µPD75P0016 enables the program memory to be switched between the Mk I mode and the Mk II mode. This capability enables the evaluation of the µPD750004, 750006, or 750008 using the µPD75P0016. When the SBS bit 3 is set to 1: sets Mk I mode (corresponds to Mk I mode of µPD750004, 750006, and 750008) When the SBS bit 3 is set to 0: sets Mk II mode (corresponds to Mk II mode of µPD750004, 750006, and 750008) 4.1 Differences between Mk I Mode and Mk II Mode Table 4-1 lists the differences between the Mk I mode and the Mk II mode of the µPD75P0016. Table 4-1. Differences between Mk I Mode and Mk II Mode Item Mk I mode Mk II mode Program counter PC13-0 Program memory (bytes) 16384 Data memory (bits) 512 × 4 Stack Stack bank Selectable from memory banks 0 and 1 Stack bytes 2 bytes 3 bytes Instruction BRA !addr1 CALLA !addr1 None Provided Instruction CALL !addr 3 machine cycles 4 machine cycles execution time CALLF !faddr 2 machine cycles 3 machine cycles Supported mask ROM versions and mode Mk I mode of µPD750004, 750006, and 750008 Mk II mode of µPD750004, 750006, and 750008 Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This mode enhances the software compatibility with products which have more than 16K bytes. When the Mk II mode is selected, the number of stack bytes used in execution of a subroutine call instruction increases by 1 per stack for the usable area compared to the Mk I mode. Furthermore, when a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine cycle. Therefore, when more importance is attached to RAM utilization or throughput than software compatibility, use the Mk I mode. 12 Data Sheet U10328EJ3V3DS µPD75P0016 4.2 Setting of Stack Bank Selection (SBS) Register Use the stack bank selection register to switch between the Mk I mode and the Mk II mode. Figure 4-1 shows the format for doing this. The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be sure to initialize the stack bank selection register to 100×B Note at the beginning of the program. When using the Mk II mode, be sure to initialize it to 000×B Note. Note Set the desired value for ×. Figure 4-1. Format of Stack Bank Selection Register Address F84H 3 2 1 0 SBS3 SBS2 SBS1 SBS0 Symbol SBS Stack area specification 0 0 Memory bank 0 0 1 Memory bank 1 1 0 1 1 0 Setting prohibited Be sure to set 0 for bit 2. Mode selection specification 0 Mk II mode 1 Mk I mode Caution SBS3 is set to “1” after RESET input, and consequently the CPU operates in the Mk I mode. When using instructions for the Mk II mode, set SBS3 to “0” to enter the Mk II mode before using the instructions. Data Sheet U10328EJ3V3DS 13 µPD75P0016 5. DIFFERENCES BETWEEN µPD75P0016 AND µPD750004, 750006, AND 750008 The µPD75P0016 replaces the internal mask ROM in the µPD750004, 750006, and 750008 with a one-time PROM and features expanded ROM capacity. The µPD75P0016’s Mk I mode supports the Mk I mode in the µPD750004, 750006, and 750008 and the µPD75P0016’s Mk II mode supports the Mk II mode in the µPD750004, 750006, and 750008. Table 5-2 lists differences among the µPD75P0016 and the µPD750004, 750006, and 750008. Be sure to check the differences between corresponding versions beforehand, especially when a PROM version is used for debugging or prototype testing of application systems and later the corresponding mask ROM version is used for full-scale production. Please refer to the µPD750008 User's Manual (U10740E) for details on CPU functions and on-chip hardware. Table 5-1. Differences between µPD75P0016 and µPD750004, 750006, and 750008 µPD750004 Item µPD750006 Program counter 12-bit 13-bit Program memory (bytes) Mask ROM 4096 Mask ROM 6144 µPD750008 µPD75P0016 14-bit Mask ROM 8192 One-time PROM 16384 Data memory (× 4 bits) 512 Mask options Pull-up resistor for port 4 and port 5 Yes (On-chip/not on-chip can be specified.) No (On-chip not possible) Wait time when RESET Yes (217/fx or 215/fx) Note No (fixed at 215/fx) Note Feedback resistor for subsystem clock Yes (can select usable or unusable.) No (usable) Pins 6-9 (CU) P33-P30 P33/MD3-P30/MD0 IC VPP P53-P50 P53/D7-P50/D4 P43-P40 P43/D3-P40/D0 Pin connection Pins 23-26 (GB) Pin 20 (CU) Pin 38 (GB) Pins 34-37 (CU) Pins 8-11 (GB) Pins 38-41 (CU) Pins 13-16 (GB) Other Noise resistance and noise radiation may differ due to the different circuit complexities and mask layouts. Note 217/fx : 21.8 ms @ 6.0 MHz, 31.3 ms @ 4.19 MHz 215/fx : 5.46 ms @ 6.0 MHz, 7.81 ms @ 4.19 MHz Caution Noise resistance and noise radiation are different in PROM version and mask ROM versions. If using a mask ROM version instead of the PROM version for processes between prototype development and full production, be sure to fully evaluate the CS of the mask ROM version (not ES). 14 Data Sheet U10328EJ3V3DS µPD75P0016 6. MEMORY CONFIGURATION Figure 6-1. Program Memory Map 0000H 7 6 MBE RBE 0 Internal reset start address (higher 6 bits) Internal reset start address (lower 8 bits) 0002H MBE RBE INTBT/INT4 start address (higher 6 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE RBE INT0 start address (higher 6 bits) CALLF !faddr instruction entry address INT0 start address (lower 8 bits) 0006H MBE RBE INT1 start address (higher 6 bits) INT1 start address (lower 8 bits) 0008H MBE RBE INTCSI start address (higher 6 bits) BRCB !caddr instruction branch address INTCSI start address (lower 8 bits) 000AH MBE RBE INTT0 start address (higher 6 bits) INTT0 start address (lower 8 bits) 000CH MBE RBE INTT1 start address (higher 6 bits) INTT1 start address (lower 8 bits) Branch address for the following instructions • BR BCDE • BR BCXA • BR !addr • CALL !addr • BRA !addr1Note • CALLA !addr1 Note Branch/call address by GETI 0020H Reference table for GETI instruction 007FH 0080H BR $addr instruction relative branch address (–15 to –1, +2 to +16) 07FFH 0800H 0FFFH 1000H BRCB !caddr instruction branch address 1FFFH 2000H BRCB !caddr instruction branch address 2FFFH 3000H BRCB !caddr instruction branch address 3FFFH Note Can be used only at Mk II mode. Remark For instructions other than those noted above, the “BR PCDE” and “BR PCXA” instructions can be used to branch to addresses with changes in the PC’s lower 8 bits only. Data Sheet U10328EJ3V3DS 15 µPD75P0016 Figure 6-2. Data Memory Map Data memory General register area Memory bank 000H (32 × 4) 01FH 020H Stack area Note 256 × 4 0 (224 × 4) Data area static RAM (512 × 4) 0FFH 100H 256 × 4 1 1FFH Unimplemented F80H 128 × 4 Peripheral hardware area FFFH Note For the stack area, one memory bank can be selected from memory bank 0 or 1. 16 Data Sheet U10328EJ3V3DS 15 µPD75P0016 7. INSTRUCTION SET (1) Representation and coding formats for operands In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s operand representations (for further description, refer to the RA75X Assembler Package User’s Manual [EEU-1363]). When there are several codes, select and use just one. Upper-case letters, and + and – symbols are key words that should be entered as they are. For immediate data, enter an appropriate numerical value or label. Instead of mem, fmem, pmem, bit, etc, a register flag symbol can be described as a label descriptor. (For further description, refer to the µPD750008 User's Manual [U10740E]) Labels that can be entered for fmem and pmem are restricted. Representation Coding format reg X, A, B, C, D, E, H, L reg1 X, B, C, D, E, H, L rp XA, BC, DE, HL rp1 BC, DE, HL rp2 BC, DE rp’ XA, BC, DE, HL, XA’, BC’, DE’, HL’ rp’1 BC, DE, HL, XA’, BC’, DE’, HL’ rpa HL, HL+, HL–, DE, DL rpa1 DE, DL n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label Note bit 2-bit immediate data or label fmem FB0H-FBFH, FF0H-FFFH immediate data or label pmem FC0H-FFFH immediate data or label addr 0000H-3FFFH immediate data or label addr1 0000H-3FFFH immediate data or label (in Mk II mode only) caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20H-7FH immediate data (however, bit0 = 0) or label PORTn PORT0-PORT8 IEXXX IEBT, IECSI, IET0, IET1, IE0-IE2, IE4, IEW RBn RB0-RB3 MBn MB0, MB1, MB15 Note When processing 8-bit data, only even addresses can be specified. Data Sheet U10328EJ3V3DS 17 µPD75P0016 (2) Operation legend A : A register; 4-bit accumulator B : B register C : C register D : D register E : E register H : H register L : L register X : X register XA : Register pair (XA); 8-bit accumulator BC : Register pair (BC) DE : Register pair (DE) HL : Register pair (HL) XA’ : Expansion register pair (XA’) BC’ : Expansion register pair (BC’) DE’ : Expansion register pair (DE’) HL’ : Expansion register pair (HL’) PC : Program counter SP : Stack pointer CY : Carry flag; bit accumulator PSW : Program status word MBE : Memory bank enable flag RBE : Register bank enable flag PORTn : Port n (n = 0 to 8) IME 18 : Interrupt master enable flag IPS : Interrupt priority select register IE××× : Interrupt enable flag RBS : Register bank select register MBS : Memory bank select register PCC : Processor clock control register . : Delimiter for address and bit (××) : Contents of address ×× ××H : Hexadecimal data Data Sheet U10328EJ3V3DS µPD75P0016 (3) Description of symbols used in addressing area MB = MBE • MBS *1 MBS = 0, 1, 15 *2 MB = 0 MBE = 0 : MB = 0 (000H-07FH) Data memory addressing MB = 15 (F80H-FFFH) *3 MBE = 1 : MB = MBS MBS = 0, 1, 15 *4 MB = 15, fmem = FB0H-FBFH, FF0H-FFFH *5 MB = 15, pmem = FC0H-FFFH *6 addr = 0000H-3FFFH addr, addr1 = (Current PC) –15 to (Current PC) –1 *7 (Current PC) +2 to (Current PC) +16 caddr = 0000H-0FFFH (PC13, 12 = 00B) or Program memory addressing 1000H-1FFFH (PC13, 12 = 01B) or *8 2000H-2FFFH (PC13, 12 = 10B) or 3000H-3FFFH (PC13, 12 = 11B) *9 faddr = 0000H-07FFH *10 taddr = 0020H-007FH *11 addr1 = 0000H-3FFFH (Mk II mode only) Remarks 1. MB indicates access-enabled memory banks. 2. In area *2, MB = 0 for both MBE and MBS. 3. In areas *4 and *5, MB = 15 for both MBE and MBS. 4. Areas *6 to *11 indicate corresponding address-enabled areas. Data Sheet U10328EJ3V3DS 19 µPD75P0016 (4) Description of machine cycles S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as shown below. • No skip .......................................................................... S = 0 • Skipped instruction is 1-byte or 2-byte instruction ......... S = 1 • Skipped instruction is 3-byte instruction Note ................. S = 2 Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1 Caution The GETI instruction is skipped for one machine cycle. One machine cycle equals one cycle (= tCY) of the CPU clock Φ. Use the PCC setting to select among four cycle times. 20 Data Sheet U10328EJ3V3DS µPD75P0016 Group Transfer Mnemonic MOV XCH Table reference MOVT Operand No. of Machine bytes cycle Operation Addressing area Skip condition A, # n4 1 1 A ← n4 reg1, # n4 2 2 reg1 ← n4 XA, # n8 2 2 XA ← n8 String-effect A HL, # n8 2 2 HL ← n8 String-effect B rp2, # n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) A, @HL+ 1 2 + S A ← (HL), then L ← L + 1 *1 L=0 A, @HL– 1 2 + S A ← (HL), then L ← L – 1 *1 L = FH A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A *1 @HL, XA 2 2 (HL) ← XA *1 A, mem 2 2 A ← (mem) *3 XA, mem 2 2 XA ← (mem) *3 String-effect A *1 mem, A 2 2 (mem) ← A *3 mem, XA 2 2 (mem) ← XA *3 A, reg 2 2 A ← reg XA, rp’ 2 2 XA ← rp’ reg1, A 2 2 reg1 ← A rp’1, XA 2 2 rp’1 ← XA A, @HL 1 1 A ↔ (HL) A, @HL+ 1 2 + S A ↔ (HL), then L ← L + 1 *1 L=0 A, @HL– 1 2 + S A ↔ (HL), then L ← L – 1 *1 L = FH A, @rpa1 1 1 A ↔ (rpa1) *2 XA, @HL 2 2 XA ↔ (HL) *1 A, mem 2 2 A ↔ (mem) *3 XA, mem 2 2 XA ↔ (mem) *3 A, reg1 1 1 A ↔ reg1 XA, rp’ 2 2 XA ↔ rp’ XA, @PCDE 1 3 XA ← (PC13-8 + DE)ROM XA, @PCXA 1 3 XA ← (PC13-8 + XA)ROM XA, @BCDE 1 3 XA ← (BCDE)ROM Note *6 3 XA ← *6 XA, @BCXA 1 (BCXA)ROM Note *1 Note As for the B register, only the lower 2 bits are valid. Data Sheet U10328EJ3V3DS 21 µPD75P0016 Group Bit transfer Operation Mnemonic MOV1 ADDS ADDC SUBS SUBC AND OR XOR 22 Operand No. of Machine bytes cycle Operation Addressing area Skip condition CY, fmem.bit 2 2 CY ← (fmem.bit) *4 CY, pmem.@L 2 2 CY ← (pmem7-2 + L3-2.bit(L1-0)) *5 CY, @H + mem.bit 2 2 CY ← (H + mem3-0.bit) *1 fmem.bit, CY 2 2 (fmem.bit) ← CY *4 pmem.@L, CY 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← CY *5 @H + mem.bit, CY 2 2 (H + mem3-0.bit) ← CY *1 A, #n4 1 1 + S A ← A + n4 carry XA, #n8 2 2 + S XA ← XA + n8 carry A, @HL 1 1 + S A ← A + (HL) XA, rp’ 2 2 + S XA ← XA + rp’ carry rp’1, XA 2 2 + S rp’1 ← rp’1 + XA carry A, @HL 1 1 A, CY ← A + (HL) + CY XA, rp’ 2 2 XA, CY ← XA + rp’ + CY rp’1, XA 2 2 rp’1, CY ← rp’1 + XA + CY A, @HL 1 1 + S A ← A – (HL) XA, rp’ 2 2 + S XA ← XA – rp’ borrow rp’1, XA 2 2 + S rp’1 ← rp’1 – XA borrow A, @HL 1 1 A, CY ← A – (HL) – CY XA, rp’ 2 2 XA, CY ← XA – rp’ – CY rp’1, XA 2 2 rp’1, CY ← rp’1 – XA – CY A, #n4 2 2 A ← A ^ n4 A, @HL 1 1 A ← A ^ (HL) XA, rp’ 2 2 XA ← XA ^ rp’ rp’1, XA 2 2 rp’1 ← rp’1 ^ XA A, #n4 2 2 A ← A v n4 A, @HL 1 1 A ← A v (HL) XA, rp’ 2 2 XA ← XA v rp’ rp’1, XA 2 2 rp’1 ← rp’1 v XA A, #n4 2 2 A ← A v n4 A, @HL 1 1 A ← A v (HL) XA, rp’ 2 2 XA ← XA v rp’ rp’1, XA 2 2 rp’1 ← rp’1 v XA Data Sheet U10328EJ3V3DS *1 carry *1 *1 *1 *1 *1 *1 borrow µPD75P0016 Group Mnemonic Operand No. of Machine bytes cycle Operation Addressing area Skip condition Accumulator RORC A 1 1 CY ← A0, A3 ← CY, An-1 ← An manipulate NOT A 2 2 A←A Increment/ INCS reg 1 1 + S reg ← reg + 1 reg = 0 rp1 1 1 + S rp1 ← rp1 + 1 rp1 = 00H @HL 2 2 + S (HL) ← (HL) + 1 *1 (HL) = 0 mem 2 2 + S (mem) ← (mem) + 1 *3 (mem) = 0 reg 1 1 + S reg ← reg – 1 reg = FH rp’ 2 2 + S rp’ ← rp’ – 1 rp’ = FFH reg, #n4 2 2 + S Skip if reg = n4 reg = n4 decrement DECS Compare SKE @HL, #n4 2 2 + S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 1 1 + S Skip if A = (HL) *1 A = (HL) XA, @HL 2 2 + S Skip if XA = (HL) *1 XA = (HL) A, reg 2 2 + S Skip if A = reg A = reg XA, rp’ 2 2 +S XA = rp’ Skip if XA = rp’ Carry flag SET1 CY 1 1 CY ← 1 manipulate CLR1 CY 1 1 CY ← 0 SKT CY 1 NOT1 CY 1 1 + S Skip if CY = 1 1 CY = 1 CY ← CY Data Sheet U10328EJ3V3DS 23 µPD75P0016 Group Memory bit Mnemonic SET1 manipulate CLR1 SKT SKF SKTCLR AND1 OR1 XOR1 24 Operand No. of Machine bytes cycle Operation Addressing area mem.bit 2 2 (mem.bit) ← 1 *3 fmem.bit 2 2 (fmem.bit) ← 1 *4 pmem.@L 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← 1 *5 @H + mem.bit 2 2 (H + mem3-0.bit) ← 1 *1 mem.bit 2 2 (mem.bit) ← 0 *3 fmem.bit 2 2 (fmem.bit) ← 0 *4 pmem.@L 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← 0 *5 @H + mem.bit 2 2 (H + mem3-0.bit) ← 0 *1 mem.bit 2 2 + S Skip if(mem.bit) = 1 *3 Skip condition (mem.bit) = 1 fmem.bit 2 2 + S Skip if(fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@L 2 2 + S Skip if(pmem7-2 + L3-2.bit(L1-0)) = 1 *5 (pmem.@L) = 1 @H + mem.bit 2 2 + S Skip if(H + mem3-0.bit) = 1 *1 (@H + mem.bit) = 1 mem.bit 2 2 + S Skip if(mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2 + S Skip if(fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@L 2 2 + S Skip if(pmem7-2 + L3-2.bit(L1-0)) = 0 *5 (pmem.@L) = 0 @H + mem.bit 2 2 + S Skip if(H + mem3-0.bit) = 0 *1 (@H + mem.bit) = 0 fmem.bit 2 2 + S Skip if(fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@L 2 2 + S Skip if(pmem7-2 + L3-2.bit (L1-0)) = 1 and clear *5 (pmem.@L) = 1 @H + mem.bit 2 2 + S Skip if(H + mem3-0.bit) = 1 and clear *1 (@H + mem.bit) = 1 CY, fmem.bit 2 2 CY ← CY ^ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ^ (pmem7-2 + L3-2.bit(L1-0)) *5 CY, @H + mem.bit 2 2 CY ← CY ^ (H + mem3-0.bit) *1 CY, fmem.bit 2 2 CY ← CY v (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY v (pmem7-2 + L3-2.bit(L1-0)) *5 CY, @H + mem.bit 2 2 CY ← CY v (H + mem3-0.bit) *1 CY, fmem.bit 2 2 CY ← CY v (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY v (pmem7-2 + L3-2.bit(L1-0)) *5 CY, @H + mem.bit 2 2 CY ← CY v (H + mem3-0.bit) *1 Data Sheet U10328EJ3V3DS µPD75P0016 Group Branch Mnemonic BR Note 1 Operand No. of Machine bytes cycle Operation Addressing area addr — — PC13-0 ← addr Assembler selects the most appropriate instruction among the following: • BR !addr • BRCB !caddr • BR $addr *6 addr1 — — PC13-0 ← addr1 Assembler selects the most appropriate instruction among the following: • BRA !addr1 • BR !addr • BRCB !caddr • BR $addr1 *11 !addr 3 3 PC13-0 ← addr *6 $addr 1 2 PC13-0 ← addr *7 $addr1 1 2 PC13-0 ← addr1 PCDE 2 3 PC13-0 ← PC13-8 + DE PCXA 2 3 PC13-0 ← PC13-8 + XA BCDE 2 3 PC13-0 ← BCDE Note 2 *6 BCXA 2 3 PC13-0 ← BCXA Note 2 *6 BRA Note 1 !addr1 3 3 PC13-0 ← addr1 *11 BRCB !caddr 2 2 PC13-0 ← PC13, 12 + caddr11-0 *8 Skip condition Notes 1. Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only. 2. As for the B register, only the lower 2 bits are valid. Data Sheet U10328EJ3V3DS 25 µPD75P0016 Group Subroutine Mnemonic Operand CALLA Note !addr1 No. of Machine bytes cycle 3 3 Operation (SP – 5) ← 0, 0, PC13,12 Addressing area Skip condition *11 (SP – 6)(SP – 3)(SP – 4) ← PC11-0 stack control (SP – 2) ← ×, ×, MBE, RBE PC13–0 ← addr1, SP ← SP – 6 CALL Note !addr 3 3 (SP – 4)(SP – 1)(SP – 2) ← PC11-0 *6 (SP – 3) ← (MBE, RBE, PC13, 12) PC13–0 ← addr, SP ← SP – 4 4 (SP – 5) ← 0, 0, PC13,12 (SP – 6)(SP – 3)(SP – 4) ← PC11-0 (SP – 2) ← ×, ×, MBE, RBE PC13-0 ← addr, SP ← SP – 6 CALLF Note !faddr 2 2 (SP – 4)(SP – 1)(SP – 2) ← PC11-0 *9 (SP – 3) ← (MBE, RBE, PC13, 12) PC13-0 ← 000 + faddr, SP ← SP – 4 3 (SP – 5) ← 0, 0, PC13,12 (SP – 6)(SP – 3)(SP – 4) ← PC11-0 (SP – 2) ← ×, ×, MBE, RBE PC13-0 ← 000 + faddr,SP ← SP – 6 RET Note 1 3 (MBE, RBE, PC13, 12) ← (SP + 1) PC11-0 → (SP)(SP + 3)(SP + 2) SP ← SP + 4 ×, ×, MBE, RBE ← (SP + 4) 0, 0, PC13-12 ← (SP + 1) PC11-0 ← (SP)(SP + 3)(SP + 2) SP ← SP + 6 RETS Note 1 3 + S (MBE, RBE, PC13, 12) ← (SP + 1) Unconditional PC11-0 ← (SP)(SP + 3)(SP + 2) SP ← SP + 4 then skip unconditionally ×, ×, MBE, RBE ← (SP + 4) 0, 0, PC13-12 ← (SP + 1) PC11-0 ← (SP)(SP + 3)(SP + 2) SP ← SP + 6 then skip unconditionally RETI Note 1 3 MBE, RBE, PC13, 12 ← (SP + 1) PC11-0 ← (SP)(SP + 3)(SP + 2) PSW ← (SP + 4)(SP + 5), SP ← SP + 6 0, 0, PC13, 12 ← (SP + 1) PC11-0 ← (SP)(SP + 3)(SP + 2) PSW ← (SP + 4)(SP + 5), SP ← SP + 6 Note Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only. 26 Data Sheet U10328EJ3V3DS µPD75P0016 Group Subroutine Mnemonic (SP – 1)(SP – 2) ← rp, SP ← SP – 2 BS 2 2 (SP – 1) ← MBS, (SP – 2) ← RBS, SP ← SP – 2 rp 1 1 rp ← (SP + 1)(SP), SP ← SP + 2 BS 2 2 MBS ← (SP + 1), RBS ← (SP), SP ← SP + 2 2 2 IME(IPS.3) ← 1 2 2 IE××× ← 1 2 2 IME(IPS.3) ← 0 IE××× 2 2 IE××× ← 0 A, PORTn 2 2 A ← PORTn XA, PORTn 2 2 XA ← PORTn+1, PORTn (n = 4, 6) 2 2 PORTn ← A (n = 2 - 8) 2 2 PORTn+1, PORTn ← XA (n = 4, 6) HALT 2 2 Set HALT Mode(PCC.2 ← 1) STOP 2 2 Set STOP Mode(PCC.3 ← 1) NOP 1 1 No Operation RBn 2 2 RBS ← n (n = 0 - 3) MBn 2 2 MBS ← n (n = 0, 1, 15) taddr 1 3 • When using TBR instruction EI IE××× DI IN Note 1 OUT Note 1 PORTn, A PORTn, XA Special Addressing area 1 control CPU control Operation 1 POP I/O No. of Machine bytes cycle rp PUSH stack control Interrupt Operand SEL GETI Note 2, 3 PC ← (taddr) Skip condition (n = 0 - 8) *10 + (taddr + 1) 13-0 5-0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • When using TCALL instruction (SP – 4)(SP – 1)(SP – 2) ← PC11-0 (SP – 3) ← MBE, RBE, PC13, 12 PC13-0 ← (taddr)5-0 + (taddr + 1) SP ← SP – 4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - • When using instruction other than TBR or TCALL Execute (taddr)(taddr + 1) instructions 1 3 • When using TBR instruction PC ← (taddr) Determined by referenced instruction *10 + (taddr + 1) 13-0 5-0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 4 • When using TCALL instruction (SP – 5) ← 0, 0, PC13, 12 (SP – 6)(SP – 3)(SP – 4) ← PC11-0 (SP – 2) ← ×, ×, MBE, RBE PC13-0 ← (taddr)5-0 + (taddr + 1) SP ← SP – 6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3 • When using instruction other than TBR or TCALL Execute (taddr)(taddr + 1) instructions Determined by referenced instruction Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15. 2. TBR and TCALL are assembler directives for the GETI instruction’s table definitions. 3. Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only. Data Sheet U10328EJ3V3DS 27 µPD75P0016 8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY The program memory in the µPD75P0016 is a 16384 × 8-bit electronic write-enabled one-time PROM. The pins listed in the table below are used for this PROM’s write/verify operations. Clock input from the X1 pins is used instead of address input as a method for updating addresses. Pin name Function VPP Pin (usually VDD) where programming voltage is applied during program memory write/verify X1, X2 Clock input pin for address updating during program memory write/verify. Input the X1 pin’s inverted signal to the X2 pin. MD0/P30-MD3/P33 Operation mode selection pin for program memory write/verify D0/P40-D3/P43 (lower 4) 8-bit data I/O pin for program memory write/verify D4/P50-D7/P53 (higher 4) VDD Pin where power supply voltage is applied. Power voltage range for normal operation is 2.2 to 5.5 V. Apply 6.0 V for program memory write/verify. Caution Pins not used for program memory write/verify should be processed as follows. • All unused pins except XT2 ...... Connect to Vss via a pull-down resistor • XT2 pin ........................................ Leave open 8.1 Operation Modes for Program Memory Write/Verify When +6 V is applied to the µPD75P0016’s VDD pin and +12.5 V is applied to its VPP pin, program write/verify modes are in effect. Furthermore, the following detailed operation modes can be specified by setting pins MD0 to MD3 as shown below. Operation mode specification Operation mode VPP VDD MD0 MD1 MD2 MD3 +12.5 V +6 V H L H L Zero-clear program memory address L H H H Write mode L L H H Verify mode H × H H Program inhibit mode Remark ×: L or H 28 Data Sheet U10328EJ3V3DS µPD75P0016 8.2 Steps in Program Memory Write Operation High-speed program memory write can be executed via the following steps. (1) Pull down unused pins to VSS via resistors. Set the X1 pin to low. (2) Apply +5 V to the VDD and VPP pins. (3) Wait 10 µs. (4) Zero-clear mode for program memory addresses. (5) Apply +6 V to VDD and +12.5 V power to VPP. (6) Write data using 1-ms write mode. (7) Verify mode. If write is verified, go to step (8) and if write is not verified, go back to steps (6) and (7). (8) X [= number of write operations from steps (6) and (7)] × 1 ms additional write (9) 4 pulse inputs to the X1 pin updates (increments +1) the program memory address. (10) Repeat steps (6) to (9) until the last address is completed. (11) Zero-clear mode for program memory addresses. (12) Apply +5 V to the VDD and VPP pins. (13) Power supply OFF The following diagram illustrates steps (2) to (9). X repetitions Write Verify Additional write Address increment VPP VPP VDD VDD + 1 VDD VDD X1 D0/P40-D3/P43 D4/P50-D7/P53 Data input Data output Data input MD0/P30 MD1/P31 MD2/P32 MD3/P33 Data Sheet U10328EJ3V3DS 29 µPD75P0016 8.3 Steps in Program Memory Read Operation The µPD75P0016 can read out the program memory contents via the following steps. (1) Pull down unused pins to VSS via resistors. Set the X1 pin to low. (2) Apply +5 V to the VDD and VPP pins. (3) Wait 10 µs. (4) Zero-clear mode for program memory addresses. (5) Apply +6 V power to VDD and +12.5 V to VPP. (6) Verify mode. When a clock pulse is input to the X1 pin, data is output sequentially to one address at a time based on a cycle of four pulse inputs. (7) Zero-clear mode for program memory addresses. (8) Apply +5 V power to the VDD and VPP pins. (9) Power supply OFF The following diagram illustrates steps (2) to (7). VPP VPP VDD VDD + 1 VDD VDD X1 D0/P40-D3/P43 D4/P50-D7/P53 Data output Data output MD0/P30 MD1/P31 “L” MD2/P32 MD3/P33 30 Data Sheet U10328EJ3V3DS µPD75P0016 8.4 One-Time PROM Screening Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC Electronics. Therefore, NEC Electronics recommends the screening process, that is, after the required data is written to the PROM and the PROM is stored under the high- temperature conditions shown below, the PROM should be verified. Storage temperature Storage time 125˚C 24 hours At present, a fee is charged by NEC Electronics for one-time PROM after-programming imprinting, screening, and verify service for the QTOP Microcontroller. For details, contact an NEC Electronics sales representative. Data Sheet U10328EJ3V3DS 31 µPD75P0016 9. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25˚C) Parameter Symbol Conditions Ratings Unit Supply voltage VDD –0.3 to + 7.0 V PROM supply voltage V PP –0.3 to + 13.5 V –0.3 to VDD + 0.3 V –0.3 to + 14 V Input voltage V I1 Other than port 4, 5 V I2 Port 4, 5 (N-ch open drain) Output voltage VO High-level output current IOH –0.3 to V DD + 0.3 V Per pin –10 mA Low-level output current IOL Total of all pins –30 mA Per pin 30 mA Operating ambient temperature TA 220 mA –40 to + 85 ˚C Storage temperature Tstg –65 to + 150 ˚C Total of all pins Caution If the absolute maximum rating of even one of the parameters is exceeded even momentarily, the quality of the product may be degraded. The absolute maximum ratings are therefore values which, when exceeded, can cause the product to be damaged. Be sure that these values are never exceeded when using the product. Capacitance (TA = 25˚C, VDD = 0 V) Parameter Symbol Conditions Input capacitance CIN f = 1 MHz Output capacitance COUT Pins other than tested pins: 0 V I/O capacitance CIO 32 Data Sheet U10328EJ3V3DS MIN. TYP. MAX. Unit 15 pF 15 pF 15 pF µPD75P0016 Main System Clock Oscillation Circuit Characteristics (TA = – 40 to +85˚C) Resonator Recommended constants Ceramic resonator X1 X2 C1 Crystal resonator C2 X1 X2 C1 C2 External clock X1 Parameter Conditions MIN. TYP. 1.0 MAX. Unit 6.0 Note 2 MHz Oscillation frequency (fX) Note 1 VDD = 2.2 to 5.5 V Oscillation stabilization time Note 3 After VDD has reached MIN. value of oscillation voltage range Oscillation frequency (fX) Note 1 VDD = 2.2 to 5.5 V Oscillation stabilization time Note 3 VDD = 4.5 to 5.5 V 10 ms VDD = 2.2 to 5.5 V 30 ms 4 1.0 X1 input frequency (fX) Note 1 VDD = 1.8 to 5.5 V 1.0 X1 input high-, low-level widths (tXH, t XL) VDD = 1.8 to 5.5 V 83.3 ms 6.0 Note 2 MHz 6.0 Note 4 MHz X2 500 ns Notes 1. The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillation circuit only. For the instruction execution time, refer to AC Characteristics. 2. If the oscillation frequency is 4.7 MHz < fX ≤ 6.0 MHz at 2.2 V ≤ VDD < 2.7 V of the supply voltage, please do not set processor clock control register (PCC) = 0011. If PCC = 0011, one machine cycle is less than 0.85 µs, falling short of the rated value of 0.85 µs. 3. The oscillation stablilization time is the time required for oscillation to be stabilized after VDD has been applied or STOP mode has been released. 4. If the X1 input frequency is 4.19 MHz < fx ≤ 6.0 MHz at 1.8 V ≤ VDD < 2.7 V of the supply voltage, please do not set PCC = 0011. If PCC = 0011, one machine cycle time is less than 0.95 µs, falling short of the rated value of 0.95 µs. Caution When using the main system clock oscillation circuit, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influences due to wiring capacitance: · Keep the wiring length as short as possible. · Do not cross the wiring with other signal lines. · Do not route the wiring in the vicinity of a line through which a high alternating current flows. · Always keep the ground point of the capacitor of the oscillation circuit at the same potential as V DD. Do not ground to a power supply pattern through which a high current flows. · Do not extract signals from the oscillation circuit. Data Sheet U10328EJ3V3DS 33 µPD75P0016 Subsystem Clock Oscillation Circuit Characteristics (TA = –40 to +85˚C) Recommended constants Resonator Crystal resonator XT1 Parameter XT2 R C3 C4 Conditions Oscillation frequency (fXT) Note 1 VDD = 2.2 to 5.5 V Oscillation stabilization time Note 2 VDD = 4.5 to 5.5 V MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.0 2 s 10 s VDD = 2.2 to 5.5 V External clock XT1 XT2 XT1 input frequency (fXT) Note 1 VDD = 1.8 to 5.5 V 32 100 kHz XT1 input high-, low-level widths (tXTH, tXTL) VDD = 1.8 to 5.5 V 5 15 µs Notes 1. The oscillation frequency shown above indicate characteristics of the oscillation circuit only. For the instruction execution time, refer to AC Characteristics. 2. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied. Caution When using the subsystem clock oscillation circuit, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influences due to wiring capacitance: · Keep the wiring length as short as possible. · Do not cross the wiring with other signal lines. · Do not route the wiring in the vicinity of a line through which a high alternating current flows. · Always keep the ground point of the capacitor of the oscillation circuit at the same potential as V DD. Do not ground to a power supply pattern through which a high current flows. · Do not extract signals from the oscillation circuit. The subsystem clock oscillation circuit has a low amplification factor to reduce current dissipation and is more susceptible to noise than the main system clock oscillation circuit. Therefore, exercise utmost care in wiring the subsystem clock oscillation circuit. RECOMMENDED OSCILLATION CIRCUIT CONSTANT Main System Clock: Ceramic Resonator (TA = –40 to +85˚C) Manufacturer TDK Corp. Part Number CCR4.0MC32 Frequency Oscillation Circuit Constant (pF) Oscillation Voltage Range (VDD) (MHz) C1 C2 MIN. (V) MAX. (V) 4.0 10 10 2.3 5.5 Remark — Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being used. 34 Data Sheet U10328EJ3V3DS µPD75P0016 DC Characteristics (TA = –40 to + 85˚C, V DD = 2.2 to 5.5 V) Parameter Low-level Symbol IOL output current High-level input V IH1 Conditions V IH3 15 mA mA Ports 2, 3, 8 Ports 0, 1, 6, 7, RESET Ports 4, 5 (N-ch open drain) X1, XT1 Ports 2-5, 8 V IL2 Ports 0, 1, 6, 7, RESET V IL3 X1, XT1 High-level output voltage V OH SCK, SO, ports 2, 3, 6-8 IOH = –1.0 mA Low-level output V OL1 voltage 2.7 ≤ VDD ≤ 5.5 V 0.7 VDD V DD V 2.2 ≤ VDD ≤ 2.7 V 0.9 VDD V DD V 2.7 ≤ VDD ≤ 5.5 V 0.8 VDD V DD V 2.2 ≤ VDD ≤ 2.7 V 0.9 VDD V DD V 2.7 ≤ VDD ≤ 5.5 V 0.7 VDD 13 V 2.2 ≤ VDD ≤ 2.7 V 0.9 VDD 13 V VDD–0.1 V DD V 2.7 ≤ VDD ≤ 5.5 V 0 0.3 VDD V 2.2 ≤ VDD ≤ 2.7 V 0 0.1 VDD V 2.7 ≤ VDD ≤ 5.5 V 0 0.2 VDD V 0 0.1 VDD V 0 0.1 V 2.2 ≤ VDD ≤ 2.7 V V OL2 Unit 150 VIL1 voltage MAX. Per pin V IH4 Low-level input TYP. Total of all pins voltage V IH2 MIN. VDD–0.5 SCK, SO, IOL = 15 mA, VDD = 4.5 to 5.5 V ports 2-8 IOL = 1.6 mA SB0, SB1 N-ch open drain V 0.2 2.0 V 0.4 V 0.2 VDD V Pins other than X1 and XT1 3 µA X1, XT1 20 µA Pull-up resistor ≥ 1 kΩ High-level input ILIH1 leakage current ILIH2 Low-level input leakage current V IN = VDD ILIH3 V IN = 13 V Ports 4, 5 (N-ch open drain) 20 µA ILIL1 V IN = 0 V Pins other than ports 4, 5, X1 and XT1 –3 µA ILIL2 X1, XT1 –20 µA ILIL3 Ports 4, 5 (N-ch open drain) When input instruction is not executed –3 µA –30 µA Ports 4, 5 (N-ch open drain) When input VDD = 5.0 V –10 –27 µA VDD = 3.0 V –3 –8 µA instruction is executed High-level output ILOH1 V OUT = VDD 3 µA leakage current ILOH2 VOUT = 13 V Ports 4, 5 (N-ch open drain) 20 µA Low-level output ILOL V OUT = 0 V –3 µA RL V IN = 0 V 200 kΩ SCK, SO/SB0, SB1, Ports 2, 3, 6-8 leakage current Internal pull-up Ports 0-3, 6-8 (except P00 pin) 50 100 resistor Data Sheet U10328EJ3V3DS 35 µPD75P0016 DC Characteristics (TA = –40 to + 85˚C, V DD = 2.2 to 5.5 V) Parameter Supply current Note 1 Symbol TYP. MAX. IDD1 6.0 MHz Note 2 Conditions V DD = 5.0 V ± 10 % Note 3 3.7 11.0 mA V DD = 3.0 V ± 10 % Note 4 0.73 2.2 mA IDD2 crystal oscillation C1 = C2 = 22 pF V DD = 5.0 V ± 10 % 0.92 2.6 mA V DD = 3.0 V ± 10 % 0.3 0.9 mA HALT mode MIN. Unit IDD1 4.19 MHz Note 2 V DD = 5.0 V ± 10 % Note 3 2.7 8.0 mA V DD = 3.0 V ± 10 % Note 4 0.57 1.7 mA IDD2 crystal oscillation C1 = C2 = 22 pF IDD3 32.768 kHz Note 5 crystal oscillation HALT mode IDD5 0.9 2.5 mA V DD = 3.0 V ± 10 % 0.28 0.8 mA 42 126 µA 23 69 µA 42 84 µA 39 117 µA V DD = 3.0 V ± 10 % Lowvoltage V DD = 2.5 V ± 10 % mode Note 6 V DD = 3.0 V, TA = 25 ˚C Low current dissipation mode Note 7 IDD4 V DD = 5.0 V ± 10 % HALT mode V DD = 3.0 V ± 10 % V DD = 3.0 V, TA = 25 ˚C VDD = 3.0 V ± 10 % Lowvoltage VDD = 2.5 V ± 10 % mode Note 6 39 78 µA 8.5 25 µA 5.0 15 µA VDD = 3.0 V, T A = 25 ˚C 8.5 17 µA Low current VDD = 3.0 V ± 10 % consumption mode Note 7 VDD = 3.0 V, T A = 25 ˚C 3.5 12 µA 3.5 7 µA XT1 = 0V Note 8 V DD = 5.0 V ± 10 % 0.05 10 µA STOP mode V DD = 3.0 V ± 10 % 0.02 5 µA 0.02 3 µA TA = 25 ˚C Notes 1. The current flowing through the internal pull-up resistor is not included. 2. Including the case when the subsystem clock oscillates. 3. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011. 4. When the device operates in low-speed mode with PCC set to 0000. 5. When the device operates on the subsystem clock, with the system clock control register (SCC) set to 1001 and oscillation of the main system clock stopped. 6. When the suboscillation circuit control register (SOS) is set to 0000. 7. When SOS is set to 0010. 8. When SOS is set to 00×1, and the suboscillation circuit feedback resistor is not used (×: don’t care). 36 Data Sheet U10328EJ3V3DS µPD75P0016 AC Characteristics (TA = –40 to + 85˚C, V DD = 2.2 to 5.5 V) Parameter CPU clock cycle Symbol Operates with main system clock tCY time Note 1 (minimum instruction Conditions with ceramic oscillator or crystal resonator with external clock execution time = 1 MIN. MAX. Unit 0.67 64 µs 0.85 64 µs VDD = 2.7 to 5.5 V 0.67 64 µs VDD = 1.8 to 5.5 V 0.95 64 µs VDD = 2.7 to 5.5 V TYP. 125 µs TI0 input frequency fTI V DD = 2.7 to 5.5 V 0 1.0 MHz 0 275 kHz TI0 high-, low-level tTIH, tTIL V DD = 2.7 to 5.5 V 0.48 µs machine cycle) Operates with subsystem clock 114 1.8 µs IM02 = 0 Note 2 µs IM02 = 1 widths Interrupt input high-, tINTH, low-level widths RESET low-level width INT0 122 10 µs INT1, 2, 4 10 µs KR0-KR7 10 µs 10 µs tINTL tRSL Notes 1. The cycle time of the CPU clock (Φ) is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (SCC), and processor clock control register (PCC). The figure on the right shows the supply voltage VDD vs. cycle time tCY characteristics when the device operates with the main system clock. 2. 2t CY or 128/f X depending on the setting of the interrupt mode register (IM0). tCY vs VDD (with main system clock) 64 60 6 5 Operation guaranteed range Cycle time tCY (µ s) 4 3 2 1 0.95 0.85 0.67 0.5 0 Remark 1 1.8 2 2.2 2.7 3 4 5 Supply voltage VDD [V] 5.5 6 Shaded area indicates operation when external clock is used. Data Sheet U10328EJ3V3DS 37 µPD75P0016 Serial Transfer Operation 2-wire and 3-wire serial I/O modes (SCK ··· internal clock output): (TA = –40 to +85 °C, VDD = 2.2 to 5.5 V) Parameter SCK cycle time SCK high-, low-level widths Symbol tKCY1 tKL1, Conditions V DD = 2.7 to 5.5 V V DD = 2.7 to 5.5 V tKH1 SINote 1 setup time tSIK1 V DD = 2.7 to 5.5 V (vs. SCK ↑) SINote 1 hold time tKSI1 V DD = 2.7 to 5.5 V (vs. SCK ↑) SCK ↓ → SONote 1 output tKSO1 VDD = 2.7 to 5.5 V CL = 100 pF delay time Notes 1. RL = 1 kΩNote 2 MIN. TYP. MAX. Unit 1300 ns 3800 ns tKCY1/2–50 ns tKCY1/2–150 ns 150 ns 500 ns 400 ns 600 ns 0 250 ns 0 1000 ns Read as SB0 or SB1 when using the 2-wire serial I/O mode. 2. R L and CL respectively indicate the load resistance and load capacitance of the SO output line. 2-wire and 3-wire serial I/O modes (SCK ··· external clock input): (TA = –40 to +85°C, VDD = 2.2 to 5.5 V) Parameter SCK cycle time SCK high-, low-level widths Symbol tKCY2 tKL2, Conditions V DD = 2.7 to 5.5 V V DD = 2.7 to 5.5 V tKH2 SINote 1 setup time tSIK2 V DD = 2.7 to 5.5 V (vs. SCK ↑) SINote 1 hold time tKSI2 V DD = 2.7 to 5.5 V (vs. SCK ↑) SCK ↓ → SONote 1 output delay time Notes 1. 2. 38 tKSO2 RL = 1 kΩ Note 2 VDD = 2.7 to 5.5 V CL = 100 pF MIN. TYP. MAX. Unit 800 ns 3200 ns 400 ns 1600 ns 100 ns 150 ns 400 ns 600 ns 0 300 ns 0 1000 ns Read as SB0 or SB1 when using the 2-wire serial I/O mode. R L and CL respectively indicate the load resistance and load capacitance of the SO output line. Data Sheet U10328EJ3V3DS µPD75P0016 SBI mode (SCK ··· internal clock output (master)): (TA = –40 to +85°C, VDD = 2.2 to 5.5 V) Parameter SCK cycle time SCK high-, low-level widths Symbol tKCY3 tKL3 Conditions V DD = 2.7 to 5.5 V V DD = 2.7 to 5.5 V tKH3 SB0, 1 setup time tSIK3 V DD = 2.7 to 5.5 V (vs. SCK ↑) SB0, 1 hold time (vs. SCK ↑) tKSI3 SCK ↓ → SB0, 1 output tKSO3 delay time MIN. TYP. MAX. 1300 ns 3800 ns tKCY3/2–50 ns tKCY3/2–150 ns 150 ns 500 ns tKCY3/2 RL = 1 kΩ Note VDD = 2.7 to 5.5 V CL = 100 pF Unit ns 0 250 ns 0 1000 ns SCK ↑ → SB0, 1 ↓ tKSB tKCY3 ns SB0, 1 ↓ → SCK ↓ tSBK tKCY3 ns SB0, 1 low-level width tSBL tKCY3 ns SB0, 1 high-level width tSBH tKCY3 ns Note RL and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines. SBI mode (SCK ··· external clock input (slave)): (TA = –40 to +85°C, VDD = 2.2 to 5.5 V) Parameter SCK cycle time SCK high-, low-level widths Symbol tKCY4 tKL4 Conditions V DD = 2.7 to 5.5 V V DD = 2.7 to 5.5 V tKH4 SB0, 1 setup time tSIK4 V DD = 2.7 to 5.5 V (vs. SCK ↑) SB0, 1 hold time (vs. SCK ↑) tKSI4 SCK ↓ → SB0, 1 output tKSO4 delay time MIN. TYP. MAX. 800 ns 3200 ns 400 ns 1600 ns 100 ns 150 ns tKCY4/2 RL = 1 kΩ Note VDD = 2.7 to 5.5 V CL = 100 pF Unit ns 0 300 ns 0 1000 ns SCK ↑ → SB0, 1 ↓ tKSB tKCY4 ns SB0, 1 ↓ → SCK ↓ tSBK tKCY4 ns SB0, 1 low-level width tSBL tKCY4 ns SB0, 1 high-level width tSBH tKCY4 ns Note RL and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines. Data Sheet U10328EJ3V3DS 39 µPD75P0016 AC Timing Test Points (except X1 and XT1 inputs) VIH (MIN.) VIH (MIN.) VIL (MAX.) VIL (MAX.) VOH (MIN.) VOH (MIN.) VOL (MAX.) VOL (MAX.) Clock timing 1/fX tXL tXH VDD – 0.1 V X1 input 0.1 V 1/fXT tXTL tXTH VDD – 0.1 V XT1 input 0.1 V TI0 timing 1/fTI tTIL tTIH TI0 40 Data Sheet U10328EJ3V3DS µPD75P0016 Serial Transfer Timing 3-wire serial I/O mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 Input data SI tKSO1, 2 Output data SO 2-wire serial I/O mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 SB0, 1 tKSO1, 2 Data Sheet U10328EJ3V3DS 41 µPD75P0016 Serial Transfer Timing Bus release signal transfer tKCY3, 4 tKL3, 4 tKH3, 4 SCK tKSB tSBL tSBH tSIK3, 4 tSBK SB0, 1 tKSO3, 4 Command signal transfer tKCY3, 4 tKL3, 4 tKH3, 4 SCK tKSB tSIK3, 4 tSBK SB0, 1 tKSO3, 4 Interrupt input timing tINTL tINTH INT0, 1, 2, 4 KR0-7 RESET input timing tRSL RESET 42 Data Sheet U10328EJ3V3DS tKSI3, 4 tKSI3, 4 µPD75P0016 Data Retention Characteristics of Data Memory in STOP Mode and at Low Supply Voltage (TA = –40 to +85˚C) Parameter Symbol Release signal setup time Conditions MIN. tSREL Oscillation stabilization TYP. MAX. tWAIT Released by RESET wait time Note 1 Unit µs 0 Released by interrupt request 215/f x ms Note 2 ms Notes 1. The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable operation when oscillation is started. 2. Set by the basic interval timer mode register (BTM). (Refer to the table below.) Wait Time BTM3 BTM2 BTM1 BTM0 – 0 0 0 220/fx (approx. 250 ms) 220/f x (approx. 175 ms) – 0 1 1 217/fx (approx. 31.3 ms) 217/f x (approx. 21.8 ms) – 1 0 1 215/fx (approx. 7.81 ms) 215/f x (approx. 5.46 ms) 1 213/fx 213/f x (approx. 1.37 ms) fx = 4.19 MHz – 1 1 fx = 6.0 MHz (approx. 1.95 ms) Data retention timing (when STOP mode released by RESET) Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD tSREL STOP instruction execution RESET tWAIT Data retention timing (standby release signal: when STOP mode released by interrupt signal) HALT mode STOP mode Operation mode Data retention mode tSREL VDD STOP instruction execution Standby release signal (interrupt request) tWAIT Data Sheet U10328EJ3V3DS 43 µPD75P0016 DC Programming Characteristics (TA = 25 ± 5°C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0V) Parameter Symbol Conditions MIN. MAX. Unit V DD V VDD – 0.5 V DD V 0 0.3 VDD V 0 0.4 V 10 µA 0.4 V 30 mA 30 mA Input voltage, high VIH1 Other than X1, X2 pins 0.7 VDD VIH2 X1, X2 Input voltage, low VIL1 Other than X1, X2 pins VIL2 X1, X2 Input leakage current ILI V IN = VIL or V IH Output voltage, high VOH IOH = – 1 mA Output voltage, low V OL IOL = 1.6 mA V DD supply current IDD V PP supply current IPP TYP. VDD – 1.0 V MD0 = VIL, MD1 = VIH Cautions 1. Keep VPP to within +13.5 V, including overshoot. 2. Apply V DD before VPP and turn it off after V PP. AC Programming Characteristics (TA = 25 ± 5°C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V) Parameter Symbol Note 1 tAS tAS 2 µs MD1 setup time (vs. MD0 ↓) tM1S tOES 2 µs Data setup time (vs. MD0 ↓) tDS tDS 2 µs tAH tAH 2 µs Address setup time (vs. MD0 ↓) Address hold time (vs. MD0 ↑) Note 2 Note 2 Conditions MIN. Data hold time (vs. MD0 ↑) tDH tDH 2 MD0 ↑ → data output float delay time tDF tDF 0 V PP setup time (vs. MD3 ↑) tVPS tVPS 2 V DD setup time (vs. MD3 ↑) tVDS tVCS 2 Initial program pulse width tPW tPW 0.95 Additional program pulse width tOPW tOPW 0.95 MD0 setup time (vs. MD1 ↑) tM0S tCES 2 TYP. MAX. Unit µs 130 ns µs µs 1.0 1.05 ms 21.0 ms µs µs MD0 ↓ → data output delay time tDV tDV MD0 = MD1 = VIL MD1 hold time (vs. MD0 ↑) tM1H tOEH tM1H + tM1R ≥ 50 µs MD1 recovery time (vs. MD0 ↓) tM1R tOR Program counter reset time tPCR — X1 input high-, low-level width tXH, t XL — 0.125 X1 input frequency fX — Initial mode set time t1 — 2 µs MD3 setup time (vs. MD1 ↑) tM3S — 2 µs MD3 hold time (vs. MD1 ↓) tM3H — 2 µs MD3 setup time (vs. MD0 ↓) tM3SR — 2 µs 1 2 µs 2 µs 10 µs When program memory is read → data output tDAD tACC When program memory is read Address Note 2 → data output hold time tHAD tOH When program memory is read 0 MD3 hold time (vs. MD0 ↑) tM3HR — When program memory is read 2 MD3 ↓ → data output float delay time tDFR — When program memory is read Note 2 Address delay time Notes 1. 2. MHz 2 µs 130 ns µs 2 µs Symbol of corresponding µ PD27C256A The internal address signal is incremented by one at the rising edge of the fourth X1 input and is not connected to a pin. 44 µs 4.19 Data Sheet U10328EJ3V3DS µPD75P0016 Program Memory Write Timing tVPS VPP VPP VDD VDD VDD+1 VDD tVDS tXH X1 tXL D0/P40-D3/P43 D4/P50-D7/P53 Data input Data output Data input tDS tI tDS tDH tDV Data input tDH tDF tAH tAS MD0/P30 tPW tM1R tM0S tOPW MD1/P31 tPCR tM1S tM1H MD2/P32 tM3S tM3H MD3/P33 Program Memory Read Timing tVPS VPP VPP VDD tVDS VDD+1 VDD tXH VDD X1 tXL tDAD tHAD D0/P40-D3/P43 D4/P50-D7/P53 Data output Data output tDV tI tDFR tM3HR MD0/P30 MD1/P31 tPCR MD2/P32 tM3SR MD3/P33 Data Sheet U10328EJ3V3DS 45 µPD75P0016 10. CHARACTERISTICS CURVES (REFERENCE VALUE) IDD vs VDD (Main system clock : 6.0 MHz crystal resonator) (TA = 25°C) 10 5.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 Main system clock HALT mode +32-kHz oscillation 1.0 Supply Current IDD (mA) 0.5 Subsystem clock operation mode (SOS.1 = 0) 0.1 0.05 Subsystem clock HALT mode (SOS.1 = 0) and main system clock STOP mode +32-kHz oscillation (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 1) and main system clock STOP mode +32-kHz oscillation (SOS.1 = 1) 0.01 0.005 X2 XT1 X1 22 pF 0.001 0 1 2 3 4 Supply Voltage VDD (V) 46 Data Sheet U10328EJ3V3DS 5 XT2 Crystal resonator Crystal resonator 6.0 MHz 32.768 kHz 22 pF 22 pF 6 330 kΩ 22 pF 7 8 µPD75P0016 IDD vs VDD (Main system clock : 4.19 MHz crystal resonator) (TA = 25°C) 10 5.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 1.0 Main system clock HALT mode +32-kHz oscillation Supply Current IDD (mA) 0.5 Subsystem clock operation mode (SOS.1 = 0) 0.1 0.05 Subsystem clock HALT mode (SOS.1 = 0) and main system clock STOP mode +32-kHz oscillation (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 1) and main system clock STOP mode +32-kHz oscillation (SOS.1 = 1) 0.01 0.005 X1 22 pF 0.001 0 1 2 3 4 5 X2 XT1 XT2 Crystal resonator Crystal resonator 4.19 MHz 32.768 kHz 330 kΩ 22 pF 22 pF 22 pF 6 7 8 Supply Voltage VDD (V) Data Sheet U10328EJ3V3DS 47 µPD75P0016 11. PACKAGE DRAWINGS 42PIN PLASTIC SHRINK DIP (600 mil) 42 22 1 21 A K H G J I L F B D N R M C M NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. ITEM MILLIMETERS INCHES A 39.13 MAX. 1.541 MAX. B 1.78 MAX. 0.070 MAX. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.9 MIN. 0.035 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.08 MAX. 0.200 MAX. K L 15.24 (T.P.) 0.600 (T.P.) 13.2 0.520 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.17 0.007 R 0~15° 0~15° P42C-70-600A-1 48 Data Sheet U10328EJ3V3DS µPD75P0016 44 PIN PLASTIC QFP ( 10) A B 23 22 33 34 detail of lead end C D S R Q 12 11 44 1 F J G H I M K M P N L NOTE ITEM Each lead centerline is located within 0.16 mm (0.007 inch) of its true position (T.P.) at maximum material condition. Data Sheet U10328EJ3V3DS MILLIMETERS INCHES A 13.2±0.2 0.520 +0.008 –0.009 B 10.0±0.2 0.394 +0.008 –0.009 C 10.0±0.2 0.394 +0.008 –0.009 D 13.2±0.2 0.520 +0.008 –0.009 F 1.0 0.039 G 1.0 0.039 H 0.37 +0.08 –0.07 0.015 +0.003 –0.004 I 0.16 0.007 J 0.8 (T.P.) 0.031 (T.P.) K 1.6±0.2 0.063±0.008 L 0.8±0.2 0.031 +0.009 –0.008 M 0.17 +0.06 –0.05 0.007 +0.002 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.125±0.075 R 3° +7° –3° 0.005±0.003 3° +7° –3° S 3.0 MAX. 0.119 MAX. S44GB-80-3BS 49 µPD75P0016 12. RECOMMENDED SOLDERING CONDITIONS The µPD75P0016 should be soldered and mounted under the following recommended conditions. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 12-1. Surface Mounting Type Soldering Conditions (1) µPD75P0016GB-3BS-MTX: 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) Soldering method Soldering conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235˚C, Time: 30 seconds max. (at 210˚C or higher), Count: Three times or less IR35-00-3 VPS Package peak temperature: 215˚C, Time: 40 seconds max. (at 200˚C or higher), Count: Three times or less VP15-00-3 Wave soldering Solder bath temperature: 260˚C max., Time: 10 seconds max., Count: Once WS60-00-1 Preheating temperature: 120˚C max. (package surface temperature) Partial heating Pin temperature: 350˚C max., Time: 3 seconds max. (per pin row) – Caution Do not use different soldering methods together (except for partial heating). Remark For soldering methods and conditions other than those recommended above, contact an NEC Electronics sales representative. (2) µPD75P0016GB-3BS-MTX-A: 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) Soldering method Soldering conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 260˚C, Time: 60 seconds max. (at 220˚C or higher), Count: Three times or less, Exposure limit: 7 daysNote (after that, prebake at 125˚C for 20 to 72 hours) IR60-207-3 Wave soldering For details, contact an NEC Electronics sales representative. – Partial heating Pin temperature: 350˚C max., Time: 3 seconds max. (per pin row) – Note After opening the dry pack, store it at 25˚C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Remarks 1. Products with “-A” at the end of the part number are lead-free products. 2. For soldering methods and conditions other than those recommended above, contact an NEC Electronics sales representative. 50 Data Sheet U10328EJ3V3DS µPD75P0016 Table 12-2. Insertion Type Soldering Conditions µPD75P0016CU: 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) µPD75P0016CU-A: 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) Soldering Method Soldering Conditions Wave soldering (pin only) Solder bath temperature: 260˚C max., Time: 10 seconds max. Partial heating Pin temperature: 300˚C max., Time: 3 seconds max. (for each pin) Caution Apply wave soldering to pins only. See to it that the jet solder does not contact with the chip directly. Remarks 1. Products with “-A” at the end of the part number are lead-free products. 2. For soldering methods and conditions other than those recommended above, contact an NEC Electronics sales representative. Data Sheet U10328EJ3V3DS 51 µPD75P0016 APPENDIX A. FUNCTION LIST OF µPD75008, 750008, 75P0016 (1/2) µPD75008 Item Program memory µPD750008 µPD75P0016 Mask ROM 0000H - 1F7FH Mask ROM 0000H - 1FFFH One-time PROM 0000H - 3FFFH (8064 × 8 bits) (8192 × 8 bits) (16384 × 8 bits) Data memory 000H - 1FFH (512 × 4 bits) CPU 75X Standard CPU 75XL CPU General register 4 bits × 8 or 8 bits × 4 (4 bits × 8 or 8 bits × 4) × 4 banks Instruction execution time When main system clock is selected • 0.95, 1.91, 15.3 µs (at 4.19 MHz operation) • 0.95, 1.91, 3.81, 15.3 µs (at 4.19 MHz operation) • 0.67, 1.33, 2.67, 10.7 µs (at 6.0 MHz operation) When subsystem clock is selected 122 µs (at 32.768 kHz operation) SBS register None Stack Yes SBS.3 = 1: Mk I mode selected SBS.3 = 0: Mk II mode selected Instructions Stack area 000H - 0FFH n00H - nFFH (n = 0, 1) Stack operation of subroutine call instruction 2-byte stack In Mk I mode: 2-byte stack In Mk II mode: 3-byte stack BRA !addr1 CALLA !addr1 Unusable In Mk I mode: Unusable In Mk II mode: Usable MOVT XA, @BCDE MOVT XA, @BCXA BR BCDE BR BCXA Usable CALL !addr 3 machine cycles Mk I mode: 3 machine cycles Mk II mode: 4 machine cycles CALLF !faddr 2 machine cycles Mk I mode: 2 machine cycles Mk II mode: 3 machine cycles Timer 3 channels • Basic interval timer: 1 channel • 8-bit timer/event counter: 1 channel • Watch timer: 1 channel 4 channels • Basic interval timer/watchdog timer: 1 channel • 8-bit timer/event counter: 1 channel • 8-bit timer counter: 1 channel • Watch timer: 1 channel Clock output (PCL) • Φ, 524, 262, 65.5 kHz (main system clock: • Φ, 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation) at 4.19 MHz operation) BUZ output (BUZ) • 2 kHz • Φ, 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation) • 2, 4, 32 kHz (main system clock: at 4.19 MHz operation) • 2.93, 5.86, 46.9 kHz (main system clock: at 6.0 MHz operation) 52 Data Sheet U10328EJ3V3DS µPD75P0016 (2/2) µPD75008 Item Serial interface SOS register µPD750008 µPD75P0016 Compatible with 3 kinds of mode • 3-wire serial I/O mode ... MSB/LSB-first can be switched • 2-wire serial I/O mode • SBI mode Feedback resistor cut flag (SOS.0) On-chip feedback resistor On chip specifiable by mask option Sub oscillator current cut flag (SOS.1) None On chip None Yes Standby release by INT0 Not possible Possible Vectored interrupt External: 3 Internal: 3 External: 3 Internal: 4 Processor clock control register (PCC) PCC = 0, 2, 3 can be used PCC = 0 to 3 can be used Supply voltage VDD = 2.7 to 6.0 V VDD = 2.2 to 5.5 V Operating ambient temperature TA = –40 to +85˚C Package • 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) • 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) Register bank selection register (RBS) Data Sheet U10328EJ3V3DS 53 µPD75P0016 APPENDIX B. DEVELOPMENT TOOLS The following development tools are provided for system development using the µPD75P0016. The 75XL series uses a common relocatable assembler, in combination with a device file matching each machine. RA75X relocatable assembler Host machine Part number OS PC-9800 series TM MS-DOS Supply medium (product name) 3.5" 2HD µS5A13RA75X 3.5" 2HC µS7B13RA75X Ver.3.30 to Ver.6.2 Note Device file IBM PC/ATTM Refer to OS for or compatible IBM PCs Host machine Part number OS PC-9800 series MS-DOS Supply medium (product name) 3.5" 2HD µS5A13DF750008 3.5" 2HC µS7B13DF750008 Ver.3.30 to Ver.6.2 Note IBM PC/AT Refer to OS for or compatible IBM PCs Note Ver. 5.00 and the upper versions of Ver. 5.00 are provided with a task swap function, but it does not work with this software. Remark 54 The operation of the assembler and device file is guaranteed only on the above host machines and OSs. Data Sheet U10328EJ3V3DS µPD75P0016 PROM Write Tools Hardware Software PG-1500 A stand-alone system can be configured of a single-chip microcomputer with on-chip PROM when connected to an auxiliary board (companion product) and a programmer adapter (separately sold). Alternatively, a PROM programmer can be operated on a host machine for programming. In addition, typical PROMs in capacities ranging from 256 K to 4 M bits can be programmed. PA-75P008CU This is a PROM programmer adapter for the µPD75P0016CU/GB. It can be used when connected to a PG-1500. PA-75P0016GB This is a PROM programmer adapter for the µPD75P0016GB-3BS-MTX. It can be used when connected to a PG-1500. PG-1500 controller Establishes serial and parallel connections between the PG-1500 and a host machine for hostmachine control of the PG-1500. Host machine Part number OS PC-9800 Series MS-DOS Supply medium (product name) 3.5" 2HD µS5A13PG1500 3.5" 2HD µS7B13PG1500 Ver.3.30 to Ver.6.2 Note IBM PC/AT Refer to OS for or compatible IBM PCs Note Ver. 5.00 and the upper versions of Ver. 5.00 are provided with a task swapping function, but it does not work with this software. Remark Operation of the PG-1500 controller is guaranteed only on the above host machine and OSs. Data Sheet U10328EJ3V3DS 55 µPD75P0016 Debugging Tools In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the µPD75P0016. Various system configurations using these in-circuit emulators are listed below. Hardware IE-75000-RNote 1 The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems that use 75X or 75XL Series products. For development of the µPD750008 subseries, the IE-75000-R is used with a separately sold emulation board IE75300-R-EM and emulation probe EP-75008CU-R or EP-75008GB-R. These products can be applied for highly efficient debugging when connected to a host machine and PROM programmer. The IE-75000-R can include a connected emulation board (IE-75000-R-EM). IE-75001-R The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems that use 75X or 75XL Series products. The IE-75001-R is used with a separately sold emulation board (IE-75300-R-EM) and emulation probe EP75008CU-R or EP-75008GB-R. These products can be applied for highly efficient debugging when connected to a host machine and PROM programmer. IE-75300-R-EM This is an emulation board for evaluating application systems that use the µPD750008 subseries. It is used in combination with the IE-75000-R or IE-75001-R in-circuit emulator. EP-75008CU-R This is an emulation probe for the µPD75P0016CU. When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM. EP-75008GB-R EV-9200G-44 Software IE control program This is an emulation probe for the µPD75P0016GB. When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM. It includes a 44-pin conversion socket (EV-9200G-44) to facilitate connections with various target systems. This program can control the IE-75000-R or IE-75001-R on a host machine when connected to the IE-75000-R or IE-75001-R via an RS-232-C or Centronics I/F. Host machine Part number OS PC-9800 series MS-DOS Supply medium (product name) 3.5" 2HD µS5A13IE75X 3.5" 2HC µS7B13IE75X Ver.3.30 to Ver.6.2 Note 2 IBM PC/AT Refer to OS for or compatible IBM PCs Notes 1. This is a service part provided for maintenance purpose only. 2. Ver. 5.00 and the upper versions of Ver. 5.00 are provided with a task swapping function, but it does not work with this software. Remarks 1. Operation of the IE control program is guaranteed only on the above host machine and OSs. 2. The µPD75000 subseries consists of the µPD750004, 750006, 750008 and 75P00016. 56 Data Sheet U10328EJ3V3DS µPD75P0016 OS for IBM PCs The following operating systems for the IBM PC are supported. OS TM PC DOS Version Ver.3.1 to Ver.6.3 J6.1/VNote to J6.3/VNote MS-DOS Ver.5.0 to Ver.6.22 5.0/VNote to J6.2/VNote IBM DOSTM J5.02/VNote Note Supports English version only. Caution Ver 5.0 and above include a task swapping function, but this software is not able to use that function. Data Sheet U10328EJ3V3DS 57 µPD75P0016 APPENDIX C. RELATED DOCUMENTS Some of the following related documents are preliminary. This document, however, is not indicated as preliminary. Device Related Documents Document No. Document name Japanese English µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Data Sheet U10738J U10738E µPD75P0016 Data Sheet U10328J This document µPD750008 User’s Manual U10740J U10740E µPD750008, 750108 Instruction List U11456J – 75XL Series Selection Guide U10453J U10453E Development Tool Related Documents Document No. Document name IE-75000 R/IE-75001-R User’s Manual Hardware Software Japanese English EEU-846 EEU-1416 IE-75300-R-EM User’s Manual U11354J U11354E EP-750008CU-R User’s Manual EEU-699 EEU-1317 EP-750008GB-R User’s Manual EEU-698 EEU-1305 PG-1500 User’s Manual U11940J U11940E RA75X Assembler Package Operation U12622J U12622E User’s Manual Language U12385J U12385E PG-1500 Controller User’s Manual PC-9800 Series (MS-DOS) Base EEU-704 EEU-1291 IBM PC Series (PC DOS) Base EEU-5008 U10540E Other Documents Document No. Document name Japanese SEMICONDUCTOR SELECTION GUIDE Products & Package (CD-ROM) English X13769X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices Electrostatic Discharge (ESD) C11892J C11892E Guide for Products Related to Microcomputer : Other Companies C11416J – Caution The above related documents are subject to change without notice. For design purpose, etc., be sure to use the latest documents. 58 Data Sheet U10328EJ3V3DS µPD75P0016 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet U10328EJ3V3DS 59 µPD75P0016 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) NEC Electronics (Europe) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Duesseldorf, Germany Tel: 0211-65030 Hong Kong Tel: 2886-9318 • Sucursal en España Madrid, Spain Tel: 091-504 27 87 • Succursale Française Vélizy-Villacoublay, France Tel: 01-30-67 58 00 • Filiale Italiana Milano, Italy Tel: 02-66 75 41 • Branch The Netherlands Eindhoven, The Netherlands Tel: 040-265 40 10 • Tyskland Filial NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 NEC Electronics Shanghai Ltd. Shanghai, P.R. China Tel: 021-5888-5400 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 Taeby, Sweden Tel: 08-63 87 200 • United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 J05.6 60 Data Sheet U10328EJ3V3DS µPD75P0016 QTOP is a trademark of NEC Corporation. MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. • The information in this document is current as of August, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. 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