SDP18N50 S a mHop Microelectronics C orp. Ver 1.0 N-Channel Logic Level Enhancement Mode Field Effect Transistor FEATURES Super high dense cell design for extremely low RDS(ON). PRODUCT SUMMARY V DSS ID R DS(ON) (m Ω) Max 500V 12A 253 @ VGS=10V High power and current handling capability. TO-220 package. D G G D S SDP SERIES TO-220 S ORDERING INFORMATION Ordering Code Package Marking Code Delivery Mode RoHS Status SDP18N50HZ TO-220 SDP18N50 Tube Halogen Free SDP18N50PZ TO-220 18N50 Tube Pb Free ABSOLUTE MAXIMUM RATINGS ( T C=25 °C unless otherwise noted ) Symbol Parameter VDS VGS Drain-Source Voltage Gate-Source Voltage ID Drain Current-Continuous IDM EAS -Pulsed c Limit 500 ±30 Units T C =25 °C 12 A T C =100 °C 8.5 35 A A 1600 mJ 75 W 37.5 W -55 to 175 °C 2 °C/W ac Single Pulse Avalanche Energy d PD Maximum Power Dissipation TJ, TSTG Operating Junction and Storage Temperature Range TC=25°C TC=100°C THERMAL CHARACTERISTICS R JC Thermal Resistance, Junction-to-Case Details are subject to change without notice. V V Apr,09,2015 1 www.samhop.com.tw SDP18N50 Ver 1.0 ELECTRICAL CHARACTERISTICS ( T C=25 °C unless otherwise noted ) 4 Symbol Parameter OFF CHARACTERISTICS Drain-Source Breakdown Voltage BVDSS IDSS Zero Gate Voltage Drain Current IGSS Gate-Body leakage current ON CHARACTERISTICS Gate Threshold Voltage VGS(th) Drain-Source On-State Resistance RDS(ON) gFS Forward Transconductance DYNAMIC CISS COSS CRSS CHARACTERISTICS b Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS tD(ON) Turn-On DelayTime tr Rise Time tD(OFF) Turn-Off DelayTime tf Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge Conditions Min VGS=0V , ID=250uA 500 Typ 1 ±100 VGS= ±30V , VDS=0V 2 Units V VDS=400V , VGS=0V VDS=VGS , ID=250uA Max uA nA 3 4 VGS=10V , ID=6A VDS=10V , ID=6A 202 22 253 VDS=25V,VGS=0V f=1.0MHz 2854 322 21 pF pF pF 75 32 ns ns ns ns nC nC nC V m ohm S b VDD=250V ID=1A VGS=10V RGEN= 6 ohm VDS=250V,ID=1A,VGS=10V VDS=250V,ID=1A, VGS=10V DRAIN-SOURCE DIODE CHARACTERISTICS VSD VGS=0V,IS=6A Diode Forward Voltage 135 38 42 6 15 0.77 1.3 V Notes _ 1%. _ 10us, Duty Cycle < a.Pulse Test:Pulse Width < b.Guaranteed by design, not subject to production testing. c.Drain current limited by maximum junction temperature. d.Starting TJ=25°C,L=50mH,VDD = 50V.(See Figure13) e.Mounted on FR4 Board of 1 inch2 , 2oz. Apr,09,2015 2 www.samhop.com.tw SDP18N50 Ver 1.0 12.0 50 I D, Drain Current(A) 30 20 10 0 RDS(on)(m Ω) VGS=5V 40 VGS=4V 9.6 7.2 4.8 Tj=125 C -55 C 2.4 25 C 0 0 15 10 5 20 25 30 0 2 3 4 6 5 V GS, Gate-to-Source Voltage(V) Figure 1. Output Characteristics Figure 2. Transfer Characteristics 600 2.5 500 2.2 400 300 V G S =10V 200 100 V G S =10V I D =6A 1.9 1.6 1.3 1.0 0 1 1 10 20 30 40 0 50 I D, Drain Current(A) BVDSS, Normalized Drain-Source Breakdown Voltage V DS =V G S I D =250uA 1.2 1.0 0.8 0.6 0.4 0.2 -50 -25 0 25 50 50 75 100 125 150 T j ( °C ) Figure 4. On-Resistance Variation with Drain Current and Temperature 1.6 1.4 25 Tj, Junction Temperature(° C ) Figure 3. On-Resistance vs. Drain Current and Gate Voltage Vth, Normalized Gate-Source Threshold Voltage 1 VDS, Drain-to-Source Voltage(V) R DS(on), On-Resistance Normalized ID, Drain Current(A) VGS=10V 75 100 125 150 Tj, Junction Temperature(° C ) 1.15 I D =250uA 1.10 1.05 1.00 0.95 0.90 0.85 -50 -25 0 25 50 75 100 125 150 Tj, Junction Temperature(° C ) Figure 5. Gate Threshold Variation with Temperature Figure 6. Breakdown Voltage Variation with Temperature Apr,09,2015 3 www.samhop.com.tw SDP18N50 Ver 1.0 20 900 Is, Source-drain current(A) I D =6A 600 125 C 450 75 C 300 25 C 150 0 2 6 4 75 C 1 10 8 25 C Ciss 2800 Coss 1400 700 Crss 20 30 40 50 VDS=250V ID=1A 8 6 4 2 0 6 12 18 24 30 36 42 V DS, Drain-to-Source Voltage(V) Qg, Total Gate Charge(nC) Figure 9. Capacitance Figure 10. Gate Charge 48 10 1 (O S I D, Drain Current(A) 1 0.1 VDS=250V,ID=1A VGS=10V 10 0.03 0.1 100 s s Tr Tf 0u ms DC TD(on) 10 10 100 10 1m TD(off ) it 100 1000 Switching Time(ns) 1.25 0 0 10 1.00 10 RD C, Capacitance(pF) V GS, Gate to Source Voltage(V) 4200 0 0.75 Figure 8. Body Diode Forward Voltage Variation with Source Current Figure 7. On-Resistance vs. Gate-Source Voltage 2100 0.50 VSD, Body Diode Forward Voltage(V) V GS, Gate-to-Source Voltage(V) 3500 0.25 0 L im 0 125 C 10 N) R DS(on)(m Ω) 750 VGS=10V Single Pulse TC=25 C 1 10 100 1000 Rg, Gate Resistance(Ω) V DS, Drain-Source Voltage(V) Figure 11. switching characteristics Figure 12. Maximum Safe Operating Area Apr,09,2015 4 www.samhop.com.tw SDP18N50 Ver 1.0 V ( BR )D S S tp L V DS D .U .T RG + - IA S VDD 20V 0.0 1 tp IAS Unclamped Inductive Test Circuit Unclamped Inductive Waveforms F igure 13a. F igure 13b. r(t),Normalized Effective Transient Thermal Impedance 2 1 D=0.5 0.2 0.1 0.1 P DM 0.05 t1 0.02 t2 0.01 1. 2. 3. 4. S ingle P uls e 0.01 0.00001 0.0001 0.001 0.01 0.1 R J C (t)=r (t) * R J C R J C =S ee Datas heet T J M-T C = P * R J C (t ) Duty C ycle, D=t1/t2 1 10 Square Wave Pulse Duration (msec) Figure 14. Normalized Thermal Transient Impedance Curve Apr,09,2015 5 www.samhop.com.tw SDP18N50 Ver 1.0 Apr,09,2015 6 www.samhop.com.tw SDP18N50 Ver 1.0 TO-220 Tube Apr,09,2015 7 www.samhop.com.tw SDP18N50 Ver 1.0 TOP MARKING DEFINITION TO-220 (Halogen Free) SamHop Logo SDP18N50 XXXXXX Product No. SMC internal code No. (A,B,C...Z) Wafer Lot Number TO-220 (Pb Free) Production Date (1,2 ~ 9, A,B...) Production Month (1,2 ~ 9, A,B,C) Production Year (2009 = 9, 2010 = A...) SamHop Logo PB Free Product No. 18N50 XXXXX Production Year (2009 = 9, 2010 = A...) Production Month (1,2 ~ 9, A,B,C) Production Date (1,2 ~ 9, A,B...) Wafer Lot Number Apr,09,2015 8 www.samhop.com.tw