Datasheet 4.5V to 13.2V, 2A 1ch Synchronous Buck Converter integrated FET BD9141MUV ●General Description ROHM’s high efficiency step-down switching regulator BD9141MUV is a power supply designed to produce a low voltage including 5.0/3.3 volts from 2 lithium cell power supply line. Offers high efficiency with our original pulse skip control technology and synchronous rectifier. Employs a current mode control system to provide faster transient response to sudden change in load. ●Key Specifications Input voltage range: Output voltage range: Output current: Switching frequency: Pch FET ON resistance: Nch FET ON resistance: Standby current: Operating temperature range: ●Features ■ Offers fast transient response with current mode PWM control system. ■ Offers highly efficiency for all load range with synchronous rectifier (Nch/Pch FET) and SLLM (Simple Light Load Mode) ■ Incorporates soft-start function. ■ Incorporates thermal protection and ULVO functions. ■ Incorporates short-current protection circuit with time delay function. ■ Incorporates shutdown function ●Package VQFN020V4040: 4.5V to 13.2V 2.5V to 6.0V 2.0A(Max.) 500KHz(Typ.) 150mΩ(Typ.) 80mΩ(Typ.) 0µA (Typ.) -40℃ to +105℃ (Typ.) (Typ.) (Max.) 4.00mm x 4.00mm x 1.00mm ●Applications Power supply for LSI including DSP, Micro computer and ASIC VQFN020V4040 ●Typical Application Circuit Fig.1 Typical Application Circuit ○Product structure：Silicon monolithic integrated circuit www.rohm.com ©2012 ROHM Co., Ltd. All rights reserved. TSZ22111･14･001 ○This product is not designed protection against radioactive rays. 1/19 TSZ02201-0J3J0AJ00180-1-2 02.MAR.2012 Rev.001 Datasheet BD9141MUV ●Pin Configuration (TOP VIEW) GND ADJ ITH VREG N.C. 15 14 13 12 11 N.C. 16 EN PGND 10 Vcc 17 9 N.C. 18 8 19 7 20 6 1 2 3 4 PVcc 5 SW Fig.2 Pin Configuration ●Pin Description Pin No. 1,2,3,4,5 6,7,8 9 10 11 12 13 14 15,16 17 18,19,20 Pin Name SW PVCC N.C. Vcc GND ADJ ITH VREG N.C. EN PGND Pin Function Pch/Nch FET drain output pin Pch FET source pin Non connection VCC power supply input pin Ground Output voltage detect pin GmAmp output pin/Connected phase compensation capacitor Reference Voltage Non connection Enable pin(Active High) Nch FET source pin ●Block Diagram Fig.3 Block Diagram www.rohm.com ©2012 ROHM Co., Ltd. All rights reserved. TSZ22111･15･001 2/19 TSZ02201-0J3J0AJ00180-1-2 02.MAR.2012 Rev.001 Datasheet BD9141MUV ●Absolute Maximum Ratings Parameter Symbol VCC Voltage VCC PVCC Voltage PVCC EN Voltage Unit -0.3 to +15 *1 V -0.3 to +15 *1 V VEN -0.3 to +15 V VSW -0.3 to +15 V VITH,VREG, VADJ, -0.3 to +7 V SW Voltage ITH,VREG,ADJ Voltage Limits Power Dissipation 1 Pd1 0.34 *2 W W W Power Dissipation 2 Pd2 0.70 *3 Power Dissipation 3 Pd3 2.21 *4 3.56 *5 Power Dissipation 4 Pd4 W Operating temperature range Topr -40 to +105 ℃ Storage temperature range Tstg -55 to +150 ℃ Tjmax +150 ℃ Maximum junction temperature *1 *2 *3 *4 *5 Pd should not be exceeded. IC only. 1 layer, mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB (Copper foil area : 10.29mm2) 4 layers, mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB (1st ,4th Copper foil area : 10.29mm2 2nd ,3rd Copper foil area : 5505mm2) ,. 4 layers, mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB (Copper foil area : 5505mm2) , copper foil in each layers. ●Recommended Operating Ratings Parameter VCC Voltage PVCC Voltage EN Voltage SW average output current Output voltage Setting Range *6 *7 (Ta=-40 to +105℃) Symbol *6 VCC *6 PVCC VEN Isw *6 VOUT *7 Limits Typ. 8.0 Max. 13.2 V 8.0 13.2 V 0 - VCC V - - 2.0 A 2.5 - 6.0 V Min. *7 4.5 4.5 *7 Unit Pd should not be exceeded. VccMin. = Vout + 1.3V. ●Electrical Characteristics (Ta=25℃, VCC=PVCC=8.0V, EN=VCC, R1=8.2kΩ, R2=43kΩ, unless otherwise specified.) Limits Parameter Symbol Unit Conditions Min. Typ. Max. Standby current ISTB 0 10 µA EN=GND Bias current ICC - 300 500 µA EN Low voltage VENL - GND 0.8 V Standby mode EN High voltage VENH 2.0 VCC - V Active mode VEN=8V EN input current IEN - 1.6 10 µA FOSC 400 500 600 KHz Pch FET ON resistance RONP - 150 300 mΩ PVCC=8V Nch FET ON resistance RONN - 80 160 mΩ PVCC=8V ADJ Voltage VADJ 0.788 0.800 0.812 V ITH SInk current ITHSI 10 20 - µA VADJ=1.0V ITH Source Current ITHSO 10 20 - µA VADJ=0.6V UVLO threshold voltage VUVLO1 3.90 4.10 4.30 V VCC=8V→0V UVLO release voltage VUVLO2 3.95 4.20 4.50 V VCC=0V→8V TSS 0.5 1 2 ms TLATCH 1 2 3 ms VSCP - 0.4 0.56 V Oscillation frequency Soft start time Timer latch time Output Short circuit Threshold Voltage www.rohm.com ©2012 ROHM Co., Ltd. All rights reserved. TSZ22111･15･001 3/19 SCP/TSD operated VADJ=0.8V→0V TSZ02201-0J3J0AJ00180-1-2 02.MAR.2012 Rev.001 Datasheet BD9141MUV ●Typical Performance Curves Fig.5 VEN-VOUT Fig.4 VCC-VOUT Fig.7 Ta-VOUT Fig.6 IOUT-VOUT www.rohm.com ©2012 ROHM Co., Ltd. All rights reserved. TSZ22111･15･001 4/19 TSZ02201-0J3J0AJ00180-1-2 02.MAR.2012 Rev.001 Datasheet BD9141MUV Fig.8 Efficiency Fig.9 Ta-FOSC Fig.10 Ta-RONN, RONP Fig.11 Ta-VEN www.rohm.com ©2012 ROHM Co., Ltd. All rights reserved. TSZ22111･15･001 5/19 TSZ02201-0J3J0AJ00180-1-2 02.MAR.2012 Rev.001 Datasheet BD9141MUV Fig.12 Ta-Icc Fig.13 VCC-FOSC Fig.14 Soft start waveform www.rohm.com ©2012 ROHM Co., Ltd. All rights reserved. TSZ22111･15･001 Fig.15 SW waveform Io=10mA 6/19 TSZ02201-0J3J0AJ00180-1-2 02.MAR.2012 Rev.001 Datasheet BD9141MUV Fig.16 SW waveform Io=2000mA Fig.17 Transient response Io=0.5A→1A(10µs) Fig.18 Transient response Io=1A→0.5A(10µs) www.rohm.com ©2012 ROHM Co., Ltd. All rights reserved. TSZ22111･15･001 7/19 TSZ02201-0J3J0AJ00180-1-2 02.MAR.2012 Rev.001 Datasheet BD9141MUV Application Information ●Operation BD9141MUV is a synchronous rectifying step-down switching regulator that achieves faster transient response by employing current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for heavier load, while it utilizes SLLM (Simple Light Load Mode) operation for lighter load to improve efficiency. ○Synchronous rectifier It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC, and its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power dissipation of the set is reduced. ○Current mode PWM control Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback. ・PWM (Pulse Width Modulation) control The oscillation frequency for PWM is 500kHz. SET signal form OSC turns ON a P-channel MOS FET (while a N-channel MOS FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp) receives two signals, a current feedback control signal (SENSE: Voltage converted from I L) and a voltage feedback control signal (FB), and issues a RESET signal if both input signals are identical to each other, and turns OFF the P-channel MOS FET (while a N-channel MOS FET is turned ON) for the rest of the fixed period. The PWM control repeat this operation. ・SLLM (Simple Light Load Mode) control When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse is designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation without voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa. Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current Comp, it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is tuned OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces the switching dissipation and improves the efficiency. SENSE Current Comp RESET VOUT Level Shift R Q FB SET Gm Amp. ITH S IL Driver Logic VOUT SW Load OSC Fig.19 Diagram of current mode PWM control PVCC Current Comp SENSE PVCC SENSE Current Comp FB FB SET GND SET GND RESET GND RESET GND SW GND SW IL GND IL(AVE) IL 0A VOUT VOUT VOUT(AVE) TMNot switching Fig.20 PWM switching timing chart www.rohm.com ©2012 ROHM Co., Ltd. All rights reserved. TSZ22111･15･001 VOUT(AVE) Fig.21 SLLM 8/19 switching timing chart TSZ02201-0J3J0AJ00180-1-2 02.MAR.2012 Rev.001 Datasheet BD9141MUV ●Description of Operations ・Soft-start function EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited during startup, by which it is possible to prevent an overshoot of output voltage and an inrush current. ・Shutdown function With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0µA (Typ.). ・UVLO function Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. of 100mV (Typ.) is provided to prevent output chattering. And the hysteresis width Hysteresis 100mV VCC EN VOUT Tss Tss Tss Soft start Standby mode Operating mode Standby mode Standby mode Operating mode UVLO UVLO Operating mode EN Standby mode UVLO Fig.22 Soft start, Shutdown, UVLO timing chart ・Short-current protection circuit with time delay function Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for the fixed time(TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking UVLO. EN Output OFF latch Output Short circuit Threshold Voltage VOUT IL Limit IL t1<TLATCH Standby mode t2=TLATCH Operating mode EN Standby mode Timer latch Operating mode EN Fig.23 Short-current protection circuit with time delay timing chart www.rohm.com ©2012 ROHM Co., Ltd. All rights reserved. TSZ22111･15･001 9/19 TSZ02201-0J3J0AJ00180-1-2 02.MAR.2012 Rev.001 Datasheet BD9141MUV ●Information on Advantages Advantage 1：Offers fast transient response with current mode control system. BD9141MUV (Load response IO=0.5A→1A) Conventional product (Load response IO=0.5A→1A) VOUT VOUT 50mV 110mV IOUT IOUT Voltage drop due to sudden change in load was reduced by about 50%. Fig.24 Comparison of transient response Advantage 2： Offers high efficiency for all load range. ・For lighter load: Utilizes the current mode control mode called SLLM for lighter load, which reduces various dissipation such as switching dissipation (PSW), gate charge/discharge dissipation, ESR dissipation of output capacitor (PESR) and on-resistance dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load. Achieves efficiency improvement for lighter load. ・For heavier load: Utilizes the synchronous rectifying mode and the low on-resistance MOS FETs incorporated as power transistor. ON resistance of P-channel MOS FET : 150mΩ(Typ.) ON resistance of N-channel MOS FET : 80mΩ(Typ.) Efficiency η[%] 100 Achieves efficiency improvement for heavier load. SLLM ② 50 ① PWM ①improvement by SLLM system ②improvement by synchronous rectifier 0 0.001 Offers high efficiency for all load range with the improvements mentioned above. 0.01 0.1 Output current Io[A] 1 Fig.25 Efficiency Advantage 3：・Supplied in smaller package due to small-sized power MOS FET incorporated. ・Output capacitor Co required for current mode control: 22µF ceramic capacitor ・Inductance L required for the operating frequency of 500kHz: 2.2µH inductor (BD9141MUV:Co=22µF, L=4.7µH) Reduces a mounting area required. VCC 15mm Cin CIN DC/DC Convertor Controller RITH RITH L VOUT L 10mm CITH Co CO CITH Fig.26 Example application www.rohm.com ©2012 ROHM Co., Ltd. All rights reserved. TSZ22111･15･001 10/19 TSZ02201-0J3J0AJ00180-1-2 02.MAR.2012 Rev.001 Datasheet BD9141MUV ●Switching Regulator Efficiency Efficiency ŋ may be expressed by the equation shown below: η= VOUT×IOUT ×100[%]= POUT POUT ×100[%]= ×100[%] Vin×Iin Pin POUT+PDα Efficiency may be improved by reducing the switching regulator power dissipation factors P Dα as follows: Dissipation factors: 2 1) ON resistance dissipation of inductor and FET：PD(I R) 2) Gate charge/discharge dissipation：PD(Gate) 3) Switching dissipation：PD(SW) 4) ESR dissipation of capacitor：PD(ESR) 5) Operating current dissipation of IC：PD(IC) 2 2 1)PD(I R)=IOUT ×(RCOIL+RON) (RCOIL[Ω]：DC resistance of inductor, RON[Ω]：ON resistance of FET, IOUT[A]：Output current.) 2 2)PD(Gate)=Cgs×f×V (Cgs[F]：Gate capacitance of FET, f[H]：Switching frequency, V[V]：Gate driving voltage of FET) 2 Vin ×CRSS×IOUT×f (CRSS[F]：Reverse transfer capacitance of FET, IDRIVE[A]：Peak current of gate.) 3)PD(SW)= IDRIVE 2 4)PD(ESR)=IRMS ×ESR (IRMS[A]：Ripple current of capacitor, ESR[Ω]：Equivalent series resistance.) 5)PD(IC)=Vin×ICC (ICC[A]：Circuit current.) ●Consideration on Permissible Dissipation and Heat Generation As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation must be carefully considered. For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered. Because the conduction losses are considered to play the leading role among other dissipation mentioned above including gate charge/discharge dissipation and switching dissipation. 2 ① Power dissipation:Pd [W] 4.0 4 layers (Copper foil area : 5505mm ) copper foil in each layers. θj-a=35.1℃/W ② 4 layers (Copper foil area : 10.29m2) copper foil in each layers. θj-a=56.6℃/W ③ 4 layers (Copper foil area : 10.29m 2) θj-a=178.6℃/W ④ IC only. θj-a=367.6℃/W ①3.56W 3.0 ②2.21W 2.0 1.0 2 P=IOUT ×RON RON=D×RONP+(1-D)RONN D：ON duty (=VOUT/VCC) RCOIL：DC resistance of coil RONP：ON resistance of P-channel MOS FET RONN：ON resistance of N-channel MOS FET IOUT：Output current ③0.70W ④0.34W 0 0 25 50 75 100 105 125 150 Ambient temperature:Ta [℃] Fig.27 Thermal derating curve (VQFN020V4040) If VCC=8V, VOUT=5V, RONP=0.15Ω, RONN=0.08Ω IOUT=2A, for example, D=VOUT/VCC=5/8=0.625 RON=0.625×0.15+(1-0.625)×0.08 =0.09375+0.03 =0.12375[Ω] 2 P=2 ×0.12375＝0.495[W] As RONP is greater than RONN in this IC, the dissipation increases as the ON duty becomes greater. consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed. www.rohm.com ©2012 ROHM Co., Ltd. All rights reserved. TSZ22111･15･001 11/19 With the TSZ02201-0J3J0AJ00180-1-2 02.MAR.2012 Rev.001 Datasheet BD9141MUV ●Selection of Components Externally Connected 1. Selection of inductor (L) The inductance significantly depends on output ripple current. As seen in the equation (1), the ripple current decreases as the inductor and/or switching frequency increases. IL ΔIL VCC ΔIL= IL (VCC-VOUT)×VOUT L×VCC×f [A]・・・(1) Appropriate ripple current at output should be 20% more or less of the maximum output current. VOUT L ΔIL=0.2×IOUTmax. [A]・・・(2) Co (VCC-VOUT)×VOUT L= Fig.28 Output ripple current ΔIL×VCC×f [H]・・・(3) (ΔIL: Output ripple current, and f: Switching frequency) ＊Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency. The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating. If VCC=8V, VOUT=5V, f=500kHz, ΔIL=0.3×2A=0.6A, for example,(BD9141MUV) (8-5)×5 L= 0.6×8×500k =6.25µ → 6.3[µH] ＊Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for better efficiency. 2. Selection of output capacitor (CO) VCC Output capacitor should be selected with the consideration on the stability region and the equivalent series resistance required to smooth ripple voltage. Output ripple voltage is determined by the equation (4)： VOUT L ESR ΔVOUT=ΔIL×ESR [V]・・・(4) Co (ΔIL: Output ripple current, ESR: Equivalent series resistance of output capacitor) Fig.29 Output capacitor www.rohm.com ©2012 ROHM Co., Ltd. All rights reserved. TSZ22111･15･001 *Rating of the capacitor should be determined allowing sufficient margin against output voltage. A 22µF to 100µF ceramic capacitor is recommended. Less ESR allows reduction in output ripple voltage. 12/19 TSZ02201-0J3J0AJ00180-1-2 02.MAR.2012 Rev.001 Datasheet BD9141MUV 3. Selection of input capacitor (Cin) VCC Input capacitor to select must be a low ESR capacitor of the capacitance sufficient to cope with high ripple current to prevent high transient voltage. The ripple current IRMS is given by the equation (5): Cin VOUT IRMS=IOUT× L √VOUT(VCC-VOUT) [A]・・・(5) VCC Co < Worst case > IRMS(max.) IOUT When Vcc is twice the VOUT, IRMS= 2 If VCC=8V, VOUT=5V, and IOUTmax.=2A, (BD9140MUV) Fig.30 Input capacitor IRMS=2× √ 5(8-5) 3 3.3 . 3 =0.97[ARMS] A low ESR 22µF/25V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency. 4. Determination of RITH, CITH that works as a phase compensator As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the power amplifier output with C and R as described below to cancel a pole at the power amplifier. fp(Min.) A Gain [dB] 0 fz(ESR) IOUTMin. Phase [deg] 1 2π×RO×CO 1 fz(ESR)= 2π×ESR×CO fp= fp(Max.) IOUTMax. Pole at power amplifier When the output current decreases, the load resistance Ro increases and the pole frequency lowers. 0 -90 fp(Min.)= 1 [Hz]←with lighter load 2π×ROMax.×CO fp(Max.)= 1 2π×ROMin.×CO Fig.31 Open loop gain characteristics A [Hz] ←with heavier load fz(Amp.) Zero at power amplifier Gain [dB] Increasing capacitance of the output capacitor lowers the pole 0 frequency while the zero frequency does not change. (This is because when the capacitance is doubled, the capacitor ESR 0 reduces to half.) Phase [deg] -90 fz(Amp.)= 1 2π×RITH×CITH Fig.32 Error amp phase compensation characteristics www.rohm.com ©2012 ROHM Co., Ltd. All rights reserved. TSZ22111･15･001 13/19 TSZ02201-0J3J0AJ00180-1-2 02.MAR.2012 Rev.001 Datasheet BD9141MUV VCC Cin EN VOUT L VCC,PVCC VOUT ITH VOUT SW ESR GND,PGND RO CO RITH CITH Fig.33 Typical application Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load resistance with CR zero correction by the error amplifier. fz(Amp.)= fp(Min.) 1 2π×RITH×CITH = 1 2π×ROMax.×CO 5. Determination of output voltage The output voltage VOUT is determined by the equation (6): VOUT=(R2/R1+1)×VADJ・・・(6) VADJ: Voltage at ADJ terminal (0.8V Typ.) With R1 and R2 adjusted, the output voltage may be determined as required. L Output SW Co R2 ADJ R1 Adjustable output voltage range : 2.5V to 6.0V Fig.34 Determination of output voltage Use 1 kΩ to 100 kΩ resistor for R1. if you can use the resistance more than 100kΩor they have a big range between the setting value of output voltage and input voltage. 8 7.5 The minimum input voltage depends on the setting output voltage. Basically, it is recommended to use in the condition : VCCmin = VOUT+1.3V. It is shown the necessary output current value at the minimum input voltage. (DCR of inductor : 0.1Ω)See Fig.35. This data is the characteristic value, so it doesn’t guarantee the operation range. INPUT VOLTAGE : VCC[V] Vo=6.0V 7 6.5 Vo=5.0V 6 Vo=4.0V 5.5 5 6.Selection of the reference voltage capacitor (CVREG) VREG voltage is the reference voltage created by Input voltage (Vcc Voltage). CVREG capacitor should be selected 0.1µF or more. Vo=3.3V 4.5 0 0.5 1 1.5 2 OUTPUT CURRENT : IOUT[A] Fig.35 minimum input voltage in each output voltage www.rohm.com ©2012 ROHM Co., Ltd. All rights reserved. TSZ22111･15･001 14/19 TSZ02201-0J3J0AJ00180-1-2 02.MAR.2012 Rev.001 Datasheet BD9141MUV ●Cautions on PC Board Layout VCC R2 EN ADJ VCC R1 EN PVCC VREG CVREG RITH ③ CITH ① L SW ITH GND PGND VOUT CIN ② Co GND Fig.36 Layout diagram ① For the sections drawn with heavy line, use thick conductor pattern as short as possible. ② Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the pin PGND. ③ Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring. ④ The Non connection pin must be left open or connected to GND. ※VQFN020V4040 (BD9141MUV) has thermal FIN on the reverse of the package. The package thermal performance may be enhanced by bonding the FIN to GND plane which take a large area of PCB. ●Recommended Components Lists on Above Application Symbol Value Manufacturer Series Coil 4.7µH TDK RLF7030T-4R7M3R4 CIN Ceramic capacitor 22µF kyocera CM32X5R226M25A CO Ceramic capacitor 22µF kyocera CM32X5R226M10A CVREG Ceramic capacitor 0.1µF murata GRM188B31H104KA92 CITH Ceramic capacitor RITH Resistance L Part Vo=3.3V 1000pF murata GRM1882C1H102JA01 Vo=5V 1000pF murata GRM1882C1H102JA01 Vo=3.3V Vo=5V 20kΩ 47kΩ Rohm Rohm MCR03 Series MCR03 Series ※The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit characteristics should be checked on your application carefully before use. Be sure to allow sufficient margins to accommodate variations between external devices and this IC when employing the depicted circuit with other circuit constants modified. Both static and transient characteristics should be considered in establishing these margins. When switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and PVCC pins, and a schottky barrier diode established between the SW and PGND pins. www.rohm.com ©2012 ROHM Co., Ltd. All rights reserved. TSZ22111･15･001 15/19 TSZ02201-0J3J0AJ00180-1-2 02.MAR.2012 Rev.001 Datasheet BD9141MUV ●I/O Equivalence Circuit ・EN pin PVCC ・SW pin PVCC PVCC EN SW ・ADJ pin ・ITH pin VCC ADJ ITH ・VREG pin VCC VCC VREG Fig.37 I/O equivalence circuit www.rohm.com ©2012 ROHM Co., Ltd. All rights reserved. TSZ22111･15･001 16/19 TSZ02201-0J3J0AJ00180-1-2 02.MAR.2012 Rev.001 Datasheet BD9141MUV ●Operational Notes 1. Absolute Maximum Ratings While utmost care is taken to quality control of this product, any application that may exceed some of the absolute maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken, short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses. 2. Electrical potential at GND GND must be designed to have the lowest electrical potential In any operating conditions. 3. Short-circuiting between terminals, and mismounting When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and power supply or GND may also cause breakdown. 4. Operation in Strong electromagnetic field Be noted that using the IC in the strong electromagnetic radiation can cause operation failures. 5. Thermal shutdown protection circuit Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be used thereafter for any operation originally intended. 6. Inspection with the IC set to a pc board If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the inspection process, be sure to turn OFF the power supply before it is connected and removed. 7. Input to IC terminals + This is a monolithic IC with P isolation between P-substrate and each element as illustrated below. This P-layer and the N-layer of each element form a P-N junction, and various parasitic element are formed. If a resistor is joined to a transistor terminal as shown in Fig 38. ○P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or GND>Terminal B (at transistor side); and ○if GND>Terminal B (at NPN transistor side), a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode. The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits, and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in activation of parasitic elements. Resistor Transistor (NPN) Pin A Pin B C B Pin B E Pin A N N P+ N P+ P N Parasitic element P+ P substrate Parasitic element GND B N P+ P N P substrate Parasitic element GND GND C E Parasitic element Other adjacent elements GND Fig.38 Simplified structure of monorisic IC 8. Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. 9. Selection of inductor It is recommended to use an inductor with a series resistance element (DCR) 0.1Ω or less. When using an inductor over 0.1Ω, be careful to ensure adequate margins for variation between external devices and this IC, including transient as well as static characteristics. Furthermore, in any case, it is recommended to start up the output with EN after supply voltage is within operation range Status of this document The Japanese version of this document is formal specification. A customer may use this translation version only for a reference to help reading the formal version. If there are any differences in translation version of this document formal version takes priority. www.rohm.com ©2012 ROHM Co., Ltd. All rights reserved. TSZ22111･15･001 17/19 TSZ02201-0J3J0AJ00180-1-2 02.MAR.2012 Rev.001 Datasheet BD9141MUV ●Ordering Information B D 9 1 4 1 M U V Package MUV: VQFN020V4040 Part Number E2 Packaging and forming specification E2: Embossed tape and reel ●Physical Dimension Tape and Reel Information ●Marking Diagram VQFN020V4040 (TOP VIEW) Part Number Marking D 9 1 4 1 LOT Number 1PIN MARK www.rohm.com ©2012 ROHM Co., Ltd. All rights reserved. TSZ22111･15･001 18/19 TSZ02201-0J3J0AJ00180-1-2 02.MAR.2012 Rev.001 Datasheet BD9141MUV ●Revision History Date Revision 17.Jan.2012 001 Changes New Release www.rohm.com ©2012 ROHM Co., Ltd. All rights reserved. TSZ22111･15･001 19/19 TSZ02201-0J3J0AJ00180-1-2 02.MAR.2012 Rev.001 Datasheet Notice ●Precaution for circuit design 1) The products are designed and produced for application in ordinary electronic equipment (AV equipment, OA equipment, telecommunication equipment, home appliances, amusement equipment, etc.). If the products are to be used in devices requiring extremely high reliability (medical equipment, transport equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car accessories, safety devices, etc.) and whose malfunction or operational error may endanger human life and sufficient fail-safe measures, please consult with the ROHM sales staff in advance. If product malfunctions may result in serious damage, including that to human life, sufficient fail-safe measures must be taken, including the following: [a] Installation of protection circuits or other protective devices to improve system safety [b] Installation of redundant circuits in the case of single-circuit failure 2) The products are designed for use in a standard environment and not in any special environments. Application of the products in a special environment can deteriorate product performance. Accordingly, verification and confirmation of product performance, prior to use, is recommended if used under the following conditions: [a] Use in various types of liquid, including water, oils, chemicals, and organic solvents [b] Use outdoors where the products are exposed to direct sunlight, or in dusty places [c] Use in places where the products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [d] Use in places where the products are exposed to static electricity or electromagnetic waves [e] Use in proximity to heat-producing components, plastic cords, or other flammable items [f] Use involving sealing or coating the products with resin or other coating materials [g] Use involving unclean solder or use of water or water-soluble cleaning agents for cleaning after soldering [h] Use of the products in places subject to dew condensation 3) The products are not radiation resistant. 4) Verification and confirmation of performance characteristics of products, after on-board mounting, is advised. 5) In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse) is applied, confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect product performance and reliability. 6) De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual ambient temperature. 7) Confirm that operation temperature is within the specified range described in product specification. 8) Failure induced under deviant condition from what defined in the product specification cannot be guaranteed. ●Precaution for Mounting / Circuit board design 1) When a highly active halogenous (chlorine, bromine, etc.) flux is used, the remainder of flux may negatively affect product performance and reliability. 2) In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the Company in advance. Regarding Precaution for Mounting / Circuit board design, please specially refer to ROHM Mounting specification ●Precautions Regarding Application Examples and External Circuits 1) If change is made to the constant of an external circuit, allow a sufficient margin due to variations of the characteristics of the products and external components, including transient characteristics, as well as static characteristics. 2) The application examples, their constants, and other types of information contained herein are applicable only when the products are used in accordance with standard methods. Therefore, if mass production is intended, sufficient consideration to external conditions must be made. Notice - Rev.001 Datasheet ●Precaution for Electrostatic This product is Electrostatic sensitive product, which may be damaged due to Electrostatic discharge. Please take proper caution during manufacturing and storing so that voltage exceeding Product maximum rating won't be applied to products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron, isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control). ●Precaution for Storage / Transportation 1) Product performance and soldered connections may deteriorate if the products are stored in the following places: [a] Where the products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [b] Where the temperature or humidity exceeds those recommended by the Company [c] Storage in direct sunshine or condensation [d] Storage in high Electrostatic 2) Even under ROHM recommended storage condition, solderability of products out of recommended storage time period may be degraded. It is strongly recommended to confirm solderability before using products of which storage time is exceeding recommended storage time period . 3) Store / transport cartons in the correct direction, which is indicated on a carton as a symbol. Otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4) Use products within the specified time after opening a dry bag. ●Precaution for product label QR code printed on ROHM product label is only for internal use, and please do not use at customer site. It might contain a internal part number that is inconsistent with an product part number. ●Precaution for disposition When disposing products please dispose them properly with a industry waste company. ●Precaution for Foreign exchange and Foreign trade act Since concerned goods might be fallen under controlled goods prescribed by Foreign exchange and Foreign trade act, please consult with ROHM in case of export. ●Prohibitions Regarding Industrial Property 1) Information and data on products, including application examples, contained in these specifications are simply for reference; the Company does not guarantee any industrial property rights, intellectual property rights, or any other rights of a third party regarding this information or data. Accordingly, the Company does not bear any responsibility for: [a] infringement of the intellectual property rights of a third party [b] any problems incurred by the use of the products listed herein. 2) The Company prohibits the purchaser of its products to exercise or use the intellectual property rights, industrial property rights, or any other rights that either belong to or are controlled by the Company, other than the right to use, sell, or dispose of the products. Notice - Rev.001