TS5A3159A 1-Ohm SPDT Analog Switch (Rev. D)

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TS5A3159A
SCDS200D – JUNE 2005 – REVISED JUNE 2015
TS5A3159A 1-Ω SPDT Analog Switch
5-V and 3.3-V Single-Channel 2:1 Multiplexer and Demultiplexer
1 Features
3 Description
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The TS5A3159A device is a single-pole double-throw
(SPDT) analog switch that is designed to operate
from 1.65 V to 5.5 V. The device offers low on-state
resistance and excellent ON-state resistance
matching with the break-before-make feature, to
prevent signal distortion during the transferring of a
signal from one channel to another. The device has
an excellent total harmonic distortion (THD)
performance and consumes very low power. These
features make this device suitable for portable audio
applications.
1
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Specified Break-Before-Make Switching
Isolation in Power-Down Mode, V+ = 0
Terminal Compatible With TS5A3159 Device
Low ON-State Resistance (1 Ω)
Control Inputs are 5.5-V Tolerant
Low Charge Injection
Excellent On-State Resistance Matching
Low Total Harmonic Distortion (THD)
1.65-V to 5.5-V Single-Supply Operation
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Performance Tested Per JESD
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TS5A3159ADBVR
SOT-23 (6)
2.90 mm × 1.60 mm
TS5A3159ADCKR
SC70 (6)
2.00 mm × 1.25 mm
TS5A3159AYZPR
DSBGA (6)
1.41 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
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Cell Phones
PDAs
Portable Instrumentation
Audio and Video Signal Routing
Low-Voltage Data Acquisition Systems
Communication Circuits
Modems
Hard Drives
Computer Peripherals
Wireless Terminals and Peripherals
Block Diagram
IN
COM
NC
NO
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS5A3159A
SCDS200D – JUNE 2005 – REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
8
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics for 5-V Supply .................. 5
Electrical Characteristics for 3.3-V Supply ............... 6
Electrical Characteristics for 2.5-V Supply ............... 8
Electrical Characteristics for 1.8-V Supply ............... 9
Typical Characteristics ............................................ 11
Parameter Measurement Information ................ 14
Detailed Description ............................................ 18
8.1 Overview ................................................................. 18
8.2 Functional Block Diagram ....................................... 18
8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 18
9
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Application ................................................. 19
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 Device and Documentation Support ................. 21
12.1
12.2
12.3
12.4
12.5
12.6
Device Support ....................................................
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
22
22
22
22
22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (May 2010) to Revision D
•
2
Page
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
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SCDS200D – JUNE 2005 – REVISED JUNE 2015
5 Pin Configuration and Functions
DBV or DCK Packages
6-Pin SOT-23 or SC-70
Top View
NO
1
YZP Packages
6-Pin DSBGA
Bottom View
6
IN
NC
3 4
COM
GND
2 5
V+
NO
1 6
IN
GND
2
5
V+
NC
3
4
COM
NO – Normally open
NC – Normally closed
Pin Functions
PIN
I/O
DESCRIPTION
NAME
SOT-23,
SC-70
DSBGA
COM
4
C2
I/O
Normally open switch port
GND
2
B1
—
Ground
IN
6
A2
I/O
Normally closed switch port
NC
3
C1
I/O
Common switch port
NO
1
A1
—
Power supply
V+
5
B2
I
Switch select. High = COM connected to NO; Low = COM connected to NC.
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SCDS200D – JUNE 2005 – REVISED JUNE 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
V+
Supply voltage (3)
–0.5
6.5
V
VNO,
VNC,
VCOM
Analog voltage (3) (4) (5)
–0.5
V+ + 0.5
V
IK
Analog port diode current
INO,
INC,
ICOM
ON-state switch current
VNC, VNO, VCOM < 0
ON-state peak switch current
(3) (4)
Digital input voltage
IIK
Digital input clamp current
I+
Continuous current through V+
IGND
Continuous current through GND
(1)
(2)
(3)
(4)
(5)
(6)
(7)
VNO, VNC, VCOM = 0 to V+
(6)
VI
VI < 0
mA
200
mA
–400
400
mA
–0.5
6.5
–50
V
mA
–100
Absolute maximum operating temperature (7)
TA
–50
–200
100
mA
100
mA
DBV or DCK package
150
YZP package
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
All voltages are with respect to ground, unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 5.5 V maximum.
Pulse at 1-ms duration <10% duty cycle.
The lifetime of the device will be reduced if the device operates continually at this temperature.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VI/O
Switch input/output voltage
V+
Supply voltage
VI
Control input voltage
TA
Operating temperature
MAX
UNIT
0
V+
V
1.65
5.5
V
0
5.5
V
–40
85
°C
6.4 Thermal Information
TS5A3159A
THERMAL METRIC
RθJA
(1)
4
(1)
Junction-to-ambient thermal resistance
DBV (SOT-23)
DCK (SC-70)
YZP (DSBGA)
6 PINS
6 PINS
8 PINS
165
259
123
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SCDS200D – JUNE 2005 – REVISED JUNE 2015
6.5 Electrical Characteristics for 5-V Supply
V+ = 4.5 V to 5.5 V, T = –40°C to 85°C (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
TA
V+
MIN
TYP
MAX
0.8
1.1
UNIT
ANALOG SWITCH
VCOM, VNO, VNC
Analog signal
0
rpeak
Peak ON resistance
0 ≤ (VNO or VNC) ≤ V+,
ICOM = –100 mA,
Switch on,
see Figure 14
25°C
ron
ON-state resistance
VNO or VNC = 2.5 V,
ICOM = –100 mA,
Switch on,
see Figure 14
25°C
Δron
ON-state resistance
match between channels
VNO or VNC = 2.5 V,
ICOM = –100 mA,
Switch on,
see Figure 14
25°C
0 ≤ (VNO or VNC) ≤ V+,
ICOM = –100 mA,
Switch on,
see Figure 14
ron(flat)
ON-state resistance
flatness
INC(OFF),
INO(OFF)
NC, NO
OFF leakage current
INC(PWROFF),
INO(PWROFF)
VNO or VNC = 1 V, 1.5 V, 2.5 V,
ICOM = –100 mA,
Switch on,
see Figure 14
VNC or VNO = 1 V, VCOM = 1 V
to 4.5 V, or
VNC or VNO = 4.5 V, VCOM = 1 V
to 4.5 V,
Switch off,
see Figure 15
VNC or VNO = 0 to 5.5 V,
VCOM = 5.5 V to 0,
Switch off,
see Figure 15
Full
Full
Full
4.5 V
NC, NO
ON leakage current
VNC or VNO = 1 V,
VCOM = Open, or VNC or
VNO = 4.5 V, VCOM = Open,
Switch on,
see Figure 16
ICOM(PWROFF)
COM
OFF leakage current
VNC or VNO = 0 to 5.5 V,
VCOM = 5.5 V to 0,
Switch off,
see Figure 15
ICOM(ON)
COM
ON leakage current
VNC or VNO = Open,
VCOM = 1 V, or VNC or
VNO = Open, VCOM = 4.5 V,
Switch on,
see Figure 16
0.7
4.5 V
0.05
25°C
Full
25°
Full
0.1
Ω
Ω
Ω
0.25
Ω
0.25
–20
5.5 V
0V
2
–100
–1
0V
0.2
–20
2
0.1
–20
1
20
2
nA
μA
20
100
–20
5.5 V
1
20
–100
–1
20
100
–20
5.5 V
25°C
Full
V
0.15
4.5 V
25°C
Full
0.1
0.1
Full
Full
0.9
1.1
4.5 V
25°C
INC(ON),
INO(ON)
1.5
25°C
25°C
V+
nA
μA
20
–100
100
nA
DIGITAL INPUT (IN)
VIH
Input logic high
Full
2.4
5.5
VIL
Input logic low
Full
0
0.8
IIH, IIL
Input leakage current
VI = 5.5 V or 0
Turnon time
VCOM = V+,
RL = 50 Ω,
CL = 35 pF,
see Figure 18
Turnoff time
VCOM = V+,
RL = 50 Ω,
CL = 35 pF,
see Figure 18
tBBM
Break-before-make time
VNC = VNO = V+,
RL = 50 Ω,
CL = 35 pF,
see Figure 19
QC
Charge injection
VGEN = 0,
RGEN = 0,
CNC(OFF),
CNO(OFF)
NC, NO
OFF capacitance
CNC(ON),
CNO(ON)
25°C
5.5 V
Full
–2
2
100
100
V
nA
DYNAMIC
tON
tOFF
25°C
5V
1
Full
4.5 V
to 5.5
V
1
25°C
5V
1
Full
4.5 V
to 5.5
V
1
12
30
35
5
ns
20
30
ns
25°C
5V
Full
4.5 V
to 5.5
V
CL = 1 nF,
see Figure 23
25°C
5V
–20
pC
VNC or VNO = V+ or GND,
Switch off,
see Figure 17
25°C
5V
18
pF
NC, NO
ON capacitance
VNC or VNO = V+ or GND,
Switch on,
see Figure 17
25°C
5V
55
pF
CCOM(ON)
COM
ON capacitance
VCOM = V+ or GND,
Switch on,
see Figure 17
25°C
5V
55
pF
CI
Digital input capacitance
VI = V+ or GND,
See Figure 17
25°C
5V
2
pF
RL = 50 Ω,
Switch on,
see Figure 20
25°C
5V
100
BW
(1)
Bandwidth
6
1
20
ns
MHz
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
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Electrical Characteristics for 5-V Supply (continued)
V+ = 4.5 V to 5.5 V, T = –40°C to 85°C (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
TA
V+
Switch off,
see Figure 21
MIN
TYP
25°C
5V
–64
dB
dB
OISO
Off isolation
RL = 50 Ω,
f = 1 MHz,
XTALK
Crosstalk
RL = 50 Ω,
f = 1 MHz,
Switch on,
see Figure 22
25°C
5V
–64
THD
Total harmonic distortion
RL = 600 Ω,
CL = 50 pF,
f = 200 Hz to 20 kHz,
see Figure 24
25°C
5V
0.004%
Positive supply current
VI = V+ or GND,
Switch on or off
MAX
UNIT
SUPPLY
I+
25°C
Full
10
5.5 V
50
nA
500
6.6 Electrical Characteristics for 3.3-V Supply
V+ = 3 V to 3.6 V, TA = –40°C to 85°C (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
TA
V+
MIN
TYP
MAX
UNIT
ANALOG SWITCH
VCOM, VNO,
VNC
Analog signal range
rpeak
Peak ON resistance
0 ≤ (VNO or VNC) ≤ V+,
ICOM = –100 mA,
Switch on,
See Figure 14
25°C
ron
ON-state resistance
VNO or VNC = 2 V,
ICOM = –100 mA,
Switch on,
See Figure 14
25°C
Δron
ON-state resistance match
between channels
VNO or VNC = 2 V, 0.8 V,
ICOM = –100 mA,
Switch on,
See Figure 14
25°C
0 ≤ (VNO or VNC) ≤ V+,
ICOM = –100 mA,
Switch on,
See Figure 14
ron(flat)
ON-state resistance
flatness
INC(OFF),
INO(OFF)
NC, NO
off leakage current
INC(PWROFF),
INO(PWROFF)
0
VNO or VNC = 2 V, 0.8 V,
ICOM = –100 mA,
Switch on,
See Figure 14
VNC or VNO = 1 V, VCOM = 1 V
to 3 V, or
VNC or VNO = 3 V, VCOM = 1 V
to 3 V,
Switch off,
See Figure 15
VNC or VNO = 0 to 3.6 V,
VCOM = 3.6 V to 0,
Switch off,
See Figure 15
Full
Full
Full
NC, NO
on leakage current
VNC or VNO = 1 V, VCOM =
Open,
or VNC or VNO = 3 V, VCOM =
Open,
Switch on,
See Figure 16
ICOM(PWROFF)
COM
off leakage current
VNC or VNO = 3.6 V to 0,
VCOM = 0 to 3.6 V,
Switch off,
See Figure 15
ICOM(ON)
COM
on leakage current
VNC or VNO = Open,
VCOM = 1 V, or VNC or
VNO = Open, VCOM = 3 V,
Switch on,
See Figure 16
1.3
3V
1.2
0.1
3V
25°C
Full
25°
Full
0.15
Ω
Ω
Ω
0.3
Ω
0.3
–20
3.6 V
0V
0V
–1
0.2
1
15
2
–20
–1
20
50
–15
0.2
1
15
2
nA
μA
10
20
–15
–10
3.6 V
2
–50
–10
3.6 V
25°C
Full
V
0.2
3V
25°C
Full
0.15
0.15
Full
Full
1.5
1.7
25°C
25°C
1.6
2
3V
25°C
INC(ON),
INO(ON)
V+
nA
μA
10
–20
20
nA
DIGITAL INPUT (IN)
VIH
Input logic high
Full
2.4
5.5
VIL
Input logic low
Full
0
0.8
IIH, IIL
Input leakage current
VI = 5.5 V or 0
tON
Turnon time
VCOM = V+,
RL = 50 Ω,
CL = 35 pF,
See Figure 18
tOFF
Turnoff time
VCOM = V+,
RL = 50 Ω,
CL = 35 pF,
See Figure 18
25°C
Full
3.6 V
–2
2
–100
100
V
nA
DYNAMIC
(1)
6
25°C
3.3 V
5
Full
3 V to
3.6 V
3
25°C
3.3 V
1
Full
3 V to
3.6 V
1
16
35
50
9
ns
20
30
ns
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
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Electrical Characteristics for 3.3-V Supply (continued)
V+ = 3 V to 3.6 V, TA = –40°C to 85°C (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
TA
V+
25°C
3.3 V
Full
3 V to
3.6 V
MIN
TYP
MAX
UNIT
9
tBBM
Break-before-make time
VNC = VNO = V+,
RL = 50 Ω,
CL = 35 pF,
See Figure 19
QC
Charge injection
VGEN = 0,
RGEN = 0,
CL = 1 nF,
See Figure 23
25°C
3.3 V
–11
pC
CNC(OFF),
CNO(OFF)
NC, NO
OFF capacitance
VNC or VNO = V+ or GND,
Switch off,
See Figure 17
25°C
3.3 V
18
pF
CNC(ON),
CNO(ON)
NC, NO
ON capacitance
VNC or VNO = V+ or GND,
Switch on,
See Figure 17
25°C
3.3 V
55
pF
CCOM(ON)
COM
ON capacitance
VCOM = V+ or GND,
Switch on,
See Figure 17
25°C
3.3 V
55
pF
CI
Digital input capacitance
VI = V+ or GND,
See Figure 17
25°C
3.3 V
2
pF
25°C
3.3 V
100
MHz
1
40
ns
BW
Bandwidth
RL = 50 Ω,
Switch on,
See Figure 20
OISO
Off isolation
RL = 50 Ω,
f = 1 MHz,
Switch off,
See Figure 21
25°C
3.3 V
–64
dB
XTALK
Crosstalk
RL = 50 Ω,
f = 1 MHz,
Switch on,
See Figure 22
25°C
3.3 V
–64
dB
THD
Total harmonic distortion
RL = 600 Ω,
CL = 50 pF,
f = 20 Hz to 20 kHz,
See Figure 24
25°C
3.3 V
0.01%
Positive supply current
VI = V+ or GND,
Switch on or off
SUPPLY
I+
25°C
Full
3.6 V
10
25
100
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6.7 Electrical Characteristics for 2.5-V Supply
V+ = 2.3 V to 2.7, TA = –40°C to 85°C (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
TA
V+
MIN
TYP
MAX
1.8
2.5
UNIT
ANALOG SWITCH
VCOM, VNO, VNC
Analog signal range
0
rpeak
Peak ON resistance
0 ≤ (VNO or VNC) ≤ V+,
ICOM = –8 mA,
Switch on,
See Figure 14
25°C
ron
ON-state resistance
VNO or VNC = 1.8 V,
ICOM = –8 mA,
Switch on,
See Figure 14
25°C
Δron
ON-state resistance match
between channels
VNO or VNC = 1.8 V,
ICOM = –8 mA,
Switch on,
See Figure 14
25°C
0 ≤ (VNO or VNC) ≤ V+,
ICOM = –8 mA,
Switch on,
See Figure 14
ron(flat)
ON-state resistance flatness
INC(OFF),
INO(OFF)
NC, NO
OFF leakage current
INC(PWROFF),
INO(PWROFF)
VNO or VNC = 0.8 V, 1.8 V,
ICOM = –8 mA,
Switch on,
See Figure 14
VNC or VNO = 0.5 V,
VCOM = 0.5 V to 2.3 V, or
VNC or VNO = 2.3 V, VCOM = 0.5 V
to 2.3 V,
Switch off,
See Figure 15
VNC or VNO = 0 to 3.6 V,
VCOM = 3.6 V to 0,
Switch off,
See Figure 15
Full
Full
Full
2.3 V
NC, NO
ON leakage current
VNC or VNO = 0.5 V, VCOM = Open,
or
VNC or VNO = 2.2 V, VCOM = Open,
Switch on,
See Figure 16
ICOM(PWROFF)
COM
OFF leakage current
VNC or VNO = 2.7 V to 0,
VCOM = 0 to 2.7 V,
Switch off,
See Figure 15
ICOM(ON)
COM
ON leakage current
VNC or VNO = Open, VCOM = 0.5 V,
or
VNC or VNO = Open, VCOM = 2.2 V,
Switch on,
See Figure 16
2.7
1.5
2.3 V
0.15
25°C
Full
25°
Full
2.7 V
0V
0.6
1
2
20
–50
50
–1
0.1
–10
0V
2
–20
Ω
Ω
Ω
–1
0.1
–10
10
20
2
nA
μA
10
20
–10
2.7 V
1
10
–10
2.7 V
25°C
Full
Ω
1
–20
25°C
Full
V
0.6
2.3 V
Full
Full
0.2
0.2
25°C
25°C
2
2.4
2.3 V
25°C
INC(ON),
INO(ON)
V+
nA
μA
10
–20
20
nA
DIGITAL INPUT (IN)
VIH
Input logic high
Full
1.8
5.5
VIL
Input logic low
Full
0
0.6
IIH, IIL
Input leakage current
VI = 5.5 V or 0
Turnon time
VCOM = V+,
RL = 50 Ω,
CL = 35 pF,
See Figure 18
Turnoff time
VCOM = V+,
RL = 50 Ω,
CL = 35 pF,
See Figure 18
tBBM
Break-before-make time
VNC = VNO = V+,
RL = 50 Ω,
CL = 35 pF,
See Figure 19
QC
Charge injection
VGEN = 0,
RGEN = 0,
CNC(OFF),
CNO(OFF)
NC, NO
OFF capacitance
CNC(ON),
CNO(ON)
25°C
Full
2.7 V
–2
2
20
20
V
nA
DYNAMIC
25°C
2.5 V
5
Full
2.3 V
to
2.7 V
5
25°C
2.5 V
2
Full
2.3 V
to
2.7 V
2
25°C
2.5 V
2
Full
2.3 V
to
2.7 V
2
CL = 1 nF,
See Figure 23
25°C
2.5 V
–7
pC
VNC or VNO = V+ or GND,
Switch off,
See Figure 17
25°C
2.5 V
18
pF
NC, NO
ON capacitance
VNC or VNO = V+ or GND,
Switch on,
See Figure 17
25°C
2.5 V
55
pF
CCOM(ON)
COM
ON capacitance
VCOM = V+ or GND,
Switch on,
See Figure 17
25°C
2.5 V
55
pF
CI
Digital input capacitance
VI = V+ or GND,
See Figure 17
25°C
2.5 V
2
pF
RL = 50 Ω,
Switch on,
See Figure 20
25°C
2.5 V
100
tON
tOFF
BW
(1)
8
Bandwidth
22
40
50
6
35
50
13
ns
ns
35
45
ns
MHz
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
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Electrical Characteristics for 2.5-V Supply (continued)
V+ = 2.3 V to 2.7, TA = –40°C to 85°C (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
TA
V+
Switch off,
See Figure 21
MIN
TYP
25°C
2.5 V
–64
dB
dB
OISO
Off isolation
RL = 50 Ω,
f = 1 MHz,
XTALK
Crosstalk
RL = 50 Ω,
f = 1 MHz,
Switch on,
See Figure 22
25°C
2.5 V
–64
THD
Total harmonic distortion
RL = 600 Ω,
CL = 50 pF,
f = 20 Hz to 20
kHz,
See Figure 24
25°C
2.5 V
0.02%
Positive supply current
VI = V+ or GND,
Switch on or off
MAX
UNIT
SUPPLY
I+
25°C
Full
10
2.7 V
20
50
nA
6.8 Electrical Characteristics for 1.8-V Supply
V+ = 1.65 V to 1.95 V, TA = –40°C to 85°C (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
TA
V+
MIN
TYP
MAX
UNIT
ANALOG SWITCH
VCOM, VNO,
VNC
Analog signal range
rpeak
Peak ON resistance
0 ≤ (VNO or VNC) ≤ V+,
ICOM = –2 mA,
Switch on,
See Figure 14
25°C
ron
ON-state resistance
VNO or VNC = 1.5 V,
ICOM = –2 mA,
Switch on,
See Figure 14
25°C
Δron
ON-state resistance match
between channels
VNO or VNC = 1.5 V,
ICOM = –2 mA,
Switch on,
See Figure 14
25°C
0 ≤ (VNO or VNC) ≤ V+,
ICOM = –8 mA,
Switch on,
See Figure 14
ron(flat)
ON-state resistance
flatness
VNO or VNC = 0.6 V, 1.5 V,
ICOM = –2 mA,
Switch on,
See Figure 14
INC(OFF),
INO(OFF)
NC, NO
OFF leakage current
INC(PWROFF)
INO(PWROFF)
0
VNC or VNO = 0.3 V,
VCOM = 0.3 V to 1.65 V,
or
VNC or VNO = 1.65 V,
VCOM = 0.3 V to 1.65 V,
Switch off,
See Figure 15
VNC or VNO = 0 to 1.95 V,
VCOM = 1.95 V to 0,
Switch off,
See Figure 15
Full
Full
Full
1.65
V
5
1.65
V
2
1.65
V
0.15
NC, NO
ON leakage current
VNC or VNO = 0.3 V, VCOM = Open,
or
VNC or VNO = 1.65 V, VCOM = Open,
Switch on,
See Figure 16
ICOM(PWROFF)
COM
OFF leakage current
VNC or VNO = 1.95 V to 0,
VCOM = 0 to 1.95 V,
Switch off,
See Figure 15
ICOM(ON)
COM
ON leakage current
VNC or VNO = Open, VCOM = 0.3 V,
or
VNC or VNO = Open, VCOM = 1.65 V,
Switch on,
See Figure 16
15
25°C
2.5
3.5
0.4
0.4
25°C
V
Ω
Ω
Ω
5
1.65
V
Ω
4.5
Full
25°C
INC(ON),
INO(ON)
V+
Full
25°C
Full
25°C
Full
25°
Full
25°C
Full
–5
1.95
V
0V
1.95
V
0V
1.95
V
2
5
nA
–20
–1
20
0.1
–5
5
–5
2
–20
–1
1
5
20
0.1
–5
7
5
–5
2
μA
nA
μA
5
–20
20
nA
DIGITAL INPUT (IN)
VIH
Input logic high
Full
1.5
5.5
VIL
Input logic low
Full
0
0.6
IIH, IIL
Input leakage current
VI = 5.5 V or 0
Turnon time
VCOM = V+,
RL = 50 Ω,
25°C
1.95
V
–2
2
Full
20
20
25°C
1.8 V
10
Full
1.65
V to
1.95
V
10
V
nA
DYNAMIC
tON
(1)
CL = 35 pF,
See Figure 18
35
70
75
ns
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
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Electrical Characteristics for 1.8-V Supply (continued)
V+ = 1.65 V to 1.95 V, TA = –40°C to 85°C (unless otherwise noted)(1)
PARAMETER
tOFF
Turnoff time
TEST CONDITIONS
VCOM = V+,
RL = 50 Ω,
CL = 35 pF,
See Figure 18
TA
V+
MIN
TYP
MAX
25°C
1.8 V
2
15
40
Full
1.65
V to
1.95
V
2
25°C
1.8 V
Full
1.65
V to
1.95
V
50
UNIT
ns
22
tBBM
Break-before-make time
VNC = VNO = V+,
RL = 50 Ω,
CL = 35 pF,
See Figure 19
QC
Charge injection
VGEN = 0,
RGEN = 0,
CL = 1 nF,
See Figure 23
25°C
1.8 V
–4
pC
CNC(OFF),
CNO(OFF)
NC, NO
OFF capacitance
VNC or VNO = V+ or GND,
Switch off,
See Figure 17
25°C
1.8 V
18
pF
CNC(ON),
CNO(ON)
NC, NO
ON capacitance
VNC or VNO = V+ or GND,
Switch on,
See Figure 17
25°C
1.8 V
55
pF
CCOM(ON)
COM
ON capacitance
VCOM = V+ or GND,
Switch on,
See Figure 17
25°C
1.8 V
55
pF
CI
Digital input capacitance
VI = V+ or GND,
See Figure 17
25°C
1.8 V
2
pF
25°C
1.8 V
105
MHz
2
70
ns
BW
Bandwidth
RL = 50 Ω,
Switch on,
See Figure 20
OISO
Off isolation
RL = 50 Ω,
f = 1 MHz,
Switch off,
See Figure 21
25°C
1.8 V
64
dB
XTALK
Crosstalk
RL = 50 Ω,
f = 1 MHz,
Switch on,
See Figure 22
25°C
1.8 V
64
dB
THD
Total harmonic distortion
RL = 600 Ω,
CL = 50 pF,
f = 20 Hz to 20 kHz,
See Figure 24
25°C
1.8 V
0.06%
I+
Positive supply current
VI = V+ or GND,
Switch on or off
25°C
1.95
V
5
10
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Full
15
50
μA
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3
3.50
2.5
3.00
V+ = 1.8 V
V+ = 2.5 V
V+ = 3.3 V
V+ = 5 V
2.50
2
ron (Ω)
Threshold Voltage – V
6.9 Typical Characteristics
1.5
1
2.00
1.50
1.00
0.5
0.50
Vt+
Vt–
0.00
0
2.3
2.7
3
3.6
4.5
0.0
5.5
0.5
1.0
Figure 1. Logic Threshold vs Power Supply
2.0
Figure 2. ron vs VCOM
1.0
TA = 85°C
TA = 25°C
TA = −40°C
1.5
1.3
0.9
0.8
1.1
0.7
ron (Ω)
ron (Ω)
1.5
VCOM (V)
Power Supply – V
0.9
0.7
0.6
0.5
0.4
0.5
TA = 85°C
TA = 25°C
TA = −40°C
0.3
0.3
0.2
0.1
0.1
0
1
2
3
4
0
1
2
3
VCOM (V)
4
5
6
VCOM (V)
Figure 3. ron vs VCOM (V+ = 3.3 V)
Figure 4. ron vs VCOM (V+ = 5 V)
3500
20
COM (pwroff)
COM (on)
3000
NO/NC (off)
−20
Leakage (nA)
Leakage (nA)
2500
0
2000
1500
1000
500
NO/NC (on)
−40
−60
−40
−20
0
20
40
60
NO/NC (pwroff)
0
80
100
−500
−60
−40
−20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
Figure 5. Leakage Current vs Temperature
(V+ = 3.3 V)
Figure 6. Leakage Current vs Temperature
(V+ = 5 V)
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45
70
60
50
40
30
20
10
0
−10
−20
−30
40
V+ = 5 V
V+ = 3 V
tON
35
30
tON/tOFF (ns)
Charge Injection (pC)
Typical Characteristics (continued)
25
20
tOFF
15
10
5
0
0
1
2
3
4
5
0
6
1
Bias Voltage (V)
3
4
5
6
V+ (V)
Figure 7. Charge Injection vs Bias Voltage
Figure 8. tON and tOFF vs Supply Voltage
16
2.5
14
VIN rising
tOFF
2.0
12
10
I+ (µA)
I+ (µA)
2
8
6
tON
4
VIN falling
1.5
1.0
0.5
2
0
0.0
−40°C
25°C
85°C
−40°C
85°C
25°C
TA (°C)
TA (°C)
Figure 9. I+ vs Temperature
Figure 10. I+ vs Temperature
0
0
−10
−2
−20
Attenuation (dB)
Gain (dB)
−4
−6
−8
−10
−12
−14
0.1
−30
−40
−50
−60
−70
−80
1
10
Frequency (MHz)
100
1000
−90
0.1
Figure 11. Bandwidth (V+ = 5 V)
12
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1
10
Frequency (MHz)
100
1000
Figure 12. Attenuation vs Frequency
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Typical Characteristics (continued)
0.010
0.009
THD + (%)
0.008
0.007
0.006
0.005
0.004
0.003
0.002
0.001
0
10
100
1000
Frequency (Hz)
10000
100000
Figure 13. Total Harmonic Distortion vs Frequency
(V+ = 5 V)
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7 Parameter Measurement Information
V+
VNC NC
COM
+
VCOM
Channel On
VNO NO
r on =
IN
VI
ICOM
VCOM – VNO or VNC
Ω
I COM
VI = VIH or VIL
+
GND
Figure 14. ON-State Resistance (ron)
V+
VNC NC
COM
+
VCOM
+
VNO NO
IN
VI
Off-State Leakage Current
Channel Off
VI = VIH or VIL
+
GND
Figure 15. OFF-State Leakage Current (INC(OFF), INC(PWROFF), INO(OFF), INO(PWROFF), ICOM(OFF), ICOM(PWROFF))
V+
VNC NC
COM
+
VNO NO
VI
VCOM
On-State Leakage Current
Channel On
VI = VIH or VIL
IN
+
GND
Figure 16. ON-State Leakage Current (ICOM(ON), INC(ON), INO(ON))
14
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Parameter Measurement Information (continued)
V+
Capacitance
Meter
VNC
NC
VNO
NO
VBIAS = V+ or GND
VI = V+ or GND
VCOM COM
VBIAS
VI
Capacitance is measured at NC,
NO, COM, and IN inputs during
on and off conditions.
IN
GND
Figure 17. Capacitance (CI, CCOM(ON), CNC(OFF), CNO(OFF), CNC(ON), CNO(ON))
V+
VCOM
NC or NO
VNC or VNO
NC or NO
CL(2)
TEST
RL
CL
VCOM
tON
50 Ω
35 pF
V+
tOFF
50 Ω
35 pF
V+
COM
RL
IN
VI
Logic
Input (1)
CL(2)
GND
RL
V+
Logic
Input
(VI )
50%
50%
0
tON
tOFF
Switch
Output
(VNC or VNO)
90%
90%
(1)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns,
tf < 5 ns.
(2)
CL includes probe and jig capacitance.
Figure 18. Turnon (tON) and Turnoff Time (tOFF)
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Parameter Measurement Information (continued)
V+
NC or NO
V+
Logic
Input
(VI)
VNC or VNO
VCOM
50%
0
COM
NC or NO
CL(2)
RL
IN
VI
Switch
Output
(VCOM)
90%
90%
tBBM
Logic
Input(1)
VNC or VNO = V+
RL = 50 Ω
CL = 35 pF
GND
(1)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns,
tf < 5 ns.
(2)
CL includes probe and jig capacitance.
Figure 19. Break-Before-Make Time (tBBM)
V+
Network Analyzer
50 Ω
VNC
NC
Channel On: NC to COM
COM
Source
Signal
VCOM
VI = V+ or GND
NO
Network Analyzer Setup
IN
VI
50 Ω
+
Source Power = 0 dBm
(632-mV P-P at 50- Ω load)
GND
DC Bias = 350 mV
Figure 20. Bandwidth (BW)
V+
Network Analyzer
Channel Off: NC to COM
50 Ω
VNC
NC
VI = V+ or GND
COM
Source
Signal
50 Ω
VCOM
NO
Network Analyzer Setup
IN
VI
50 Ω
+
GND
Source Power = 0 dBm
(632-mV P-P at 50- Ω load)
DC Bias = 350 mV
Figure 21. OFF Isolation (OISO)
16
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Parameter Measurement Information (continued)
V+
Network Analyzer
Channel On: NC to COM
50 Ω
VNC
Channel Off: NO to COM
NC
VCOM
Source
Signal
VNO
NO
+
Network Analyzer Setup
50 Ω
IN
VI
50 Ω
VI = V+ or GND
Source Power = 0 dBm
(632-mV P-P at 50- Ω load)
GND
DC Bias = 350 mV
Figure 22. Crosstalk (XTALK)
V+
RGEN
VGEN
Logic
Input
(VI)
OFF
ON
OFF V
IL
NC or NO
COM
+
VIH
VCOM
VCOM
NC or NO
ΔVCOM
CL(2)
VI
VGEN = 0 to V+
IN
Logic
Input(1)
RGEN = 0
CL = 1 nF
QC = CL × ΔVCOM
VI = VIH or VIL
GND
(1)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns,
tf < 5 ns.
(2)
CL includes probe and jig capacitance.
Figure 23. Charge Injection (QC)
Channel On: COM to NC
VSOURCE = V+ P-P
VI = VIH or VIL
RL = 600 Ω
fSOURCE = 20 Hz to 20 kHz
CL = 50 pF
V+/2
V+
Audio Analyzer
RL
Source
Signal
10 µ F
NO
10 µ F
COM
600 Ω
NC
600 Ω
VI
CL(1)
IN
GND
600 Ω
(1)
CL includes probe and jig capacitance.
Figure 24. Total Harmonic Distortion (THD)
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8 Detailed Description
8.1 Overview
The TS5A3159A is a single-pole-double-throw (SPDT) solid-state analog switch. The TS5A3159A, like all analog
switches, is bidirectional. When powered on, each COM pin is connected to the NC pin. For this device, NC
stands for normally closed and NO stands for normally open. If IN is low, COM is connected to NC. If IN is high,
COM is connected to NO.
The TS5A3159A is a break-before-make switch. This means that during switching, a connection is broken before
a new connection is established. The NC and NO pins are never connected to each other.
8.2 Functional Block Diagram
IN
COM
NC
NO
8.3 Feature Description
The low ON-state resistance, ON-state resistance matching, and charge injection in the TS5A3159A make this
switch an excellent choice for analog signals that require minimal distortion. In addition, the low THD allows
audio signals to be preserved more clearly as they pass through the device.
The 1.65-V to 5.5-V operation allows compatibility with more logic levels, and the bidirectional I/Os can pass
analog signals from 0 V to V+ with low distortion.
8.4 Device Functional Modes
Table 1 lists the functional modes of the TS5A3159A.
Table 1. Function Table
NC TO COM,
COM TO NC
NO TO COM,
COM TO NO
L
ON
OFF
H
OFF
ON
IN
18
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TS5A3159A can be used in a variety of customer systems. The TS5A3159A can be used anywhere multiple
analog or digital signals must be selected to pass across a single line.
9.2 Typical Application
5V
V+
IN
NO
COM
GND
NC
MCU or
System Logic
To/From
System
Figure 25. System Schematic for TS5A3159A
9.2.1 Design Requirements
In this particular application, V+ was 5 V, although V+ is allowed to be any voltage specified in Recommended
Operating Conditions. A decoupling capacitor is recommended on the V+ pin. See Power Supply
Recommendations for more details.
9.2.2 Detailed Design Procedure
In this application, IN is, by default, pulled low to GND. Choose the resistor size based on the current driving
strength of the GPIO, the desired power consumption, and the switching frequency (if applicable). If the GPIO is
open-drain, use pullup resistors instead.
9.2.3 Application Curve
180
160
140
I+ (nA)
120
100
80
60
40
20
0
-20
-40°C
25°C
85°C
TA (°C)
Figure 26. Power-Supply Current vs Temperature
(V+ = 5 V)
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If there are multiple pins labeled VCC, then a 0.01-μF or
0.022-μF capacitor is recommended for each VCC because the VCC pins will be tied together internally. For
devices with dual-supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass
capacitor is recommended for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to loop antenna theory, but different enough to warrant their own
discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This is primarily due to the
change of width of the trace. At the apex of the turn, the trace width is increased to 1.414 times its width. This
upsets the transmission line characteristics, especially the distributed capacitance and self–inductance of the
trace — resulting in the reflection. It is a given that not all PCB traces can be straight, and so they will have to
turn corners. Below figure shows progressively better techniques of rounding corners. Only the last example
maintains constant trace width and minimizes reflections.
Unused switch I/Os, such as NO, NC, and COM, can be left floating or tied to GND. However, the IN pin must be
driven high or low. Due to partial transistor turnon when control inputs are at threshold levels, floating control
inputs can cause increased ICC or unknown switch selection states.
11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 27. Trace Example
20
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
Table 2. Parameter Description
SYMBOL
VCOM
DESCRIPTION
Voltage at COM
VNC
Voltage at NC
VNO
Voltage at NO
ron
Resistance between COM and NC or COM and NO ports when the channel is on
rpeak
Peak ON-state resistance over a specified voltage range
Δron
Difference of ron between channels
ron(flat)
Difference between the maximum and minimum value of ron in a channel over the specified range of conditions
INC(OFF)
Leakage current measured at the NC port, with the corresponding channel (NC to COM) in the off state under
worst-case input and output conditions
INC(PWROFF)
INO(OFF)
INO(PWROFF)
Leakage current measured at the NC port during the power-down condition, V+ = 0
Leakage current measured at the NO port, with the corresponding channel (NO to COM) in the off state under
worst-case input and output conditions
Leakage current measured at the NO port during the power-down condition, V+ = 0
INC(ON)
Leakage current measured at the NC port, with the corresponding channel (NC to COM) in the on state and the
output (COM) being open
INO(ON)
Leakage current measured at the NO port, with the corresponding channel (NO to COM) in the on state and the
output (COM) being open
ICOM(ON)
ICOM(PWROFF)
Leakage current measured at the COM port, with the corresponding channel (COM to NO or COM to NC) in the on
state and the output (NC or NO) being open
Leakage current measured at the COM port during the power-down condition, V+ = 0
VIH
Minimum input voltage for logic high for the control input (IN)
VIL
Maximum input voltage for logic low for the control input (IN)
VI
Voltage at (IN)
IIH, IIL
Leakage current measured at (IN)
tON
Turnon time for the switch. This parameter is measured under the specified range of conditions and by the
propagation delay between the digital control (IN) signal and analog outputs (COM, NC, or NO) signal when the
switch is turning on.
tOFF
Turnoff time for the switch. This parameter is measured under the specified range of conditions and by the
propagation delay between the digital control (IN) signal and analog outputs (COM, NC, or NO) signal when the
switch is turning off.
tBBM
Break-before-make time. This parameter is measured under the specified range of conditions and by the
propagation delay between the output of two adjacent analog channels (NC and NO) when the control signal
changes state.
QC
Charge injection is a measurement of unwanted signal coupling from the control (IN) input to the analog (NC, NO,
or COM) output. This is measured in coulomb (C) and measured by the total charge induced due to switching of the
control input. Charge injection, QC = CL × ΔVO, CL is the load capacitance and ΔVO is the change in analog output
voltage.
CNC(OFF)
Capacitance at the NC port when the corresponding channel (NC to COM) is off
CNO(OFF)
Capacitance at the NO port when the corresponding channel (NO to COM) is off
CNC(ON)
Capacitance at the NC port when the corresponding channel (NC to COM) is on
CNO(ON)
Capacitance at the NO port when the corresponding channel (NO to COM) is on
CCOM(ON)
CIN
Capacitance at the COM port when the corresponding channel (COM to NC or COM to NO) is on
Capacitance of (IN)
OISO
OFF isolation of the switch is a measurement OFF-state switch impedance. This is measured in dB in a specific
frequency, with the corresponding channel (NC to COM or NO to COM) in the off state.
XTALK
Crosstalk is a measurement of unwanted signal coupling from an on channel to an off channel (NC to NO or NO to
NC). This is measured in a specific frequency and in dB.
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Copyright © 2005–2015, Texas Instruments Incorporated
Product Folder Links: TS5A3159A
21
TS5A3159A
SCDS200D – JUNE 2005 – REVISED JUNE 2015
www.ti.com
Table 2. Parameter Description (continued)
SYMBOL
DESCRIPTION
BW
Bandwidth of the switch. This is the frequency in which the gain of an on channel is –3 dB below the DC gain.
THD
Total harmonic distortion describes the signal distortion caused by the analog switch. This is defined as the ratio or
root mean square (RMS) value of the second, third, and higher harmonic to the absolute magnitude of the
fundamental harmonic.
I+
Static power supply current with the control (IN) terminal at V+ or GND
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
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Copyright © 2005–2015, Texas Instruments Incorporated
Product Folder Links: TS5A3159A
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TS5A3159ADBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(JAJK ~ JAJR)
JAJH
TS5A3159ADBVRE4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(JAJK ~ JAJR)
JAJH
TS5A3159ADBVRG4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(JAJK ~ JAJR)
JAJH
TS5A3159ADBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(JAJK ~ JAJR)
JAJH
TS5A3159ADBVTE4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(JAJK ~ JAJR)
JAJH
TS5A3159ADBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(JAJK ~ JAJR)
JAJH
TS5A3159ADCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(JJK ~ JJR)
JJH
TS5A3159ADCKRE4
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(JJK ~ JJR)
JJH
TS5A3159ADCKRG4
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(JJK ~ JJR)
JJH
TS5A3159ADCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(JJK ~ JJR)
JJH
TS5A3159ADCKTG4
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(JJK ~ JJR)
JJH
TS5A3159AYZPR
ACTIVE
DSBGA
YZP
6
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(JJ2 ~ JJ7 ~ JJN)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2015
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Nov-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
TS5A3159ADBVR
SOT-23
3000
180.0
9.2
DBV
6
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.17
3.23
1.37
4.0
8.0
Q3
TS5A3159ADBVT
SOT-23
DBV
6
250
180.0
9.2
3.17
3.23
1.37
4.0
8.0
Q3
TS5A3159ADCKR
SC70
DCK
6
3000
180.0
9.2
2.3
2.55
1.2
4.0
8.0
Q3
TS5A3159ADCKT
SC70
DCK
6
250
180.0
9.2
2.3
2.55
1.2
4.0
8.0
Q3
TS5A3159AYZPR
DSBGA
YZP
6
3000
178.0
9.2
1.02
1.52
0.63
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Nov-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TS5A3159ADBVR
SOT-23
DBV
6
3000
205.0
200.0
33.0
TS5A3159ADBVT
SOT-23
DBV
6
250
205.0
200.0
33.0
TS5A3159ADCKR
SC70
DCK
6
3000
205.0
200.0
33.0
TS5A3159ADCKT
SC70
DCK
6
250
205.0
200.0
33.0
TS5A3159AYZPR
DSBGA
YZP
6
3000
220.0
220.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
YZP0006
DSBGA - 0.5 mm max height
SCALE 9.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.15
BALL TYP
0.05 C
0.5 TYP
C
SYMM
1
TYP
B
0.5
TYP
D: Max = 1.418 mm, Min =1.358 mm
E: Max = 0.918 mm, Min =0.858 mm
A
6X
0.015
0.25
0.21
C A
B
1
2
SYMM
4219524/A 06/2014
NanoFree Is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
TM
3. NanoFree package configuration.
www.ti.com
EXAMPLE BOARD LAYOUT
YZP0006
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
6X ( 0.225)
1
2
A
(0.5) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
( 0.225)
METAL
0.05 MAX
METAL
UNDER
MASK
0.05 MIN
( 0.225)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219524/A 06/2014
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).
www.ti.com
EXAMPLE STENCIL DESIGN
YZP0006
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
6X ( 0.25)
(R0.05) TYP
2
1
A
(0.5)
TYP
SYMM
B
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219524/A 06/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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