Hi-performance Regulator IC Series for PCs FET Integrated Switching Regulator for DDR-SDRAM Cores BD95514MUV No.09030EBT16 ●Description BD95514MUV is a switching regulator capable of supplying high current output (up to 4A) at low output voltages (0.7V~5.0V) over a broad range of input voltages (4.5V~28V). The regulator features an internal N-MOSFET power transistor for high 3 TM efficiency and low space consumption, while incorporating ROHM’s proprietary H Reg control mode technology, yielding the industry’s fastest transient response time against load changes. SLLM (Simple Light Load Mode) technology is also integrated to improve efficiency when powering lighter loads, as well as soft start, variable frequency, short-circuit protection with timer latch, over-voltage protection, and REF tracking functions. This regulator is suited for PC applications. ●Features 1) I Internal low ON-resistance power N-MOSFET (typ:120mΩ) 2) I Internal 5V linear voltage regulator (100mA) 3 TM 3) Integrated H Reg DC/DC converter controller 4) Selectable Simple Light Load Mode (SLLM), Quiet Light Load Mode (QLLM) and forced continuous mode 5) Built-in thermal shutdown, low input, current overload, output over- and under-voltage protection circuitry 6) Soft start function to minimize rush current during startup 7) Adjustable switching frequency (f = 200 kHz ~ 1000 kHz:It changes depending on the setup condition.) 8) Built-in output discharge function 9) VQFN032V5050 power package 10) Tracking function 11) Internal bootstrap diode ●Applications Mobile PCs, desktop PCs, LCD-TV, digital household electronics www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 1/15 2009.04 - Rev.B Technical Note BD95514MUV ●Absolute Maximum Ratings (Ta=25°C) Parameter Input Voltage 1 Input Voltage 2 Input Voltage 3 Input Voltage 4 External VCC Voltage BOOT Voltage BOOT-SW Voltage Output Feedback Voltage SS/FS/MODE Voltage VREG Voltage EN/CTL Input Voltage PGOOD Voltage Output Current (Average) Power Dissipation 1 Power Dissipation 2 Power Dissipation 3 Power Dissipation 4 Operating Temperature Range Storage Temperature Range Junction Temperature Symbol VCC VDD AVIN VIN EXTVCC BOOT BOOT-SW FB SS/FS/MODE VREG EN/CTL PGOOD Isw Pd1 Pd2 Pd3 Pd4 Topr Tstg Tjmax Value 7 *1 7 *1 30 *1 30 *1 7 *1 35 7 *1 VCC VCC VCC 7 *1 7 *1 4 *1 0.38*2 0.88*3*6 2.06*4*6 4.56*5*6 -10～+100 -55～+150 +150 Unit V V V V V V V V V V V A W W W W °C °C °C *1 Do not exceed Pd. *2 Ta≧25°C (IC only), power dissipated at 3.0mW / °C. *3 Ta≧25°C (single-layer board, 20.2 mm2 copper heat dissipation pad), power dissipated at 7.0mW / °C. *4 Ta≧25°C (4-layer board, 10.29 mm2 copper heat dissipation pad on top layer, 5505 mm2 pad on 2nd and 3rd layer), power dissipated at 16.5mW / °C. *5 Ta≧25°C (4-layer board, all layers with 5505 mm2 copper heat dissipation pads), power dissipated at 36.5mW / °C. *6 Values observed with chip backside soldered. When unsoldered, power dissipation is lower. ●Operating Conditions (Ta=25°C) Parameter Input Voltage 1 Input Voltage 2 Input Voltage 3 Input Voltage 4 External VCC Voltage BOOT Voltage SW Voltage BOOT-SW Voltage MODE Input Voltage EN/CTL Input Voltage PGOOD Voltage Minimum On Time Symbol VCC VDD AVIN VIN EXTVCC BOOT SW BOOT-SW MODE EN/CTL PGOOD tonmin Min 4.5 4.5 4.5 4.5 4.5 4.5 -0.7 4.5 0 0 0 - Max 5.5 5.5 28 28 5.5 33 28 5.5 5.5 5.5 5.5 100 Unit V V V V V V V V V V V nsec *This product is not designed for use in a radioactive environment. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 2/15 2009.04 - Rev.B Technical Note BD95514MUV ●ELECTRICAL CHARACTERISTICS (unless otherwise noted, Ta=25℃, AVIN=12V, VCC=VDD=VREG, EN/CTL=5V, MODE=0V, RFS=180kΩ) Standard Value Parameter Symbol Unit Condition MIN TYP MAX [Whole Device block] AVIN bias current 1 IIN1 1300 2000 μA AVIN bias current 2 IIN2 200 300 μA EXTVCC=5V AVN standby current IINstb 0 10 μA CTL=EN＝0V EN Low voltage ENlow GND 0.8 V EN High voltage ENhigh 2.3 5.5 V EN bias current IEN 12 20 μA CTL Low voltage CTLlow GND 0.8 V CTL High voltage CTLhigh 2.3 5.5 V CTL bias current ICTL 1 6 μA [5V Linear regulator block ] VREG output voltage VREG 4.90 5.00 5.10 V AVIN=6.0 to 25VIREG=0 to 100mA Maximum current IREG 200 mA [5V switch block ] EXTVCC input threshold voltage EVCC_UVLO 4.2 4.4 4.6 V EXTVCC:Sweep up Switch resistance REVCC 1.0 2.0 Ω [Under Voltage Locked Out block ] AVIN threshold voltage AVIN_ UVLO 4.1 4.3 4.5 V VCC:Sweep up AVIN hysteresis voltage dAVIN_ UVLO 100 160 220 mV VCC:Sweep down VREG threshold voltage VREG_ UVLO 4.1 4.3 4.5 V VREG:Sweep up VREG hysteresis voltage dVREG_ UVLO 100 160 220 mV VREG:Sweep down [H3RegTM block] ON Time ton 400 500 600 nsec MAX ON Time tonmax 5.0 11.0 22.0 μsec MIN OFF Time toffmin 450 550 nsec [FET Driver block] High side ON resistance Ron_high 120 200 mΩ Low side ON resistance Ron_low 120 200 mΩ [SCP block] SCP startup voltage VSCP 0.420 0.490 0.560 V VFB:30%down Delay time tSCP 0.5 1 2 ms [OVP block] OVP setting voltage VOVP 0.800 0.840 0.880 V VFB:20%up Delay time tOVP 0.5 1 2 ms [Soft start block] Charge current Iss 1.4 2.2 3.0 μA Standby voltage Vss_stb 100 mV [Current Limit block] High side FET output current limit IHOCP 4.5 6.0 7.5 A High peak detect Low side FET output current limit ILOCP 3.0 4.0 5.0 A Low peak detect [Output Voltage Sense block] Feedback pin voltage 1 VFB1 0.693 0.700 0.707 V Feedback pin voltage 2 VFB2 0.690 0.700 0.710 V Ta=-10℃ to 100℃,Iout=0A to 4A Feedback pin bias current IFB -100 0 100 nA [Mode block] SLLM VthSLLM VCC-0.5 VCC V SLLM(Maximum LG offtime:∞) Forced continuous mode VthCONT GND 0.5 V Continuous mode QLLM VthQLLM 2.5 3.0 3.5 V QLLM(Maximum LG offtime:40usec) Open voltage VMODE 1.5 3.0 V [Power Good block] VFB Power Good Low voltage VFB PL 0.605 0.630 0.655 V VFB:10%down VFB Power Good High voltage VFB PH 0.745 0.770 0.795 V VFB:10%up www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 3/15 2009.04 - Rev.B Technical Note BD95514MUV ●Reference Data 100 100 100 SLLM SLLM SLLM 80 60 60 η [%] η [%] Continuous Mode 40 20 0 0.01 80 60 Continuous Mode 40 40 20 20 0 0.1 1 10 Io [A] 0.01 2μsec/div VOUT (50mV/div) 0 0.1 Io [A] 1 10 0.01 SW (10V/div) 2μsec/div VOUT (50mV/div) SW (10V/div) IOUT (2A/div) Fig.3 Io-Efficiency (VIN=19V,VOUT=2.5V) VOUT (50mV/div) Fig.6 Transient Response (VIN=19V, VOUT=2.5V) Fig.5 Transient Response (VIN=12V, VOUT=2.5V) 2μsec/div 2μsec/div 2μsec/div VOUT (50mV/div) VOUT (50mV/div) SW (10V/div) SW (10V/div) SW (10V/div) IOUT (2A/div) IOUT (2A/div) Fig.8 Transient Response (VIN=12V, VOUT=2.5V) Fig.7 Transient Response (VIN=7V, VOUT=2.5V) 200μsec/div 2msec/div EN EN VOUT 2[V/div] VOUT 2[V/div] PGOOD www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Fig.9 Transient Response (VIN=19V, VOUT=2.5V) VOUT 2[V/div] 200μsec/div SW IL 5[A/div] PGOOD Fig.10 PGOOD Rising Waveform 2μsec/div IOUT (2A/div) VOUT (50mV/div) IOUT (2A/div) 1 SW (10V/div) IOUT (2A/div) Fig.4 Transient Response (VIN=7V, VOUT=2.5V) 0.1 Io [A] Fig.2 Io-Efficiency (VIN=12V,VOUT=2.5V) Fig.1 Io-Efficiency (VIN=7V,VOUT=2.5V) Continuous Mode η [%] 80 Fig.11 PGOOD Falling Waveform 4/15 Fig.12 SCP Timer Latch Waveform 2009.04 - Rev.B 10 Technical Note BD95514MUV ●Reference Data 400μsec/div EN VREG 2[V/div] VOUT 2[V/div] SW Fig.13 EN wake up ●Block Diagram VIN VREG 13 VCC 7 AVIN SS 16 VDD EN 10 8 VREG AVIN Reference Block CTL 5 Soft Start 1 SS VREF×0.85 VSS×0.85 VOUT Delay PGOOD 3 SCP ILIM 4 OCP HG MODE EN Power Good H3RegTM Controller Block R 26 SW MODE Q 28 MODE S FB AVIN 14 REF×1.2 OVP www.rohm.com VDD PGND 23 24 25 TSD 32 20 CE EN/UVLO MODE © 2009 ROHM Co., Ltd. All rights reserved. 21 22 FB 5V Reg VREG VREG 31 LG Thermal Protection 15 30 Driver Circuit 18 UVLO ILIM SCP TSD VOUT 29 SS EXTVCC VIN(4.5～28V) VIN 27 17 6 BOOT 2 OVP REF(0.7V) VREG UVLO 11 9 FS 19 VOUT 12 MODE 5/15 GND 2009.04 - Rev.B Technical Note BD95514MUV ●Pin Configuration 24 23 22 21 20 19 18 17 16 SS PGND 25 SW 26 15 VREG SW 27 14 EXTVcc SW 28 13 VCC SW 29 12 GND SW 30 11 FS SW 31 10 EN PGND 32 9 MODE 1 2 3 4 VIN VIN VIN VIN 5 6 7 8 BOOT PGOOD AVIN CTL *Connect the underside (FIN) to the ground terminal ●Pin Function Table PIN No. 1-4 5 6 7 8 PIN Name VIN BOOT PGOOD AVIN CTL 9 MODE 10 11 12 13 14 15 16 17 18 19 20 21 22-25 26-31 32 Underside EN FS GND VCC EXTVCC VREG SS REF FB VOUT CE VDD PGND SW PGND FIN www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. PIN Function Battery voltage input (4.5 ~ 28 V) HG driver power supply Power good output (high when output ±10% of regulation) Battery voltage sense Linear regulator on/off (high = 5.0V, low = off) Control mode selection GND：Continuous Mode 3.0V：QLLM VCC：SLLM Enable output (high when VOUT ON) Switching frequency adjustment(RFS = 30 k ~ 300 kΩ) Sense ground Power supply input External power supply input IC reference voltage (5.0V / 100mA) Soft start condenser input Output reference voltage (0.7 V) Feedback input (0.7 V) Voltage discharge output Reversing HG output Power supply input (5 V) Power ground Output to inductor Power ground Substrate connection 6/15 2009.04 - Rev.B Technical Note BD95514MUV ●Pin Descriptions ・VCC This pin supplies power to the IC’s internal circuitry, excluding the FET driver. The input supply voltage range is 4.5 to 5.5 V. This pin should be bypassed with either a power capacitor or RC filter. ・EN Enables or disables the switching regulator. When the voltage on this pin reaches 2.3V or higher, the internal switching regulator is turned on. At voltages less than 0.8V, the regulator is turned off. ・VDD This pin supplies power to the low side of the FET driver, as well as to the bootstrap diode. As the diode draws its peak current when switching on or off, this pin should be bypassed with a capacitance of approximately 1µF. ・VREG Output pin from the 5V linear regulator. This pin also supplies power to the internal driver and control circuitry. VREG standby function is controlled by the CTL pin. The output supplies 5V at 100mA and should be bypassed to ground using a 10 µF capacitor with a rating of X5R or X7R. ・EXTVCC External power supply input for the linear regulator. When the voltage on the EXTVCC pin exceeds 4.4V, the regulator uses it in conjunction with other power sources to supply VREG. Connect the EXTVCC pin to GND when not in use. ・REF Reference voltage output pin. The reference voltage is set internally by the IC to 0.7V, and the IC works to keep VREF approximately equal to VFB. Variations in voltage levels on this pin affect the output voltage, so the pin should be bypassed with a 100pF ~ 0.1µF ceramic capacitor. ・SS Soft start pin. When EN is set high, the capacitor between the internal current source(typ:2.2μA) and SS-GND controls the startup time of the IC. When the voltage on the SS pin is lower than the REF output voltage (0.7V), the output voltage is held at the same voltage as the SS pin. ・AVIN The BD95514MUV controls the duty cycle and output voltage based upon the input voltage at this pin, so voltage variations or oscillations on this line can cause operation to become unstable. This pin also acts as the voltage input for the switching block, so insufficient coupling impedance can also cause operation to become unstable. Therefore, this line should be bypassed with either a power capacitor or RC filter. ・FS Frequency-adjusting resistance input pin. Attaching a resistance of 30k~300kΩ adjusts the switching frequency from 200 kHz~1MHz (p.11). ・BOOT This pin serves as the power source for the high side of the FET driver. A bootstrap diode is integrated within the IC. The maximum voltage on this pin should not exceed +30V vs. GND or +7V vs. SW. When operating the switching regulator, the operation of the bootstrap circuitry causes the BOOT voltage to swing from (VIN + VDD) ~ VDD. ・PGOOD Power good indicator. This open-drain output should be connected via a 100kΩ pull-up resistor. ・MODE Mode selection pin. When low, the IC functions in forced-continuous mode; at voltages from 0V ~ 3V, QLLM mode; when high, SLLM mode. ・CTL Linear regulator control pin. When voltage is 2.3V or higher, a logic HIGH is recognized and the internal regulator (VREG = 5 V) is switched on. At voltages of 0.8V or lower, a logic LOW is recognized and the regulator is switched off. However, even if EN is logic HIGH, the switching regulator will not operate if CTL is logic LOW. ・FB Output voltage feedback input. VFB is held at 0.7V by the IC. ・SW Output from the switching regulator to the inductor. This output swings from VIN ~ GND. The trace from the output to the inductor should be as short and wide as possible. ・VOUT Voltage output discharge pin. When EN is off, this output is pulled low. ・VIN Power supply input. The IC can accept any input from 4.5V to 28V. This pin should be bypassed directly to ground by a power capacitor. ・PGND Power ground terminal. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 7/15 2009.04 - Rev.B Technical Note BD95514MUV ●Operation The BD95514MUV is a switching regulator incorporating ROHM’s proprietary H3RegTM CONTROLLA control system. When VOUT drops suddenly due to changes in load, the system quickly restores the output voltage by extending the ton time interval. This improves the regulator’s transient response. When light-load mode is activated, the IC employs the Simple Light Load Mode (SLLM) controller, further improving system efficiency. 3 TM H Reg Control (Normal Operation) VFB When VFB falls below the reference voltage (0.7V), the H3RegTM CONTROLLA is activated; VREF tON HG VREF VIN × 1 [sec]・・・(1) f High gate output is determined by the above formula. LG (Rapid Changes in Load) When VOUT drops due to a sudden change in load and the voltage remains below VREF after the preprogrammed tON time interval has elapsed, the system quickly restores VOUT by extending the tON time, thereby improving transient response. VFB VREF Io tON+α HG LG Light Load Control (SLLM Mode) VFB SLLM mode is enabled by setting the MODE pin to logic high. When the low gate is off and the current through the inductor is 0 (current flowing from VOUT to SW), the SLLM function is activated, disabling high gate output. If VFB falls below VREF again, the high gate is switched back on, lowering the switching frequency of the regulator and yielding higher efficiency when powering light loads. VREF HG LG 0A (QLLM Mode) QLLM mode is enabled by setting the MODE pin to HiZ or middle voltage. When the lower gate is off and the current through the inductor is 0 (current flowing from VOUT to SW), QLLM mode is activated, disabling high gate output. If VFB falls below VREF within a programmed time interval (typ. 40µs), the high gate is switched on, but if VFB does not fall below VREF, the lower gate is forced on, dropping VFB and switching the high gate back on. The minimum switching frequency is set to 25 kHz (T=40 µS), which keeps the regulator’s frequency from entering the audible spectrum but yields less efficient results than SLLM mode. VFB VREF HG LG 0A www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 8/15 2009.04 - Rev.B Technical Note BD95514MUV ●Timing Chart ・Soft Start Function The soft start function is enabled when the EN pin is set high. Current control circuitry takes effect at startup, yielding a moderate “ramping start” in output voltage. Soft start timing and incoming current are given by equation (2) and (3) below: EN tSS SS Soft start period: VOUT tSS = VREF×Css [sec] ・・・(2) 2.2μA(typ) Rush current: IIN IIN(ON)= Co×VOUT tss [A] ・・・(3) (Css: soft start capacitor; Co: All capacitors connected with VOUT) ・Timer Latch-type Short Circuit Protection VREF×0.70 When output voltage falls to VREF x 0.70 or less, the output short circuit protection engages, turning the IC off after a set period of time to prevent internal damage. When EN is switched back on or when UVLO is cleared, output continues. The time period before shutting off is set internally at 1 ms. VOUT 1ms SCP EN/UVLO ・Output Over-Voltage Protection VOUT VREF×1.2 When output reaches or exceeds VREF x 1.2, the output over-voltage protection is engaged, turning the low-side FET completely on to reduce the output (low gate on, high gate off). When the output falls, it returns to standard mode. HG LG Switching www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 9/15 2009.04 - Rev.B Technical Note BD95514MUV ●External Component Selection 1. Inductor (L) Selection The inductor’s value directly influences the output ripple current. As formula (4) indicates below, the greater the inductance or switching frequency, the lower the ripple current: (VIN-VOUT)×VOUT ΔIL= [A]・・・(4) L×VIN×f ΔIL VIN The proper output ripple current setting is about 30% of maximum output current. IL ΔIL=0.3×IOUTmax. [A]・・・(5) VOUT L L= Co (VIN-VOUT)×VOUT ΔIL×VIN×f [H]・・・(6) (ΔIL: output ripple current, f: switching frequency) Output ripple current ※ Passing a current larger than the inductor’s rated current will cause magnetic saturation in the inductor and decrease system efficiency. In selecting the inductor, be sure to allow enough margin to assure that peak current does not exceed the inductor’s rated current value. ※ To minimize possible inductor damage and maximize efficiency, choose an inductor with a low DCR and ACR resistance. 2. Output Capacitor Selection (CO) VIN When determining the proper output capacitor, be sure to factor in the equivalent series resistance (ESR) and equivalent series inductance (ESL) required to set the output ripple voltage at 20 mV or more. VOUT L ESR When selecting the limit of the inductor, be sure to allow enough margin for the output voltage. Output ripple voltage is determined by formula (7) below: ESL Co ΔVOUT=ΔIL×ESR+ESL×ΔIL / TON・・・(7) Output Capacitor (ΔIL: Ouput ripple current, ESR: equivalent series resistance, ESL: equivalent series inductance) Give special consideration to the conditions of formula (7) for output capacitance. Also, keep in mind that the output rise time must be established within the soft start timeframe. Co≦ tss×(Ilimit-IOUT) VOUT ・・・(8) tss: Soft start timeframe (see p. 10, equation (2)) Ilimit: Maximum output current Choosing a capacitance that is too large can cause startup malfunctions, or in some cases, may engage the short circuit protection. 3. Input Capacitor Selection (CIN) In order to prevent extreme over-current conditions, the input capacitor must have a low enough ESR to fully support a large ripple in the output. The formula for RMS ripple current (IRMS) is given by equation (9) below: VIN CIN VOUT L IRMS=IOUT× √VIN(VIN-VOUT) [A]・・・(9) VIN Co When VIN=2×VOUT, IRMS= IOUT 2 Input Capacitor A low-ESR capacitor is recommended to reduce ESR loss and maximize efficiency. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 10/15 2009.04 - Rev.B Technical Note BD95514MUV 4. Frequency Adjustment The resistance connected to the FS terminal adjusts the on-time (tON) during normal operation as illustrated to the left. When tON, input voltage and VREF voltage are known, the switching frequency can be determined by the following formula: VREF F= ・・・(10) VIN×tON 500 From top:VIN= 450 400 5V 7V 12V 19V 25V Frequency [kHz] 350 300 250 However, real-life considerations (such as external MOSFET gate capacitance and switching time) must be factored in as they affect the overall switching rise and fall time. This leads to an increase in tON, lowering the total frequency slightly. 200 150 100 50 Additionally, when output current lingers around 0A in continuous mode, this “dead time” also has an effect upon tON, further lowering the switching frequency. Confirm the switching frequency by measuring the current through the coil (at the point where current does not flow backwards) during normal operation. 0 50 100 150 200 250 300 RFS[kΩ] The BD95514MUV operates by feeding the output voltage back through a resistive voltage divider. The output voltage is set by the following equation (see schematic below): Output Voltage = R1+R2 R2 × VREF (0.7V) + 1 ×ΔIL×ESR・・・(11) 2 The switching frequency is also amplified by the same resistive voltage divider network: fsw ＝ R1+R2 R2 ×(frequency set by RFS) [Hz]・・・(12) VIN REF(0.7V) H3RegTM CONTROLLA VIN R Q SLLM TM Driver S SLLM FB Output Voltage ESR Circuit R1 R2 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 11/15 2009.04 - Rev.B Technical Note BD95514MUV ●Evaluation Board Circuit (Frequency=300kHz Continuous Mode/QLLM/SLLM Example Circuit) SW VOUT L1 VOUT D1 C14 GND_VIN R4 PGND SW SW SW SW SW C9 VIN C10 VIN PGND C11 VIN PGND VIN VDD R22 VDD SW C8 PGND VIN VIN GND_VOUT PGND GND_VDD R9 BOOT C12 PGOOD PGOOD C13 CE R7 VOUT AVIN FB SW3 REF R8 SS VREG EXTVCC VCC CTL GND D FS C7 VDD EN REF CTL MODE SW1 C6 VDD C19 VDD MODE R6 R5 VDD SW2 R17 C1 EN C2 R2 C4 C5 SS R1 VCC GND PGND VREG R18 GND ●Evaluation Board Parts List Designation Rating PART No. R1 10Ω MCR03 R2 0Ω MCR03 R3 R4 10Ω MCR03 R5 10KΩ MCR03 R6 270KΩ MCR03 R7 10kΩ MCR03 R8 3.07kΩ MCR03 R9 100KΩ MCR03 R10 R11 R12 R13 R14 R15 0Ω MCR03 R16 0Ω MCR03 R17 0Ω MCR03 R18 0Ω MCR03 R22 510kΩ MCR03 C01 1μF ceramic capacitor C02 - www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. VCC Company ROHM ROHM ROHM ROHM ROHM ROHM ROHM ROHM ROHM ROHM ROHM ROHM ROHM - EXTVCC Designation C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 D1 D L1 U1 12/15 Rating 1μF 1μF 3300pF 0.1μF 0.1μF 22μF 0.1μF 1000pF 220μF 470pF 3.2μH - PART No. Company ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor 4TPE220MF SANYO ceramic capacitor RSX501L-20 ROHM TDZ5.1 ROHM CDEP105-3R2MC-50 Sumida BD95514MUV ROHM 2009.04 - Rev.B Technical Note BD95514MUV ●Operation Notes (1) Absolute maximum ratings Exceeding the absolute maximum ratings (such as supply voltage, temperature range, etc.) may result in damage to the device. In such cases, it may be impossible to identify problems such as open circuits or short circuits. If any operational values are expected to exceed the maximum ratings for the device, consider adding protective circuitry (such as fuses) to eliminate the risk of damaging the IC. (2) Power supply polarity Connecting the power supply in reverse polarity can cause damage to the IC. Take precautions when connecting the power supply lines. An external power diode can be added. (3) Power supply lines The PCB layout pattern should be designed to provide the IC with low-impedance GND and supply lines. To minimize noise on the supply and GND lines, ground and power supply lines of analog and digital blocks should be separated. For all power lines supplying ICs, connect a bypass capacitor between the power supply and the GND terminal. If using electrolytic capacitors, keep in mind that their capacitance is reduced at lower temperatures. (4) GND voltage The potential of the GND pin must be the minimum potential in the system in all operating conditions. (5) Thermal design Use thermal design techniques that allow for a sufficient margin for power dissipation in actual operating conditions. (6) Inter-pin shorts and mounting errors Use caution when positioning he IC for mounting on PCBs. or if pins are shorted together. The IC may be damaged if there are any connection errors (7) Operation in strong electromagnetic fields Exercise caution when using the IC in the presence of strong electromagnetic fields as doing so may cause the IC to malfunction. (8) ASO When using the IC, set the output transistor so that it does not exceed either absolute maximum ratings or ASO. (9) Thermal shutdown circuit The IC incorporates a built-in thermal shutdown circuit (TSD circuit), which is designed to shut down the IC only to prevent thermal overloading. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC if this circuit is activated, or in environments in which activation of this circuitry can be assumed. BD95514MUV TSD ON Temp. [°C] (typ.) 175 Hysteresis Temp. [°C] (typ.) 15 (10) Testing on application boards When testing the IC with application boards, connecting capacitors directly to low-impedance terminals can subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should be turned off completely before connecting it to or removing it from a jig or fixture during the evaluation process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 13/15 2009.04 - Rev.B Technical Note BD95514MUV (11) Regarding IC input pins This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. PN junctions are formed at the intersection of these P layers with the N layers of other elements, creating parasitic diodes and/or transistors. For example (refer to the figure below): ・When GND > Pin A and GND > Pin B, the PN junction operates as a parasitic diode ・When GND > Pin B, the PN junction operates as a parasitic transistor Parasitic diodes occur inevitably in the structure of the IC, and the operation of these parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, conditions that cause these diodes to operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be avoided. Resistance Transistor (NPN) Pin A Pin B C B 端子 B E Pin A N P + N P P N + P+ B B N P N P Substrate Parasitic Element P C + N E P 基板 Parasitic Element GND Parasitic Elements GND GND Parasitic Elements GND Other Adjacent Elements Example of IC Structure (12) (12) Ground wiring traces When using both small-signal and large-current GND traces, the two ground traces should be routed separately but connected to a single ground potential within the application in order to avoid variations in the small-signal ground caused by large currents. Also ensure that the GND traces of external components do not cause variations on GND voltage. ●Power Dissipation 5.5 ① 5.0 θj-a = 328.9 °C/W ④4.56W 4.5 Power Dissipation Pd [W] IC Only ② 4.0 2 IC mounted on 1-layer board (with 20.2 mm copper thermal pad) θj-a = 142.0 °C/W 3.5 ③ 2 IC mounted on 4-layer board (with 20.2 mm pad on top layer, 2 5502 mm pad on layers 2,3) 3.0 θj-a = 60.7 °C/W 2.5 ④ ③2.06W 2 IC mounted on 4-layer board (with 5505mm pad on all layers) 2.0 1.5 ②0.88W 1.0 ①0.38W 0.5 0 0 20 40 60 80 100 120 140 Ambient Temperature Ta [°C] VQFN032V5050 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 14/15 2009.04 - Rev.B Technical Note BD95514MUV ●Ordering part number B D 9 Part No. 5 5 1 4 M Part No. U V Package MUV : VQFN032V5050 - E 2 Packaging and forming specification E2: Embossed tape and reel VQFN032V5050 <Tape and Reel information> 5.0 ± 0.1 5.0±0.1 1.0MAX 3.4±0.1 0.4 ± 0.1 1 8 9 32 16 25 24 0.75 0.5 2500pcs E2 The direction is the 1pin of product is at the upper left when you hold ) (0.22) ( reel on the left hand and you pull out the tape on the right hand 3.4 ± 0.1 +0.03 0.02 -0.02 S C0.2 Embossed carrier tape Quantity Direction of feed 1PIN MARK 0.08 S Tape 17 +0.05 0.25 -0.04 1pin (Unit : mm) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Reel 15/15 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2009.04 - Rev.B Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. 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