Infineon Power LED Driver -TLD5095 / TLD5098 DC-DC Multitopology Controller IC

Inf ineon ® P o w e r L E D D r i v e r
TLD5095 / TLD5098 DC-DC Multitopology
Controller IC
Dimensioning and Stability Guideline - Theory and Practice
Application Note
Application Note
V1.3, 2011-08-08
by Dieter Parth and Enrico Tonazzo
Automotive Power
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Table of Contents
Table of Contents
1
1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
The 10-step approach for your TLD5095/98 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
2.1.1
2.2
2.3
2.4
2.4.1
2.4.2
2.4.3
2.5
2.6
2.7
2.8
2.9
2.10
2.11
Calculation of external components for a TLD5095/98 application . . . . . . . . . . . . . . . . . . . . . . . . 7
Example: Automotive LED application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Application boundary conditions: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Switching frequency definition fSW - calculation of RFREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Calculation of the switching duty cycle - D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Calculation of boost inductor LBO and current loop resistor RCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Calculation of the current sensing resistor - RCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Boost inductor LBO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Boost inductor LBO if switching frequency fSW is provided by the µC . . . . . . . . . . . . . . . . . . . . . . . . 15
Calculation of the output capacitor - COUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Calculation of the input capacitance CIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Switching MOSFET considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Calculation of power resistor for LED current definition - RFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Calculation of over-voltage protection resistor divider - ROVL, ROVH . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Output diode selection - DBO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Gate driver buffer capacitance selection - CIVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.5
Stability considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED resistance considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED forward voltage considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stability calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Closed loop considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of the open loop gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of zeros and poles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of the slope compensation parameters and quality factor Q . . . . . . . . . . . . . . . . . . . . . .
Open loop gain calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculation of the phase margin: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
28
29
30
31
32
33
35
35
36
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Power loss and system efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLD5095/98 IC Power Losses - PIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power MOSFET - PMOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED current feedback resistor power loss - PRFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch current sensing resistor power loss - PRCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductor power loss - PLBO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input capacitor power loss - PCIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output capacitor power loss - PCOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Freewheeling diode power loss - PDBO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
39
40
40
40
40
41
41
41
5
5.1
5.2
5.3
5.4
5.5
Design-in tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Excel tool for fast evaluation of external components, efficiency and stability . . . . . . . . . . . . . . . . . .
Electrical and thermal simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Demo boards for fast evaluation in the lab & onboard LED chain . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample layouts for small application boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMC test reports and results summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
42
43
44
45
46
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Application Note
2
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Introduction
1
Introduction
Note: The following information is provided only as a guide for the implementation of the device and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
The aim of this application note is to provide a dimensioning guideline for TLD5095/98 applications. A 10-step
approach has been developed to guide the reader through the calculation of external components and stability
considerations (Chapter 2 and Chapter 3). Furthermore, an efficiency and power loss summary (Chapter 4)
completes the picture. To put the theory into practice, a typical example of application has been chosen, which
should improve the understanding of the equations used. Chapter 5 provides an overview of tools and further
information, which could be very valuable for design-in activities and detailed evaluation of TLD5095/98
applications.
Note: The following considerations focus on the TLD5095/98 for a standard boost to GND application in constant
current mode (CCM).
1.1
The 10-step approach for your TLD5095/98 application
We have developed a 10-step approach to help you find your way through the maze of formulas and equations.
We proceed step by step to develop a stable switching and energy-efficient application considering all the
application-specific boundary conditions. Figure 1 displays the flow chart for the 10-step approach.
Note: The “10-step approach” is the one used to dimension a TLD5095/98 boost application. To optimize and
further improve the system response, the entire procedure may be repeated several times! Thus, it is clear
that this is an iterative procedure and, at times, more than one dimensioning cycle is required.
STEP 1: Get Application Information
Get in touch with your customer and obtain the boundary conditions for the specific application. Think carefully
about the worst case conditions and try to avoid mapping worst case scenarios over worst case scenarios. Very
detailed knowledge about the real application ensures greater flexibility for the dimensioning of the system. In our
example, the boundary conditions are defined in Chapter 2.1.
STEP 2: Defining the Switching Frequency - fSW
A DC/DC converter is also called a switched mode power supply (SMPS). Thus, switching is its main job. The
selection of the system switching frequency is important for the selection of the external components (inductor and
capacitor size). The system efficiency and the EMC performance are directly related to one another. The RF
spectrum has some free areas in the 100 kHz to 500 kHz band. In our example, we switch at fSW = 400 kHz. The
TLD5095/98 features two different control options for fixing the switching frequency fSW. Refer to Chapter 2.2 for
more details.
STEP 3: Calculating the Switching Duty Cycle - D
The input and output power balance of a DC/DC converter is controlled by the ON and OFF timing of the switching
MOSFET. The ratio of the ON and OFF phases is called the switching duty cycle (DC). The DC can be calculated
using a simplified formula or a more detailed equation. Both approaches for calculating the DC are described in
Chapter 2.3.
Application Note
4
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Introduction
STEP 4: Selection of the Boost Inductor - LBO
An inductor is necessary to supply the output of a boost converter with the appropriate amount of power. To
dimension the boost inductor LBO you need to calculate the current flowing trough the inductor depending on the
required input voltage condition. A worst-case condition, which results in a higher inductor value, is the minimum
value of input supply voltage VIN and a lower switching frequency fSW. The calculation of the proper boost inductor
LBO for the TLD5095/98 ICs also depends on the current loop stability and the value of the current sensing resistor
RCS that senses the current through the inductor. All the equations required for this purpose are furnished in
Chapter 2.4.
STEP 5: Calculation and Selection of Output Capacitor - COUT
The output capacitor of a boost system is very important to maintain constant current flow through the load. The
capacitance value at the given output voltage is crucial. The effect of a capacitor’s DC bias is often
underestimated. For selection of the proper COUT please refer to Chapter 2.5.
STEP 6: Calculation and Selection of Input Capacitor - CIN
The value of the input capacitance CIN of a boost converter is generally selected to limit the input voltage ripple
ΔVIN required by the specification. For proper dimensioning please refer to Chapter 2.6.
STEP 7: Select Other External Components such as MOSFET, RFB, ROVL, ROVH, DBO
The selection of the switching MOSFET, freewheeling diode DBO, load current defining shunt resistor RFB and the
over-voltage protection resistors ROVL, ROVH plus gate buffer capacitance CIVCC is described in Chapter 2.7 to
Chapter 2.11.
STEP 8: Determine the Compensation Network - RCOMP, CCOMP1, CCOMP2
The external compensation network provides the flexibility to ensure a stable application with respect to various
boundary conditions. The calculation of the open loop gain and the corresponding phase margin PM and the
influence of the compensation network are explained in Chapter 3.
STEP 9: Calculate Power Loss and System Efficiency
After dimensioning the external components and the selection of the actual parts used to build up a TLD5095/98
application, the system power loss and efficiency can be determined. The method for this is illustrated in
Chapter 4.
STEP 10: Verify the Application with Simulations and Measurements
Before building prototype hardware, it is useful to perform system simulations (e.g. SPICE simulations). A thermal
system evaluation, too, could be beneficial. Infineon provides several design-in tools to simplify the usage of the
TLD5095/98 products. A summary of the available design-in tools is presented in Chapter 5.
Application Note
5
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Introduction
1
Get Application Information :
VIN Range, VOUT, I OUT, fSW , ∆VIN , ∆VOUT
2
Switching Frequency definition f SW - Calculation of R FREQ
3
•
Calculation of the Switching Duty Cycle – D
Consider worst case when VIN is at it’s minimum
Selection of the Boost Inductor - LBO
•
•
•
Calculation and selection of the current sense resistor – RCS
• Select proper R CS value to protect L BO and MOSFET and keep
in mind that the R CS value is important for the stability of the
current loop and has influence on the dimensioning of the
Boost inductor LBO
4
•
•
5
6
8
Calculation and selection of Input Capacitor – CIN and max. ESR
Select proper CIN to fullfill the input voltage ripple requirement ∆VIN
Select other Components which meet the ratings and requirements :
• Switching MOSFET
• Power resistor for LED current definition – R FB
• Overvoltage protection resistor divider - ROVL, ROVH
• Output Diode selection – DBO
• Gate Driver buffer capacitor - CIVCC
Determine the compensation network – RCOMP, CCOMP1, CCOMP2
9
Figure 1
Calculation of Boost Inductor – LBO
RCS, VOUT and fSW has influence on the size of L BO
Perform some iteration steps here to find the best solution for
the the size of the boost indctor L BO
Calculation and selection of Output Capacitor – COUT and max. ESR
• Select proper COUT to fullfill the output voltage ripple requirement
∆VOUT
•
7
10
Inductor / Input current calculation :
Average inductor current I L(AVG)
Inductor ripple current ∆IL
Min. and max. inductor current I L(min) , IL(peak)
Calculate power loss and system efficiency - η
Verify the application with simulations and measurements
Proposed procedure for selecting external components
Application Note
6
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
2
Calculation of external components for a TLD5095/98 application
The following chapter provides a detailed overview of the formulas that are used to achieve proper dimensioning
of all external components used to build up a DC/DC boost application featuring the TLD5095/98. In addition, a
sample calculation demonstrates the usage of these formulas. An Excel sheet including all formulas below can be
provided on request. Refer to Chapter 5 to get an overview of other support tools and info material.
Only constant current mode (CCM) is taken into account for further considerations.
1
2.1
Example: Automotive LED application
A typical automotive exterior light application these days is the Daytime Running Light function. Most of the OEM’s
introduce LED lights to establish brand recognition and achieve extraordinary headlamp design solutions.
Figure 2 below illustrates an eye-catching OEM example of a DRL application.
Figure 2
Daytime running light example - source: AUDI AG
2.1.1
Application boundary conditions:
Note: The following example of an application boundary condition is independent of the picture illustrated in
Figure 2.
•
•
Sum of LED forward voltage = output voltage VOUT = 40 V.
Supply input voltage VIN is specified in the range 8 V < VIN < 16 V. The typical value is usually 12 V.
Note: Many calculations must consider the worst case input voltage condition to achieve a design that works
properly over the entire input voltage range. Therefore, many calculations consider 8 V (= lowest input
voltage is the worst case for boost converters).
•
•
•
LED current or output current IOUT should be 400 mA.
Switching frequency fSW of the DC/DC converter is 400 kHz.
Boost to GND application is used according to Figure 3 below.
Application Note
7
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
VIN = 8V to 16V
IL,AVE = I IN
ID
LBO
CIN
VREF
DBO
VOUT = 40V
RFB
ISW
COUT
14
1
+5V
CIVCC
IN
IOUT = 400mA
TSW
SWO
2
SWCS
4
D1
IVCC
D2
R CS
10
SET
SGND
3
OVFB
9
D3
ROVH
D4
D5
D6
ROVL
D7
PWM
13
EN / PWMI
D8
D9
CCOMP2
11
FREQ / SYNC
8
COMP
FBH
6
FBL
7
D11
CCOMP1
D12
PWMO
RFREQ
Figure 3
D10
5
PWM
TDIM
GND
RCOMP
12
Example: B2G configuration
A summary of the application boundary condition, which should be the basis of the values used in our example for
better understanding of the upcoming equations, is presented in Figure 4 below.
INPUTS
Figure 4
Symbol
Value
Unit
Name
VIN
12,00
V
Input Voltage
Vo ut
40,00
V
Output Voltage
Io ut
0,40
A
Output Current
fsw
400,00
kHz
Switching Frequency
∆VOUT
100,00
mV
Max. allowable Ripple Voltage on VOUT
∆VIN
100,00
mV
Max. allowable Ripple Voltage on VIN
∆IL%
20,00%
%
Pk-Pk Inductor Ripple Current
VREF
300,00
mV
Feedback reference voltage VREF
Example: Typical input values
Application Note
8
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
2
2.2
Switching frequency definition fSW - calculation of RFREQ
The regulator switching frequency fSW of the TLD5095/98 can be adjusted via:
1) a simple resistor RFREQ (for fSW between 100 kHz and 500 kHz) or
2) an external clock signal generated by a µC port (VCLK -> fCLK between 250 kHz and 500 kHz).
The synchronization with an external clock signal can be beneficial if there are multiple DC/DC converters in a
system. A defined phase shift strategy could improve EMC performance. Figure 5 illustrates the two options for
controlling the switching frequency.
Note: The value of the boost inductor LBO required is calculated differently for the two switching control methods.
(Please refer to Section 2.4.2 and Section 2.4.3)
Oscillator
FREQ / SYNC
11
RFREQ
VCLK
Clock Frequency
Detector
Multiplexer
PWM
Logic
Gate
Driver
2
SWO
1
2
Figure 5
Two options for controlling the regulator switching frequency fSW
The formula below expresses the mathematical relationship between the resistor RFREQ and the switching
frequency fSW Figure 6 provides a diagram for fast evaluation.
RFREQ =
1
−12
141⋅10 F ⋅ f SW
R FREQ =
141 ⋅ 10
−12
− 3.5 ⋅103
(1)
1
− 3.5 ⋅ 10 3 = 14 .23 kΩ
F ⋅ 400 kHz
(2)
Note: 141*10-12F: internal equivalent capacitance of the Oscillator
Application Note
9
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
Figure 6
RFREQ
f SW
67.42 kΩ
100 kHz
43.78 kΩ
150 kHz
31.96 kΩ
200 kHz
24.87 kΩ
250 kHz
20.14 kΩ
300 kHz
16.76 kΩ
350 kHz
14.23 kΩ
400 kHz
12.26 kΩ
450 kHz
10.68 kΩ
500 kHz
Switching frequency fSW versus frequency selection resistor RFREQ to GND
3
2.3
Calculation of the switching duty cycle - D
The first step is to determine the switching duty cycle, D, which is needed to generate a high output voltage VOUT
from a low input voltage VIN. In principle, there are two approaches for calculating the duty cycle of the MOSFET
boost switch.
TSW = 2.5µs
ton = 2µs
VSW
toff = 0.5µs
VOUT = VLED = 40V
VIN = 8V
VRDS(on)
t
VSWO = VGS
D = 0.80
VSWO = 5V
SWITCH = ON
Figure 7
SW=OFF
SWITCH = ON
SW=OFF
t
Switching MOSFET voltage VSW and the switching duty cycle - D
Application Note
10
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
1) Simplified equation:
This calculation approach merely focuses on the input and output voltage relation. In most cases, these results
are sufficient and can be used for further calculations. (All the following considerations are based on this simplified
equation.)
D≈
VOUT − VIN
VOUT
(3)
The worst case evaluation considers the lowest input voltage VIN(min) and the highest output voltage VOUT(max) that
can occur in a system. For further calculations, this worst case duty cycle is referred to as D(worst case). For some
calculations, this parameter is required to ensure a proper dimensioning of the external passive components.
D( worstcase) ≈
40V − 8V
≈ 0.80
40V
(4)
The ON and OFF times of the switching MOSFET can be calculated on the basis of the duty cycle. The parameter
TSW is the switching period time and can be calculated from the given switching frequency:
TSW =
1
f SW
=
1
= 2.5µs
400kHz
(5)
ton = D ⋅ Tsw
(6)
t on = 0.80 ⋅ 2.5µs = 2 µs
(7)
toff = (1 − D) ⋅ Tsw
(8)
t off = (1 − 0.80) ⋅ 2.5µs = 0.5µs
(9)
Application Note
11
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
2) Detailed equation:
The Equation (10) below also considers the freewheeling diode forward voltage VD and the voltage drop across
the switching MOSFET in the ON-state VRDS(ON). During the initial evaluation stages of a DC/DC application, it is
not known which switching MOSFET and freewheeling diode will be used. Therefore, it seems difficult to calculate
a precise duty cycle at the initial stage. To complete the picture, some values have been chosen to demonstrate
the difference between the two calculation approaches.
Assumptions:
•
•
RDS(ON) of switching MOSFET = 26 mΩ; VRDS(ON) = RDS(ON) * IRMS_SW = 30mΩ ∗ 1.79 A = 0.046 V
forward voltage drop of freewheeling Schottky diode VD = 0.4 V
D=
VOUT + VD − VIN
VOUT + VD − VRDS (ON )
(10)
D=
40V + 0.4V − 8V
= 0.803
40V + 0.4V − 0.046V
(11)
There is not much difference between the approaches 1 and 2. For worst case considerations it may be meaningful
to evaluate the exact duty cycle.
4
2.4
Calculation of boost inductor LBO and current loop resistor RCS
Note: The following description to calculate the appropriate boost inductor LBO is based on the current loop stability
and the integrated slope compensation of the TLD5095/98, and differs from the standard booster equations.
IIN = IL
IL,peak = 2.2A
IL,avg = IIN,avg = 2A
IL,min = 1.8A
∆IL = 0.4A
t
SWITCH = ON
Figure 8
SW=OFF
SWITCH = ON
SW=OFF
Inductor current
Application Note
12
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
The average current IL(AVG) that flows trough the boost inductor LBO is dependent on the output current IOUT
required and the worst case duty cycle D(worst case).
I L ( AVG ) =
I OUT
1 − D( worstcase )
I L ( AVG ) =
(12)
0 .4 A
= 2A
1 − 0.80
(13)
Referring to the inductor current slope of a boost converter in CCM operation (shown in Figure 5) the minimum
inductor current IL(min) and the peak inductor current IL(Peak) can be calculated from the current ripple ΔIL specified.
ΔI L = I L ( AVG) ⋅ ΔI L %
(14)
Δ I L = 2 A ⋅ 0 . 20 = 0 . 4 A
(15)
I L( peak) = I L( AVG) +
ΔI L
2
I L ( peak ) = 2 A +
0 .4 A
= 2 .2 A
2
(17)
I L (min) = I L ( AVG ) −
ΔI L
2
(18)
I L (min) = 2 A −
(16)
0 .4 A
= 1 . 80 A
2
(19)
The inductor peak current IL(Peak) calculated for the worst case, Equation (17), indicates the maximum current
flowing through the inductor LBO, the MOSFET SW and the current loop sense resistor RCS. (See the application
drawing in Figure 39 for details.)
Application Note
13
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
An important factor for the calculation of the boost inductor LBO in Equation (22) is the value of the sensing resistor
RCS.
2.4.1
Calculation of the current sensing resistor - RCS
The RCS resistor has two functions:
•
•
1) Over-current protection: RCS is needed to limit the current through the external MOSFET switch SW and the
inductor LBO.
2) Building up a current control loop for the boost regulator: RCS is needed to measure the current through the
switch.
The switch peak over-current threshold (VSWCS) in the datasheet is required to determine the proper value for RCS:
The relationship is described in Equation (20) below.
RCS =
VSWCS
I lim it
(20)
The limiting current Ilimit should be chosen according to the highest peak current IL(peak) that can occur in the system
+ a reasonable margin of safety. Furthermore, Ilimit should be higher than the max. peak inductor current IL(peak)
and should be lower than the permissible current rating of the MOSFET SW selected and the boost inductor LBO.
Based on the maximum peak current calculated in Equation (17), we must consider 2.2 A. The assumption for
Ilimit = 3 A.
RCS =
2.4.2
0 .15V
= 0 .05 Ω
3A
(21)
Boost inductor LBO
The equivalent circuit of an inductor consists of 3 components:
•
•
•
DCR: DC resistance of a coil. The DCR value is used to calculate the power loss in the inductor.
L: total inductance of a coil.
CW: winding capacitance (winding capacitance will be ignored in further considerations)
L
DCR
CW
Figure 9
Example: Equivalent circuit of a real inductor
Application Note
14
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
Knowing the proper RCS resistance completes the device specific formula, which includes the integrated slope
compensation consideration for control loop stability at duty cycles above 0.5. This formula considers VOUT>>VIN.
The constant slope compensation is not dependent on the switching frequency fSW.
LBO ≥
VOUT ⋅ RCS
106 ⋅10−3V ⋅ f SW
L BO ≥
40V ⋅ 0 .05 Ω
= 47 .17 µH
106 ⋅ 10 − 3 V ⋅ 400 kHz
(22)
(23)
Component selected:
•
Coilcraft MSS1278563MLD, L = 56 µH, DCR = 80.2 mW
2.4.3
Boost inductor LBO if switching frequency fSW is provided by the µC
If the synchronization feature is used, the following formular should be applied to determine the proper inductor
value. The constant slope compensation is fixed for a specific switching frequency (fSW = 250 kHz).
LSYNC ≥
VOUT ⋅ RCS
106 ⋅ 10−3V ⋅ 250kHz
(24)
LSYNC ≥
40V ⋅ 0.05Ω
= 75.47µH
106 ⋅ 10−3V ⋅ 250kHz
(25)
Note: 106*10-3V: equivalent slope compensation voltage
Tips for choosing the right inductor LBO
•
•
•
•
•
In fixed-frequency boost converters, the value of the inductor is based on the desired peak-to-peak ripple
current ΔIL.
Selection of the boost inductor is a trade-off between size and cost. Higher switching frequencies = lower
inductance value = smaller component size = lower costs.
Larger inductance means lower input ripple current.
Ripple current between 20 % to 50 % of ILAVG are reasonable values to make calculations for CCM
Check the maximum DC peak current ratings and maximum operating frequencies for the inductor selected.
(In general, always try to remain within the max. ratings.)
Application Note
15
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
5
2.5
Calculation of the output capacitor - COUT
The simplified equivalent circuit of a capacitor is shown in Figure 10 below. The resistive part of the capacitor is
considered as equivalent to a series resistance ESR. The output capacitor is chosen such that it filters the
switching ripple significantly. The parasitic resistance ESR, which is out of phase with its capacitance, causes
additional voltage ripple. Ensure that capacitors are selected based on their maximum voltage, maximum ripple
current and ESR ratings at the temperature and frequency of the application. The inductive portion LC shall be
ignored in further considerations.
ESR
Figure 10
C
LC
Simplified equivalent circuit of a real capacitor
The ESR value at the required switching frequency and the capacitance at the operating point (VOUT = 40 V) can
be obtained from the datasheets of capacitors. The capacitor elected has 2 µF @ VOUT = 40 V although it is a
device rated for 4.7 µF (Figure 11, diagram on the right hand side). Hence, the application requires 5 capacitors
in parallel to achieve the required capacitance of >8µF.
C @ 40V ~ 2µF
ESR~2.5mΩ
f SW =400kHz
VOUT=40V
Figure 11
COUT: ESR and DC bias of a 4.7 µF/50 V/X7R ceramic capacitor (source Murata:
GRM32EB31H475KA87) Automotive type: GCM32ER71H475KA55
Application Note
16
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
When the switching MOSFET is ON the output capacitor COUT must supply the load. Therefore, the worst case
duty cycle (D(worstcase)) divided by the switching frequency (fSW) is used in the formula to indicate the ON time (tON
in Equation (6)). The ripple content due to the ESR of the capacitor is ignored in this formular.
COUT ≥
I OUT ⋅ D( worstcase)
C OUT ≥
(26)
ΔVOUT ⋅ f SW
0.4 A ⋅ 0.80
≥ 8 µF
100 mV ⋅ 400 kHz
(27)
It is good to know the mean current which is flowing through the output capacitor for the calculation of the power
consumption of the output capacitor.
I RMS
_ COUT
=
I OUT
2
I RMS _ COUT = 0.4 A2 ⋅
⋅
D ( worstcase
2
)
1 − D ( worstcase
+
)
ΔI L
⋅ (1 − D ( worstcase
12
)
2
)
(28)
0.80
0.20 2
2
+
⋅ (1 − 0.80) = 0.800013A
1 − 0.80
12
(29)
A simplified formula can be used since the second term only has a small impact:
I RMS _ COUT ≈ I OUT ⋅
I RMS
_ COUT
D ( worstcase )
(30)
1 − D ( worstcase )
≈ 0 .4 A ⋅
0 . 80
≈ 0 .8 A
1 − 0 . 80
(31)
ID = ICOUT
I L,peak = 2.2A
IL,min = 1.8A
IRMS_D = IRMS_COUT = 0.8A
t
SWITCH = ON
Figure 12
SW=OFF
SWITCH = ON
SW=OFF
Diode current ID flowing trough COUT
The maximum permissible voltage ripple on the output voltage should be known and specified by the application.
In our example, the voltage output ripple should not exceed: ΔVOUT = 100 mV.
Application Note
17
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
Output voltage ripple and ESR value:
ΔVOUT = I L ( peak ) ⋅ ESR
(32)
The maximum permissible ESR value can be derived:
ESR ≤
ΔVOUT
I L ( peak )
(33)
ESR ≤
100mV
= 45.45mΩ
2.2 A
(34)
Selection of the output capacitor:
•
•
•
Voltage Rating > 40 V: GCM32ER71H475KA55 = 50 V
IRMS > 800 mA: GCM32ER71H475KA55 > 1 A
ESR < 45.45 mOhm: GCM32ER71H475KA55 = 5 times 2.5 mΩ in parallel = 2mΩ
The output capacitor system design could consider:
1) An electrolytic capacitor. This solution is suitable if the capacitance value required is relatively high
(e.g. > 22 µF) and higher DC voltage classes are called for. Despite the advantage of higher capacitance values
available, the electrolytic capacitor has some disadvantages such as:
•
•
•
•
Higher ESR values = more power losses (those with low ESR are more expensive and, in any case, far less
than ESR values for ceramic capacitors)
Poor thermal conduction path (e.g. SMD versions have a plastic interface to the PCB)
Less robust and less reliable
Limited temperature range (those with high temperature ranges are more expensive)
If an electrolytic capacitor is used in a system, it is a good practice to place a small (e.g. 100 nF) capacitor in
parallel to bring down the ESR and achieve an additional filtering effect.
2) To overcome the issues with electrolytic capacitors, you can also use a bank of several ceramic capacitors
connected in parallel. For the example under consideration, 5 times 4.7 µF/50 V capacitors can be placed in
parallel, to fulfill the requirements. As shown in Figure 11, the capacitance value at 40 V is only 2 µF although the
nominal rating is 4.7 µF. To be on the safe side, it is recommended to use 5*2 µT = 10 µF. The major advantage
is the very low ESR value of 2 mΩ.
1
2
Electrolytic
Capacitor
Ceramic
Capacitors
VOUT
VOUT
C OUT
Figure 13
100nF
COUT_bank
1) Electrolytic capacitor with small parallel C and 2) Pure ceramic capacitor bank
Application Note
18
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
Tips:
•
•
•
•
•
•
•
The output capacitance depends on the load and the converter configuration.
In boost configurations, output capacitances are larger than in buck configurations to achieve the same load
current ripple.
Lower operating frequencies will require larger output capacitances.
Output capacitors are selected based on their: capacitance; equivalent series resistance (ESR should be low);
RMS or AC current rating and the DC bias voltage response.
Note that a ceramic capacitor can have a very low capacitance value at the working voltage level! Hence, a
reasonable margin of safety should be considered.
X7R ceramic capacitances should be used: For automotive high-temperature applications, X8R ceramic
capacitors are available.
To improve the EMC, cost and thermal response, a parallel setup of ceramic capacitors is recommended.
(Disadvantage: this is only possible in a reasonable µF range).
6
2.6
Calculation of the input capacitance CIN
The value of the input capacitance CIN of a boost converter is generally selected to limit the input voltage ripple
ΔVIN specified by the application. For continuous inductor current mode operation, the current flowing through CIN
is primarily determined by the inductor ripple current ΔIL. The charge and discharge current of the capacitors is
balanced, and thus, the root mean square (RMS) current flowing through the capacitor is zero.
ICIN
∆IL = 0.4A
+
CCIN_RMS=0.115A
0A
SWITCH = ON
Figure 14
SW=OFF
t
SWITCH = ON
SW=OFF
Current flowing through input capacitor CIN
Note: For the worst case calculation, VIN = 8 V has been considered. Hence, ΔL is at its maximum value.
Application Note
19
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
C @ max.18V = 1.7µF
ESR~5mΩ
f SW=400kHz
VIN=max.18V
Figure 15
CIN: ESR and DC bias of a 2.2 µF/50 V/X7R ceramic capacitor (source Murata:
GRM31CR71H225KA88) Automotive type: GCM31CR71H225KA55
The input capacitor CIN can be calculated as:
C IN ≥
ΔI L ⋅ TSW
8 ⋅ ΔVIN
(35)
C IN ≥
0 .4 A ⋅ 2 .5 µs
= 1 .25 µF
8 ⋅ 100 mV
(36)
RMS current through CIN:
I RMS
_ CIN
=
I RMS _ CIN =
ΔI L
12
(37)
0.4 A
= 0.115 A
12
Application Note
(38)
20
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
Input voltage ripple and ESR value:
Δ V IN = Δ I L ⋅ ESR
(39)
The maximum permissible ESR value can be derived:
ESR ≤
Δ V IN
100 mV
=
= 25 m Ω
ΔI L
0 .4 A
(40)
Selection of input capacitor CIN:
•
•
•
Voltage rating > 18 V: GCM31CR71H225KA55 = 50 V
IRMS > 115 mA: GCM31CR71H225KA55 > 1 A
ESR < 25 mOhm: GCM31CR71H225KA55 = 5 mΩ
Tips:
•
•
SEPIC and boost converters require a lower input capacitance than buck converters
Refer to remarks in the output capacitance section
Application Note
21
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
7
2.7
Switching MOSFET considerations
The major parasitic components are show in the MOSFET equivalent circuit on the right hand side in Figure 16.
Furthermore, the corresponding MOSFET gate charging steps are shown on the left hand side.
Note: Parasitic MOSFET and freewheeling diode effects are not considered in this summary!
Explanation of the different gate charging steps:
•
•
•
•
•
•
•
Before time t0 the gate source voltage VGS is zero and no current flows in the MOSFET.
At time t0 the gate-source voltage VGS starts to increase.
At time t1, the gate-source voltage VGS is equal to the threshold voltage VGS(th) and the current ID begins to flow
in the MOSFET, and until time t2, all the current ID flows in the MOSFET. (
The input capacitance Cgs continues to charge during the time interval t1 - t2.
After time t2 the drain voltage VDS begins to decrease while the drain current ID is constant.
The drain voltage decreases during the interval t2 - t3. At t3 the drain voltage VDS reaches the value RDSon * ID
(where RDSon is the power MOSFET ON resistance and the sum of Rd + Rs).
Towards t3 the gate source voltage VGS can be increased furthermore to drive the ON resistance at an optimum
value.
VGS
Qgate
Qgs
Q gd
Qsw
Drain
Q g(TH)
Id
VGS(TH)
C gd
t
t1
t2
t3
t ,Qgate
Igd
5V
VDS
Ig
Gate
0V
Igs
VDS
VGS
Cgs
Drain Current
Source
ID
Drain Voltage
t
Figure 16
t1
t2
t3
t
MOSFET - Gate charge characteristic
Application Note
22
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
Switch ON timing calculation for a MOSFET:
t ON =
t ON =
Q gate
(41)
I SWO ,SRC
6.5 nC
= 17 .22 ns
380 mA
(42)
Switch OFF timing calculation for a MOSFET:
tOFF =
t OFF =
Qgate
(43)
I SWO,SNK
6.5nC
= 11.82 ns
550 mA
(44)
Drain Voltage
VDS
t
Drain Current
ID
t ID_rise
tVDS_fall
tVDS_rise
t
tOFF
t ON
Figure 17
t ID_fall
MOSFET - Switching time definition
Application Note
23
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
Tips for selecting the power MOSFET:
For the application example under consideration, the Infineon OptiMOS®-T2 power transistor IPD25N06S4L-30
has been selected. Automotive applications require the use of AEC qualified robust MOSFETs with high operating
temperature rating (Tj(max) = 175°C). The crucial MOSFET parameters are shown in Figure 18 below.
•
•
•
•
•
n-channel MOSFETs are used for boost configurations (advantage of simple gate drive), a 5 V gate voltage
compatible device should be selected (example: VGS(th) of 1.7 V).
The MOSFET should have an appropriate RDS(on) to handle the input current flow even during worst case
conditions and to reduce the conduction losses PC.
The MOSFET breakdown voltage V(BR)DSS should be greater than the maximum output voltage (example: VOUT
= 40 V < VDS = 60 V).
The MOSFET should have low value of gate input capacitances and gate charges since this will minimize the
MOSFET’s switching losses PSW and power loss inside the TLD5095/98 PIC (example: QG = 6.5 nC).
Lead-free automotive qualified MOSFETs from Infineon are recommended: Please browse the portfolio on
Infineon’s website: www.infineon.com/automotivemosfet
Figure 18
MOSFET datasheet abstract - IPD25N06S4L-30
Application Note
24
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
2.8
Calculation of power resistor for LED current definition - RFB
The typical reference voltage VREF is 300 mV (specified parameter in product datasheet).
RFB =
VREF
I OUT
(45)
R FB =
0 .3V
= 0 .75 Ω
0 .4 A
(46)
Tips:
•
Isabellenhuette power shunt resistors of the SMS series having 1 % tolerance can be recommended
2.9
Calculation of over-voltage protection resistor divider - ROVL, ROVH
The maximum permissible voltage at the output (VOUT(max)) should be slightly higher than the desired operating
voltage VOUT. To simplify the calculation, the lower value of the over-voltage resistor ROVL is fixed at 1 kΩ. The
internal over-voltage feedback threshold VOVFB,TH is specified in the product datasheet. The typical value is:
VOVFB,TH = 1.25 V. The current flowing through the over-voltage protection resistor divider is:
I OV =
I OV =
VOVFB ,TH
(47)
ROVL
1 .25V
= 1 .25 mA
1kΩ
(48)
Now, you can calculate the upper over-voltage protection resistance. The rough assumption is to apply a little
voltage overhead of 3 V for this estimation VOUT(max) = 43 V.
ROVH =
R OVH =
VOUT ,max
(49)
I OV
43V
= 34 .4 k Ω
1 .25 mA
(50)
The over-voltage resistor divider protects the application at:
V OUT
_ OV
= 1 . 25 V + 43 V = 44 . 25 V
(51)
The internal parameter VOVFB,TH has a spread of +/-3.2%. The external resistor divider should have a tolerance of
1 % (E96 series). This leads to a variation in the protected voltage VOUT_OV of +/-4.2%. Figure 19 below shows the
variation of the protected output voltage. It is important that VOUT < VOUT_OVmin to ensure proper application
according to the maximum output voltage desired.
Application Note
25
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
VOVFB
example: VOUT_OV = 44.25V
VOVP,max
1.25mA
ROVH
TLD5098
OVFB
Overvoltage Protection
ACTIVE
43V
34.4kΩ
VOVFB,TH
9
ROVL
GND
1kΩ
1.25V
1.25V
Overvoltage Protection is
disabled
12
t
∆=±3.1%
Min.
Typ.
Max.
Resistor divider from E96 series = 1% tolerance
= ±4.2%
∆VOUT_OV = ±3.2 % ±1%
= 46.10V
VOUT_Ovmax = 44.25V * 1.042
= 42.39V
VOUT_Ovmin = 44.25V * 0.958
Figure 19
Description of over-voltage protection
Tips:
•
E96 series (1%) resistors recommended
2.10
Output diode selection - DBO
Diode selected for the example:
Schottky diode: 1 A / 50 V
Tips:
•
•
•
•
•
•
The diode must handle the maximum DC output current = IOUT
The minimum reverse voltage should be higher than the max. VOUT voltage
Low leakage current at higher temperatures could be important
Low forward voltage drop (use Schottky diodes)
Diode should react fast (= fast switching)
Package and thermal resistance considerations
Application Note
26
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Calculation of external components for a TLD5095/98 application
2.11
Gate driver buffer capacitance selection - CIVCC
The calculation of the gate buffer capacitance CIVCC is based on the standard capacitance equation:
I =C⋅
dV
dt
(52)
The current in this formula is specified in the TLD5095/98 datasheet and represented by the gate driver peak
sourcing current ISWO,SRC = 380 mA.
The value of dV is the voltage ripple on the regulator output voltage. Let’s assume dV = 20 mV.
The value of dt is the switching ON time of the MOSFET, which is calculated in “Switching MOSFET
considerations” on page 22. tON = 17.22 ns
The buffer capacitance required can be calculated:
C IVCC =
I SWO , SRC ⋅ t ON
dV
=
380 mA ⋅ 17 . 22 ns
= 327 nF
20 mV
(53)
Selection of gate driver buffer capacitance CIVCC:
CIVCC = 1µF/6V
Tips:
•
•
•
CIVCC should have a low ESR
X7R ceramic capacitors should be used: For automotive high-temperature applications, X8R ceramic
capacitors are available.
The parasitic inductance of the capacitor should be as low as possible. Otherwise, the parasitic inductor could
lead to decreasing the gate switch ON time and result in higher switching power losses. The slope control of
the MOSFET should be done with a defined external resistor (e.g. 10 Ohm), if necessary. A parasitic
inductance also creates more ringing on the voltage signal and thus influences the delta voltage on the
regulator output.
Application Note
27
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Stability considerations
8
3
Stability considerations
The TLD5095/98 products feature an external compensation network (RCOMP, CCOMP1, CCOMP2), which can be
adapted to a variety of application boundary conditions and ensure stable switching behavior. All the details for
the dimensioning are explained in the following chapter.
3.1
LED resistance considerations
One crucial parameter for the stability calculation is the output impedance. A resistor value for the LED load must
be defined. This is explained in the figure below.
RLED =
ΔVF
0.4V
=
= 0.67Ω
ΔI F 600mA
(54)
We assume LED forward drop voltage of 3.1 V to reach with 12 LEDs the VOUT = 12 * 3.1 = 40.72 V which is
close to our example VOUT = 40 V.
LW W5SN – OSRAM Platinum DRAGON
ΔI F=600mA
ΔVF =0.4V
Figure 20
LED current versus LED forward voltage (LW W5SN – OSRAM Platinum DRAGON)
Application Note
28
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Stability considerations
3.2
LED forward voltage considerations
Figure 21 below gives an indication of the LED forward voltage variation of a high-brightness LED. In general, the
LED forward voltage VF is dependent on the junction temperature Tj and the load current IF.
At low temperatures, the LED forward voltage has its maximum value (e.g. 4.3 V). In many application
specifications, where LEDs are connected in series, customers request the worst case forward voltage at low
temperatures. This leads to relatively high output voltages and more expensive external components must be
used as a consequence.
Theoretically, this may be correct but it should be always cross-checked if it is really necessary to map worst case
on worst case conditions. In a real application, the LEDs will heat up very fast and the Tj = -40°C is not a continuous
operating condition.
In our example, we select a continuous VF of 3.368V for one single LED (typ. value @ Room Temperature). The
sample application consists of 12 LEDs in series, which results in a VOUT = 40.42V, which is very close to the output
voltage initially assumed by us (VOUT = 40 V).
Note: To be precise the contribution of VREF (0.3V) must be considered as well, to get the proper output voltage:
VOUT = VLED + VREF = 40.42V + 0.3V = 40.72V
LED Forward Voltage V F versus Temperature (IF=700mA)
4,5
VF [V]
4
3,5
VF,min
3
VF,typ
2,5
VF,max
2
‐40
‐20
0
20
40
60
80
100
120
Tj [°C]
Figure 21
LED forward voltage VF over temperature Tj (LW W5SN – OSRAM Platinum DRAGON)
Application Note
29
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Stability considerations
3.3
Stability calculation
Figure 22 below shows the parameter input of a dedicated Excel calculation file. Especially for the stability
calculation, it is more efficient to work with the tools provided to achieve faster results. Nevertheless, one sample
calculation is shown to give a feel of the mathematical calculations used by the Excel tool. More information on
the Excel tool is furnished in “Excel tool for fast evaluation of external components, efficiency and stability”
on page 42.
One way of using the compensation sheet could be:
•
•
•
•
Fill in the yellow parameters such as “application input values”, “LED model characteristic values”, “output RC
network values” according to the values determined by the application dimensioning process.
Try to fill in some initial estimated values for the “compensation network values”. Use the values recommended
in the TLD5095/98 product datasheet and view the stability results.
If the phase margin parameter is below 60°, try to reduce the resistor value RCOMP and increase the value
for CCOMP1 and view the stability results once again.
Repeat this procedure until you have the desired phase margin of > 60° and cross-check the result for the
entire input voltage range.
Note: Sometimes it may be necessary to redefine the input values such as LBO, RSWCS, RESR to achieve optimized
stability.
Parameter
Application Input Values
Input Voltage DC/DC
Boost Inductor
SET Voltage
Feedback Resistor
Symbol
Value
VIN
LBO
VSET
RFB
12
56,0
5
0,750
Over Current Resistor
Rswcs
Switching frequency
fsw
LED Model Characteristic Values
number of LED
n_LED
LED threshold voltage
Vth_LED
single LED Resistor
R_LED
Output RC network Values
Capacitor
Cout
Output Cap. Series Resistor Resr
Compensation network Values
Resistor
Rcomp
Capacitor
Ccomp1
Capacitor
Ccomp2
Output Characteristic
Feedback Reference Voltage Vref
LED Current
ILED
LED Voltage
VLED
Output Voltage
Vout
Duty Cycle
D
LED equivalent Resistor
RL
Load Resistor
Rload
DC Gain Values for small signal model
Gain between VOUT and VFB beta_DC
Error Amplifier Gain
AEA_DC
Current Mode Gain
ACM_DC
Stability results
Open Loop DC Gain
DC_Gain
Cut Frequency
fc
Phase Margin
PM
Figure 22
Unit
V
µH
V
Ohm
0,05 Ohm
400000 Hz
12
3,10 V
0,67 Ohm
10,00 µF
0,01 Ohm
1000 Ohm
47,00 nF
0,00 nF
0,30
0,400
40,42
40,72
0,705
8,04
8,79
V
A
V
V
Ohm
Ohm
0,09
1500,00
9,54
61,73 dB
1400 Hz
73,44 deg
Inputs and numeric results of the Excel compensation sheet
Application Note
30
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Stability considerations
3.4
Closed loop considerations
The TLD5095/98 control logic consists of two control loops. A current control loop, defined by the shunt resistor
RCS, and the voltage control loop, defined by the load current shunt resistor RFB. Internal slope compensation
ensures the loop stability at duty cycles above 50%. The external compensation network RCOMP and CCOMP1
connected in series to ground, plus a parallel capacitor CCOMP2 is needed to achieve a stable application for the
application boundary condition specified.
The main contributors for the closed loop stability are displayed in Figure 23 below. These are primarily the boost
inductor LBO, the output capacitor COUT and its ESR value, the feedback resistor RFB, and the output network RLED
and VLED have an significant impact on the stability. The freewheeling diode parameters Vd and Rd may be ignored.
Note: The ACM Equation (56) describes more than just the current loop amplifier. Current loop, slope
compensation, logic and the booster network (consisting of: COUT and RLED, LBO) itself, are summarized as
highlighted in the dotted area in Figure 23.
RESRL=0Ω
VIN
LBO
Vd =0V; Rd=0Ω
RFB
D
RON =0Ω
LOGIC
Current
Loop
ACM
COUT
RESRC
RSWCS
RLED
+
I
-
Slope Comp
VLED
t
AEA
CCOMP1
CCOMP2
Voltage Loop
RCOMP
Figure 23
TLD5095/98 closed loop schematic
Application Note
31
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Stability considerations
3.4.1
Definition of the open loop gain
The poles of the open loop gain need to be obtained for the stability of a control system. The pole and zero map
is often used to assess the stability of a control system. In general, it can be said that a system is stable if all the
poles are located on the left hand side of the imaginary axis. Refer to Figure 24 to see more details.
Note: Zeros are not influencing the stability of a system!
im
S
X
X
re
X
Stable !
Figure 24
General overview of a pole and zero map
T ≅ ACM ⋅ A EA ⋅ β
(55)
T = Open loop gain
ACM = Amplification of current measurement amplifier (Current loop)
AEA = Amplification of error amplifier (Voltage loop)
β = Feedback network
The feedback network describes the relation between the feedback signal and the output signal.
A CM ≅
0 . 2 ⋅ D ′ ⋅ R load
(1 − τ z 1 ⋅ s ) ⋅ (1 + τ z 2 ⋅ s )
⋅
− n ⋅ V th _ LED ⎞
V
⎛
⎛
s
s2
⎜⎜ 1 + OUT
⎟⎟ ⋅ R swcs (1 + τ p 1 ⋅ s )⋅ ⎜ 1 +
+
⎜
V OUT
ωn ⋅Q ωn2
⎝
⎠
⎝
A EA ≅ 0 . 0006 × R EA ×
(1 + τ
(1 + τ z 3
p2
⋅ s)
⋅ s ) ⋅ (1 + τ
p3
⋅ s)
⎞
⎟
⎟
⎠
(56)
(57)
0.0006 = gmEA "transconductance" of the error amplifier
β≅
RFB
Rload
Application Note
(58)
32
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Stability considerations
3.4.2
Definition of zeros and poles
The following formulas require some parameters that are defined here:
D = 1 − D′
(59)
D′ =
Vin
Vout
(60)
D′ =
Vin
12V
=
= 0.295
Vout 40 .72V
(61)
Rload ≅ RFB + n ⋅ R LED
(62)
Rload ≅ R FB + n ⋅ R LED = 0.75Ω + 12 ⋅ 0.67 Ω = 8.79 Ω
(63)
D’ = inverted switching duty cycle
n = number of LEDs
RLED = forward LED resistor
The system displayed in Figure 3 includes three zeros which are defined as:
τ z1 ≅
L BO
Rload ⋅ D ′ 2
⎛ VOUT − n ⋅ Vth _ LED
⋅ ⎜⎜
VOUT
⎝
⎞
56 µH
⎟⎟ =
8
.
79
Ω ⋅ 0 .295 2
⎠
s
⎛ 40 .72V − 12 ⋅ 3 .1V ⎞
−7
⋅⎜
⎟ = 6 .33 ⋅ 10
40
.
72
V
rad
⎝
⎠
(64)
τ z 2 ≅ C out ⋅ R ESR _ Cout = 10 µF ⋅ 0 .01Ω = 1 ⋅ 10 − 7
s
rad
(65)
τ z 3 ≅ Ccomp1 ⋅ Rcomp = 47 nF ⋅ 1kΩ = 4.7 ⋅ 10 −5
s
rad
(66)
Application Note
33
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Stability considerations
Corresponding to the three zeros, the system includes three poles as well:
τ p1 ≅
C out ⋅ ( R load + 2 ⋅ R ESR _ Cout ) 10 µF ⋅ (8 . 79 Ω + 2 ⋅ 0 . 01 Ω )
s
=
= 8 . 11 ⋅ 10 − 5
40 . 72 V − 12 ⋅ 3 . 1V ⎞
V OUT − n ⋅ V th _ LED ⎞
rad
⎛
⎛
⎜⎜ 1 +
⎟⎟
⎜1 +
⎟
40 . 72 V
⎝
⎠
V OUT
⎝
⎠
(67)
REA = internal resistor of error amplifier
REA ≅ 2.5 MΩ (for TLD5098)
REA ≅ 47 MΩ (for TLD5095)
REA >> RCOMP
Note: CCOMP1 >> CCOMP2
τ p 2 ≅ (C comp 1 + C comp 2 )⋅ R EA = (47 nF + 0 nF ) ⋅ 2.5 M Ω = 1.18 ⋅10 −1
τ p 3 ≅ C comp 2 ⋅ Rcomp = 0 nF ⋅ 1kΩ = 0
Application Note
s
rad
s
rad
(68)
(69)
34
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Stability considerations
3.4.3
Definition of the slope compensation parameters and quality factor Q
The slope compensation parameters (ωn, Q, mc, Se, Sn) for the current loop model is based on R.B. Ridley.
[1]
Reference: Ridley, R.B.; “A New Continuos Time Model for Current Mode Control”; IEEE Transaction on
Power Electronics; Vol. 6; Issue 2; pp. 271-280; 1991.
Note: For the stability of the system it is necessary that the quality factor Q is positive!
Se =
50 ⋅ 10 − 6 A 50 ⋅ 10 − 6 A
A
=
= 20
2 . 5 µs
T SW
s
(70)
TSW = switching period
Se = internal slope compensation
S n = 0 .001 ⋅
V IN
12V
A
⋅ R swcs = 0 .001 ⋅
⋅ 50 m Ω = 10 .71
56 µH
L BO
s
(71)
Sn = Slope of the ON period of the switch
A
20
Se
s = 2.87
mc = 1 +
= 1+
A
Sn
10.71
s
Q≅
(72)
1
1
=
= 0.92
π ⋅ (mc ⋅ D′ − 0.5) π ⋅ (2.87 ⋅ 0.295 − 0.5)
(73)
Q = Quality factor of the overshoot
3.4.4
Open loop gain calculations
ACM (0) ≅
0.2 ⋅ D ′ ⋅ Rload
0.2 ⋅ 0.295 ⋅ 8.79 Ω
=
= 9.54
⎛ 40 .72V − 12 ⋅ 3.1V ⎞
⎛ VOUT − n ⋅ Vth _ LED ⎞
1
+
⋅
0
.
05
Ω
⎟⎟ ⋅ R swcs ⎜
⎟
⎜⎜1 +
40 .72V
⎝
⎠
VOUT
⎠
⎝
AEA (0) ≅ 0.0006 ⋅ REA = 0.0006 ⋅ 2.5MΩ = 1500
β≅
(74)
(75)
RFB 0.75Ω
=
= 0.0853
Rload 8.79Ω
(76)
T ( 0) ≅ ACM ⋅ AEA ⋅ β = 9.54 ⋅1500 ⋅ 0.0853 = 1220 .64
(77)
T (0) | dB = 20 ⋅ log(1220.64) = 61.73dB
(78)
Application Note
35
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Stability considerations
3.5
Calculation of the phase margin:
Good practice for a proper phase margin value is > 60°. If the phase margin is lower, the system has a faster
response time and oscillations can occur (the f cross-over is also higher in that case). A more gentle switching
response can be achieved by increasing the phase margin.
Systemspeed: Fast
PM: 16° = Low
Systemspeed: Medium
PM: 73° = OK
Systemspeed: Slow
PM: 92° = OK
1 / fc
Stability results
Open Loop DC Gain
Cut Frequency
Phase Margin
Gain Margin
DC_Gain
fc
PM
GM
61,73
5500
15,94
13,68
dB
Hz
deg
dB
RCOMP =1.1kΩ
CCOMP1 = 4.7nF
Figure 25
Stability results
Open Loop DC Gain
Cut Frequency
Phase Margin
Gain Margin
DC_Gain
fc
PM
GM
61,73
1400
73,45
27,39
dB
Hz
deg
dB
Stability results
Open Loop DC Gain
Cut Frequency
Phase Margin
Gain Margin
RCOMP =1.0kΩ
CCOMP1 = 47nF
DC_Gain
fc
PM
GM
61,73
760
92,48
27,42
dB
Hz
deg
dB
RCOMP =1.0kΩ
CCOMP1 =100nF
Response of fast and slow systems
This can be achieved by changing the compensation network values. A dedicated Excel file for the stability
estimation is of great help to figure out the proper compensation network values RCOMP, CCOMP1, CCOMP2. The Excel
sheet itself features a built-in function which indicates a green label for the phase margin if it is in the proper range
for a stable application. In addition, a Bode plot is provided to see the phase and gain slopes directly as illustrated
in Figure 26 below. The crossover frequency fcross_over is defined as the value when the gain slope intersects the
0 dB line. The phase margin PM of the system is obtained at the fcross_over point.
f cross
_ over
≅
T (0)
1220 .64
=
≅ 1653 Hz
2 ⋅ π ⋅ C comp 1 ⋅ R EA 2 ⋅ π ⋅ 47 nF ⋅ 2 .5 M Ω
ωc _ o = 2 ⋅ π ⋅ fcross _ over = 2 ⋅ π ⋅1653 Hz = 10386
(79)
rad
s
(80)
φm =180− tan−1(ωc0 ⋅τ p1 ) − tan−1(ωc0 ⋅τ p2 ) − tan−1(ωc0 ⋅τ p3 ) − tan−1(ωc0 ⋅τ z1 ) + tan−1(ωc0 ⋅τ z2 ) + tan−1(ωc0 ⋅τ z3 )
(81)
φ m = 180 ° − 40 . 1 ° − 89 . 95 ° − 0 ° − 3 . 76 ° + 0 . 06 ° + 26 ° = 72 . 25 °
(82)
Note: The deviations between the calculated values and the results in the Excel sheet are attributable to
differences on account of rounding up!
Application Note
36
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Stability considerations
TLD5095/98 CCM Bode plot
90
60
30
0db - Line 0
-30
-60
-90
-120
-150
-180
-210
-240
-270
-300
-330
-360
0,01
fc=1400Hz
PM=180°-106.56°=73.44°
Open Loop Gain (dB)
Open Loop Phase (deg)
0,1
1
10
100
1000
10000
100000 1000000 10000000
Frequency (Hz)
Figure 26
Bode plot
Application Note
37
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Power loss and system efficiency
9
4
Power loss and system efficiency
After dimensioning and careful selection of the external components the overall power loss and system efficiency
can be calculated. This chapter describes in detail how the power dissipation for each component can be obtained.
The typical application input voltage VIN = 12 V is considered for the calculations.
Figure 27
Power loss summary
Figure 28
System efficiency and single power loss contribution slopes
Application Note
38
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Power loss and system efficiency
4.1
TLD5095/98 IC Power Losses - PIC
There are various power dissipating blocks integrated in the DC/DC controller IC.
1) Losses of the integrated voltage regulator - PLDO:
It is necessary to calculate the average value of current required by the internal LDO.
I VCC _ RMS = Qg ⋅ f SW
(83)
IVCC_ RMS = 6.5nC ⋅ 400kHz = 2.6mA
(84)
PLDO = (VIN − VIVCC ) ⋅ I VCC _ RMS
(85)
PLDO = (12V − 5V ) ⋅ 2.6mA = 18.2mW
(86)
2) Gate charge losses: Pgate_charge:
Pgate _ ch arg e = VIVCC ⋅ IVCC _ RMS
(87)
Pgate _ ch arg e = 5V ⋅ 2.6 mA = 13mW
(88)
3) Quiescent current consumption losses - PQ:
PQ = VIN ⋅ I q _ on
(89)
PQ = 12V ⋅ 7 mA = 0.084W
(90)
Total IC losses:
PIC = PLDO + Pgate _ ch arg e + PQ = 115 .2 mW
Application Note
(91)
39
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Power loss and system efficiency
4.2
Power MOSFET - PMOSFET
The power MOSFET losses are split up between:
1) Conduction losses PC:
2
PC = D ⋅ I IN ⋅ R DS ( on )
(92)
PC = 0.70 ⋅ 1.33 A 2 ⋅ 30 m Ω = 37 .33 mW
(93)
2) Switching losses PSW:
PSW = 0.5 ⋅VOUT ⋅ I IN ⋅ (tON + tOFF ) ⋅ f SW
(94)
PSW = 0.5 ⋅ 40V ⋅1.33 A ⋅ (39.5ns + 27.3ns ) ⋅ 400 kHz = 308 .52 mW
(95)
The total MOSFET losses are:
PMOSFET = PC + PSW = 37.33mW + 308.52mW = 345.85mW
4.3
(96)
LED current feedback resistor power loss - PRFB
2
PRFB = I OUT ⋅ RFB
(97)
PRFB = 0 . 4 A 2 ⋅ 0 . 75 Ω = 0 . 12 W
(98)
4.4
Switch current sensing resistor power loss - PRCS
2
PRCS = D ⋅ I IN ⋅ R CS
(99)
PRCS = 0.70 ⋅ 1.33 A2 ⋅ 0.05Ω = 0.062W
4.5
(100)
Inductor power loss - PLBO
2
PLBO = I L, AVG ⋅ DCR
(101)
PLBO = 1.33A2 ⋅ 0.0802Ω = 142.58mW
(102)
Application Note
40
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Power loss and system efficiency
4.6
Input capacitor power loss - PCIN
2
PCIN = I RMS ⋅ ESR
(103)
PCIN = 0 . 115 A 2 ⋅ 0 . 005 Ω = 10 µW
(104)
4.7
Output capacitor power loss - PCOUT
2
PCOUT = I RMS _ COUT ⋅ ESR
(105)
PCOUT = 0 .61 A 2 ⋅ 0 .01Ω = 3 .73 mW
(106)
4.8
Freewheeling diode power loss - PDBO
Pdiode = I OUT ⋅ VFW
(107)
Pdiode = 0.4 A ⋅ 0.4V = 160mW
(108)
Application Note
41
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Design-in tools
10
5
Design-in tools
Dimensioning and design efforts could become a very time-consuming task, particularly for switched mode power
supply applications. To reduce the development cycle, design-in tools are well appreciated by customers, and
Infineon provides several tools and guidelines to ensure streamlined design-in activity for the TLD5095/98 DC/DC
controller ICs.
5.1
Excel tool for fast evaluation of external components, efficiency and stability
All the equations that have been summarized and described in this application note have been incorporated in a
dedicated Excel sheet. This Excel tool supports the dimensioning, stability, and power loss and efficiency
considerations very clearly. Last but not least, it is possible to export all results into a PDF document, which can
be used as a design summary for permanent application documentation. The application note in combination with
the Excel tool should provide a focused and fast approach for the proper design of a TLD5095/98 application.
Figure 29
Excel sheet calculator for application dimensioning and stability
Application Note
42
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Design-in tools
5.2
Electrical and thermal simulation
A PSPICE model could be very beneficial to get an initial impression of the system response. After the
dimensioning process, a quick crosscheck of the application response could save costs by reducing hardware
development cycles. Stability and switching response can be investigated easily with the help of the PSPICE
models of the TLD5095/98 ICs provided. A complete test bench including discrete components, the DC/DC
converter and the MOSFET can be provided on request. It is also worth mentioning that the comprehensive
Infineon MOSFET portfolio also features dedicated PSPICE models that could be included in such a test bench.
Infineon website: www.infineon.com/automotivemosfet
In addition to electrical simulation, it becomes increasingly important to estimate the thermal performance of a
system. It is recommended to run thermal simulations (e.g. Flotherm) or other appropriate tools to study the
thermal response of a rough layout. The maximum ratings of the components used must not be exceeded!
Figure 30
Simulation tools and support
Application Note
43
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Design-in tools
5.3
Demo boards for fast evaluation in the lab & onboard LED chain
Another step in the evaluation of the TLD5095/98 products could be to conduct real measurements on a plug &
play hardware such as the evaluation kit. The DC/DC layout has been reused from our EMC test PCB. All pins of
the ICs can be easily connected with the help of banana cables to the measuring instruments, load and power
supply equipment.
The evaluation kit features onboard LEDs (max. 8 LEDs in series, reconfigurable to only 1 LED in series for buck
boost configurations). In addition, there is the feature of driving real loads via dedicated ports (4 mm banana
sockets). You can switch between onboard LEDs and the external load using a simple switch on the demo board.
As illustrated in Figure 31 below, the Evaluation Kit can be ordered for two different configurations.
1. One demo board features the standard boost to GND application and a SEPIC configuration can be realized
with simple adaptation of the external circuitry. In addition, both, the B2G and the SEPIC can be driven in a
constant voltage mode.
2. The second demo board features a boost to battery configuration, which is needed to achieve a BUCK-BOOST
response and connect a single LED or several LEDs in a string. Constant voltage mode regulation is also
possible for this configuration after simple modification of the external components on the demo board.
The TLD5095/98 demo boards enable quick evaluation of the products under real application conditions at the
work bench level and can be ordered from our local sales team.
Figure 31
Plug & play demo boards for getting started in the laboratory
Application Note
44
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Design-in tools
5.4
Sample layouts for small application boards
In addition to the evaluation kit for fast evaluation of the products, dedicated EMC and size-optimized application
PCBs are available. These application boards are dedicated to one specific configuration such as the standard
boost to GND or SEPIC configurations. The size of the application boards is 4.5 cm x 4 cm and the connections
to the power supply and external load can be established with cables.
To simulate real load conditions, Infineon has also developed a general purpose LED board. The LED load board
features up to 20 LEDs in series or can be configured in parallel connection as well to simulate multi-channel light
sources.
The application boards in combination with real loads or the Infineon load board enable fast and realistic
application prototyping and could be very beneficial for constructing initial system demonstrators. The layout of
these boards is optimized for EMC and can be reused for customer applications.
Figure 32
Small versatile application boards and EMC optimized layouts
Application Note
45
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Design-in tools
5.5
EMC test reports and results summary
The EMC behavior of switched mode power supplies is considered as one of the most crucial topics during the
design-in activities. All OEMs specify different limits which must be complied with by the application. The Infineon
EMC investigation clearly takes care of the OEM and customer specifications and provides comprehensive
reports.
The EMC reports consist of conducted and radiated emissions, immunity response, and ISO pulses.
In some cases, dedicated filter and countermeasures are described to improve the EMC behavior further as well
as to provide guidelines to the reader for a proper EMC design.
Figure 33
•
EMC test reports and results summary
For further information, please contact http://www.infineon.com/
Application Note
46
V1.3, 2011-08-08
TLD5095 / TLD5098
Dimensioning and Stability Guideline - Theory and Practice
Revision history
6
Revision history
Revision History: V1.3, 2011-08-08
Previous version(s):
1.0, 1.1, 1.2
Page
Subjects (major changes since last revision)
all
Editorial Changes
Application Note
47
V1.3, 2011-08-08
Edition 2011-08-08
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2011 Infineon Technologies AG
All Rights Reserved.
LEGAL DISCLAIMER
THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE IMPLEMENTATION
OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY
DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY, CONDITION OR QUALITY OF THE
INFINEON TECHNOLOGIES COMPONENT. THE RECIPIENT OF THIS APPLICATION NOTE MUST VERIFY
ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION. INFINEON TECHNOLOGIES HEREBY
DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND (INCLUDING WITHOUT
LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY
THIRD PARTY) WITH RESPECT TO ANY AND ALL INFORMATION GIVEN IN THIS APPLICATION NOTE.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
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Infineon Technologies components may be used in life-support devices or systems only with the express written
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