V6208604

REVISIONS
LTR
DESCRIPTION
DATE
Prepared in accordance with ASME Y14.24
APPROVED
Vendor item drawing
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PMIC N/A
PREPARED BY
Phu H. Nguyen
Original date of drawing
YY MM DD
CHECKED BY
08-01-07
Phu H. Nguyen
APPROVED BY
Thomas M. Hess
SIZE
A
REV
AMSC N/A
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CODE IDENT. NO.
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DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
TITLE
MICROCIRCUIT, DIGITAL, CMOS, DUAL
DIGITALLY CONTROLLED POTENTIOMETERS,
MONOLITHIC SILICON
DWG NO.
V62/08604
16236
PAGE
1
OF
12
5962-V013-08
1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance dual digitally controlled potentiometers
microcircuit, with an operating temperature range of -55°C to +125°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/08604
-
Drawing
number
01
X
E
Device type
(See 1.2.1)
Case outline
(See 1.2.2)
Lead finish
(See 1.2.3)
1.2.1 Device type(s).
Device type
Generic
01
ISL22326
Circuit function
Dual digitally controlled potentiometers
1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter
Number of pins
X
14
JEDEC PUB 95
Package style
MO-153
Plastic small outline
1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture:
Finish designator
A
B
C
D
E
Z
1.3 Absolute maximum ratings.
Material
Hot solder dip
Tin-lead plate
Gold plate
Palladium
Gold flash palladium
Other
1/
Supply voltage range ( VCC ) .................................................................................................
Voltage at any digital interface pin with respect to GND .......................................................
Voltage at any DCP pin with respect to GND .......................................................................
Lead temperature (Soldering, 10s) .......................................................................................
IW (10s) ................................................................................................................................
Latchup ...............................................................................................................................
Storage temperature range (TSTG) ........................................................................................
ESD :
(HBM) ...........................................................................................................................
(CDM) ...........................................................................................................................
Thermal resistance ( θJA ) (case X) ......................................................................................
1/
2/
3/
-0.3 V to 6.0 V
-0.3 V to VCC + 0.3 V
-0.3 V to VCC
300°C
±6 mA
Class II, Level B @ +125°C 2/
-65°C to 150°C
2.5 kV
1 kV
100°C/W
3/
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied.
JEDEC class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5 V on the
SHDN pin, and using a max negative pulse of -0.8 V for all pins.
θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See manufacturer
data for more information.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
CODE IDENT NO.
DWG NO.
A
16236
V62/08604
REV
PAGE
2
1.4 Recommended operating conditions.
Supply voltage range ( VCC ) .....................................................................................................
Power rating of each DCP ........................................................................................................
Wiper current of each DCP ......................................................................................................
Operating free-air temperature range ( TA )...............................................................................
2.7 V to 5.5 V
5 mW
±3.0 mA
-55°C to +125°C
2. APPLICABLE DOCUMENTS
JEDEC PUB 95
–
Registered and Standard Outlines for Semiconductor Devices
(Applications for copies should be addressed to the Electronic Industry Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834
or at http://www.jedec.org)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.
Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are
as specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Block diagram. The block diagram shall be as shown in figure 3.
3.5.4 Timing waveforms. The timing waveforms shall be as shown in figure 4.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
CODE IDENT NO.
DWG NO.
A
16236
V62/08604
REV
PAGE
3
TABLE I. Electrical performance characteristics. 1/
Test
RH to RL resistance
RH to RL resistance tolerance
Symbol
RTOTAL
End to end temperature coefficient
Wiper resistance
VRH and VRL terminal voltage
Potentiometer capacitance
RW
Limits
Conditions
2/
unless otherwise specified
W option
W option
W option
Min
3/
Unit
Max
10 TYP
-20
+20
±50 TYP
3/
200
VCC = 3.3 V, TA = +25°C,
wiper current = VCC/RTOTAL
VRH and VRL to GND
kΩ
%
ppm/°C
16/
Ω
VRH, VRL
0
VCC
V
CH/ CL/ CW
10/ 10/ 25 TYP
pF
3/
Leakage on DCP pins
ILkgDCP
Voltage at pin from GND to VCC
1
µA
Voltage divider mode (0V @ RLi; VCC @RHi; measured at RW i, unloaded; I = 0 or 1)
LSB
Integral non-linearity
INL 4/
Monotonic over all tap positions
-1
1
5/
Differential non linearity
DNL 6/
Monotonic over all tap positions
-1
1
Zero scale error
ZSerror 7/ W option
0
5
Full scale error
FSerror 8/ W option
-5
0
-2
2
DCP to DCP matching
VMATCH
Any two DCPs at same tap position, same
voltage at all RH terminals, and same
9/
voltage at all RL terminals.
Ratiometric temperature coefficient
TCV 3/
DCP register set to 40 hex
±4 TYP
ppm/°C
10/
Resistor mode (Measurements between RW i and RLi with RHi not connected, or between RW i and RHi with RLi not connected, I = 0 or 1)
MI
Integral non-linearity
RINL 11/ DCP register set between 10h and 7Fh;
-1
1
12/
monotonic over all tap positions
Differential non-linearity
RDNL 13/ DCP register set between 10h and 7Fh;
-1
1
monotonic over all tap positions
Offset
Roffset 14/ W option
0
5
DCP to DCP matching
RMATCH 15/ Any two DCPs at the same tap position
-2
2
with the same terminal voltages
See footnote at end of table.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
CODE IDENT NO.
DWG NO.
A
16236
V62/08604
REV
PAGE
4
TABLE I. Electrical performance characteristics – Continued . 1/
Test
Symbol
VCC Supply current (volatile
write/read)
ICC1
VCC Supply current (nonvolatile write/read)
ICC2
VCC current (standby)
Isb
VCC current (shutdown)
Isd
Leakage current at pins A0,
ILkgDig
Limits
Conditions
2/
unless otherwise specified
Unit
Min
fSCL = 400 kHz; SDA = Open;
(for I2C, active, read and write states)
fSCL = 400 kHz; SDA = Open;
(for I2C, active, read and write states)
VCC = 5.5 V @ I2C interface in standby state
2
VCC = 3.6 V @ I C interface in standby state
VCC = 5.5 V @ I2C interface in standby state
2
VCC = 3.6 V @ I C interface in standby state
Voltage at pin from GND to VCC
Max
0.5
mA
3
µA
7
5
5
4
1
-1
A1, A2, SHDN , SDA, and SCL
DCP wipe response time
tWRT 3/
SCL falling edge of last bit of DCP data byte to wiper
new position
1.5 TYP
DCP recall time from shutdown
mode
tShdnRec
From rising edge of SHDN signal to wiper stored
position and RH connection
SCL falling edge of last bit of ACR data byte to wiper
stored position and RH connection
Minimum VCC at which memory recall occurs
1.5 TYP
Power on recall voltage
VCC ramp rate
Power up delay
EEPROM specification
EEPROM endurance
EEPROM retention
EEPROM retention
EEPROM retention
Non-volatile write cycle time
3/
Vpor
VCCRamp
tD
µs
1.5 TYP
2.6
V
V/ms
ms
0.2
VCC above Vpor, to DCP initial value register recall
completed, and I2C interface stand by state
3
1,000,000
50
15
10
Temperature T ≤ 55°C
Temperature T ≤ 90°C
Temperature T ≤ 125°C
tWC
17/
Cycles
Years
20
ms
V
Serial interface specs
A2, A1, A0, SHDN , SDA, and
SCL input buffer LOW voltage
VIL
-0.3
0.3*VCC
A2, A1, A0, SHDN , SDA, and
SCL input buffer LOW voltage
SDA and SCL input buffer
Hysteresis
VIL
0.7*VCC
VCC+0.3
Hysteresis
0.05*VCC
See footnote at end of table.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
CODE IDENT NO.
DWG NO.
A
16236
V62/08604
REV
PAGE
5
TABLE I. Electrical performance characteristics – Continued . 1/
Test
Serial interface specs - Cotinued
SDA output buffer LOW voltage,
Sinking 4 mA
Symbol
Limits
Conditions
2/
unless otherwise specified
Cpin
3/
Clock LOW time
Clock HIGH time
START condition setup time
tLOW
tHIGH
tSU:STA
START condition hold time
tHD:STA
Input data setup time
tSU:DAT
Input data hold time
tSU:DAT
STOP condition setup time
tSU:STO
STOP condition hold time for Read or
Volatile only Write
Output data hold time
tHD:STO
fSCL
tsp
SDA and SCL rise time
tR
SDA and SCL fall time
tF
From 70% to 30% of VCC
A2, A1 and A0 setup time
A2, A1, and A0 hold time
Max
0
0.4
tAA
tBUF
tDH
Cb
Rpu
tSU:A
tHD:A
V
10 TYP
Any pulse narrower than the max spec is
suppressed
SCL falling edge crossing 30% of VCC, until SDA
exits the 30% to 70% of VCC window
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC during the
following START condition
Measured at the 30% of VCC crossing
Measured at the 30% of VCC crossing
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
From SDA falling edge crossing 30% of VCC to
SCL falling edge crossing 70% of VCC
From SDA exiting the 30% to 70% of VCC window,
to SCL rising edge crossing 30% of VCC
From SCL rising edge crossing 70% of VCC to
SDA entering the 30% to 70% of VCC window
From SCL rising edge crossing 70% of VCC, to
SDA rising edge crossing 30% of VCC
From SDA rising edge to SCL falling edge; both
crossing 70% of VCC
From SCL falling edge crossing 30% of VCC, until
SDA enters the 30% to 70% of VCC window
From 30% to 70% of VCC
Capacitive loading of SDA or SCL
SDA and SCL bus pull up resistor off
chip
Min
VOL
A2, A1, A0, SHDN , SDA, and SCL
pin capacitance
SCL frequency
Pulse width suppression time at SDA
and SCL inputs
SCL falling edge to SDA output data
valid
Time the bus must be free before the
start of a new transmission
Unit
Total on chip and off chip
Maximum is determined by tR and tF
For Cb = 400 pF, max is about 2 ~ 2.5 kΩ
For Cb = 40 pF, max is about 15 ~ 20 kΩ
Before START condition
After STOP condition
pF
400
50
kHz
ns
900
1300
1300
600
600
600
100
0
600
1300
0
20 +
0.1*Cb
20 +
0.1*Cb
10
1
250
250
400
pF
kΩ
ns
600
600
See footnote at end of table.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
CODE IDENT NO.
DWG NO.
A
16236
V62/08604
REV
PAGE
6
TABLE I. Electrical performance characteristics – Continued . 1/
1/
Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may
not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.
2/
Over recommended operating conditions. All typical values are for TA = +25°C and 3.3 V supply voltage.
3/
This parameter is not 100% tested.
4/
INL = [V(RW)i – i * LSB – V(RW)0]/LSB for i = 1 to 127.
5/
LSB:[V(RW )127 – V(RW )0]/127. V(RW )127 and V(RW )0 are V(RW ) for the DCP register set to 7F hex and 00 hes respectively. LSB
is the incremental voltage when changing from one tap to an adjacent tap.
6/
DNL = [V(RW )i – V(RW )i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting.
7/
ZS error = V(RW )0/LSB.
8/
FS error = :[V(RW )127 – VCC]/LSB.
9/
VMATCH = [V(RWx)i – V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 1 and y = 0 to 1.
10/
TCV =
Max( V(RW )i ) − Min( V(RW )i )
106
x
[Max( V(RW )i ] + Min( V(RW )i ] / 2
165°C
for i = 16 to 112 decimal, T = -40°C to + 125°C. Max() is the maximum value
of the wiper voltage and Min() is the minimum value of the wiper voltage over
the temperature range
11/
RINL = [RWi – M(MI * i) – RW0]/MI for I = 16 to 127.
12/
MI = [RW127 – RW0]/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to
7F hex and 00 hex respectively.
13/
RDNL = [RWi – RWi-1]/MI-1, for i = 16 to 127.
14/
Roffset = RW0/MI, when measured between RW and RL.
Roffset = RW127/MI when measured between RW and RH.
15/
RMATC = (RWi,x – RWi,y)/MI, for i = 1 to 127, x = 0 to 1 and y = 0 to 1.
16/
TCR =
Max(Ri) − Min(Ri)
106
x
[Max(Ri) + Min(Ri)] / 2
165°C
for i = 16 to 112, T = -40°C to + 125°C. Max() is the maximum value of the resistance
and Min() is the minimum value of the resistance over the temperature range
17/
tWC is the time from a valid STOP condition at the end of a Write sequence I2C serial interface, to the end of the self timed
internal non-volatile write cycle.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
CODE IDENT NO.
DWG NO.
A
16236
V62/08604
REV
PAGE
7
Case X
Symbol
A
A1
A2
b
c
D
Dimension
Millimeters
Symbol
Min
Max
1.20
e
0.05
0.15
E
0.80
1.05
E1
0.19
0.30
L
0.09
0.20
α
4.95
5.05
Millimeters
Min
Max
0.65 BSC
4.30
4.50
6.25
6.50
0.45
0.75
0o
8o
NOTES:
1. These package dimensions are within allowable dimensions of JEDEC MO-153 AC.
2. Body dimensions do not include mold flash, protrusion or gate burrs. Mold flash, protrusion or gate burrs shall not exceed
0.15 mm per side.
3. “L” is the length of terminal for soldering to a substrate.
4. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08 mm total in excess of “b”
dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07 mm.
FIGURE 1. Case outline.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
CODE IDENT NO.
DWG NO.
A
16236
V62/08604
REV
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8
Case X
Terminal
number
1
2
Terminal
symbol
VCC
SHDN
Terminal
number
8
9
Terminal
symbol
SDA
GND
3
4
5
6
7
RH0
RL0
RW0
A2
SCL
10
11
12
13
14
RW1
RL1
RH1
A0
A1
FIGURE 2. Terminal connections.
FIGURE 3. Block diagram.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
CODE IDENT NO.
DWG NO.
A
16236
V62/08604
REV
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FIGURE 4. Timing waveforms.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
CODE IDENT NO.
DWG NO.
A
16236
V62/08604
REV
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10
FIGURE 4. Timing waveforms - Continued.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
CODE IDENT NO.
DWG NO.
A
16236
V62/08604
REV
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4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,
classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item.
1/
2/
Vendor item drawing
administrative control
number 1/
Device
manufacturer
CAGE code
Vendor part number
V62/08604-01XE
34371
ISL22326WMVEP
Top side
Marking
2/
22326WMVEP
The vendor item drawing establishes an administrative control number for identifying
the item on the engineering documentation.
Add –TK suffix to vendor part number for 1000 piece quantity with tape and reel packaging
option.
CAGE code
34371
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
Source of supply
Intersil Corporation
1001 Murphy Ranch Road
Milpitas, CA 95035-5680
Point of contact: 2401 Palm Bay Blvd.
P.O. Box 883
Melbourne, FL 32902-0883
SIZE
CODE IDENT NO.
DWG NO.
A
16236
V62/08604
REV
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