Data Sheet

PSMN025-80YL
N-channel 80 V, 25 mΩ logic level MOSFET in LFPAK56
14 April 2016
Product data sheet
1. General description
Logic level N-channel MOSFET in an LFPAK56 (Power SO8) package using TrenchMOS
technology. This product is designed and qualified for use in a wide range of power
supply & motor control equipment.
2. Features and benefits
•
•
•
•
Advanced TrenchMOS provides low RDSon and low gate charge
Logic level gate operation
Avalanche rated, 100% tested
LFPAK provides maximum power density in a Power SO8 package
3. Applications
•
•
•
•
•
Synchronous rectification in power supply equipment
Chargers & adaptors with Vout < 10 V
Fast charge & USB-PD applications
Battery powered motor control
LED lighting & TV backlight
4. Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage
25 °C ≤ Tj ≤ 175 °C
-
-
80
V
ID
drain current
VGS = 5 V; Tmb = 25 °C; Fig. 2
-
-
37
A
Ptot
total power dissipation
Tmb = 25 °C; Fig. 1
-
-
95
W
VGS = 5 V; ID = 10 A; Tj = 25 °C; Fig. 11
-
22.2
27
mΩ
ID = 10 A; VDS = 64 V; VGS = 5 V;
-
5.8
-
nC
Static characteristics
RDSon
drain-source on-state
resistance
Dynamic characteristics
QGD
gate-drain charge
Tj = 25 °C; Fig. 13; Fig. 14
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PSMN025-80YL
NXP Semiconductors
N-channel 80 V, 25 mΩ logic level MOSFET in LFPAK56
5. Pinning information
Table 2.
Pinning information
Pin
Symbol Description
Simplified outline
1
S
source
2
S
source
3
S
source
4
G
gate
mb
D
mounting base; connected to
drain
Graphic symbol
D
mb
G
mbb076
S
1 2 3 4
LFPAK56; PowerSO8 (SOT669)
6. Ordering information
Table 3.
Ordering information
Type number
Package
PSMN025-80YL
Name
Description
Version
LFPAK56;
Power-SO8
Plastic single-ended surface-mounted package
(LFPAK56; Power-SO8); 4 leads
SOT669
7. Marking
Table 4.
Marking codes
Type number
Marking code
PSMN025-80YL
025L80
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
25 °C ≤ Tj ≤ 175 °C
-
80
V
VDGR
drain-gate voltage
RGS = 20 kΩ
-
80
V
VGS
gate-source voltage
-20
20
V
Ptot
total power dissipation
Tmb = 25 °C; Fig. 1
-
95
W
ID
drain current
VGS = 5 V; Tmb = 25 °C; Fig. 2
-
37
A
VGS = 5 V; Tmb = 100 °C; Fig. 2
-
26.5
A
pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3
-
150
A
-55
175
°C
IDM
peak drain current
Tstg
storage temperature
PSMN025-80YL
Product data sheet
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PSMN025-80YL
NXP Semiconductors
N-channel 80 V, 25 mΩ logic level MOSFET in LFPAK56
Symbol
Parameter
Conditions
Tj
junction temperature
Min
Max
Unit
-55
175
°C
Source-drain diode
IS
source current
Tmb = 25 °C
-
37
A
ISM
peak source current
pulsed; tp ≤ 10 µs; Tmb = 25 °C
-
150
A
-
45.4
mJ
Avalanche ruggedness
EDS(AL)S
non-repetitive drain-source
avalanche energy
ID = 37 A; Vsup ≤ 80 V; RGS = 50 Ω;
[1][2]
VGS = 5 V; Tj(init) = 25 °C; unclamped;
Fig. 4
[1]
[2]
Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
Refer to application note AN10273 for further information.
03aa16
120
ID
(A)
Pder
(%)
003aaj005
40
30
80
20
40
10
0
Fig. 1.
0
50
100
150
Tmb (°C)
Normalized total power dissipation as a
function of mounting base temperature
PSMN025-80YL
Product data sheet
0
200
Fig. 2.
0
30
90
120
150
Tmb (°C)
180
Continuous drain current as a function of
mounting base temperature
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PSMN025-80YL
NXP Semiconductors
N-channel 80 V, 25 mΩ logic level MOSFET in LFPAK56
ID
(A)
003aaj007
103
Limit RDSon = VDS / ID
102
tp = 10 us
10
100 us
DC
1
1 ms
10 ms
100 ms
10-1
10-2
Fig. 3.
1
102
10
VDS (V)
103
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
IAL
(A)
003aaj006
102
(1)
10
(2)
1
(3)
10-1
10-2
10-3
Fig. 4.
10-2
10-1
1
tAL (ms)
10
Avalanche rating; avalanche current as a function of avalanche time
9. Thermal characteristics
Table 6.
Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance
from junction to
mounting base
Fig. 5
-
-
1.58
K/W
PSMN025-80YL
Product data sheet
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PSMN025-80YL
NXP Semiconductors
N-channel 80 V, 25 mΩ logic level MOSFET in LFPAK56
003aai733
10
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
10-1
P
0.05
0.02
δ=
Fig. 5.
T
single shot
tp
10-2
10-6
tp
10-5
10-4
10-3
10-2
10-1
t
T
tp (s)
1
Transient thermal impedance from junction to mounting base as a function of pulse duration
10. Characteristics
Table 7.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
80
-
-
V
ID = 250 µA; VGS = 0 V; Tj = -55 °C
72
-
-
V
gate-source threshold
voltage
ID = 1 mA; VDS=VGS; Tj = 25 °C; Fig. 9;
1.4
1.7
2.1
V
ID = 1 mA; VDS=VGS; Tj = -55 °C; Fig. 9
-
-
2.45
V
ID = 1 mA; VDS=VGS; Tj = 175 °C; Fig. 9
0.5
-
-
V
VDS = 80 V; VGS = 0 V; Tj = 25 °C
-
0.1
1
µA
VDS = 80 V; VGS = 0 V; Tj = 175 °C
-
-
500
µA
VGS = 16 V; VDS = 0 V; Tj = 25 °C
-
2
100
nA
VGS = -16 V; VDS = 0 V; Tj = 25 °C
-
2
100
nA
VGS = 5 V; ID = 10 A; Tj = 25 °C; Fig. 11
-
22.2
27
mΩ
VGS = 10 V; ID = 10 A; Tj = 25 °C;
-
20.5
25
mΩ
-
-
67.8
mΩ
-
17.1
-
nC
-
34.3
-
nC
Static characteristics
V(BR)DSS
VGS(th)
IDSS
IGSS
RDSon
drain leakage current
gate leakage current
drain-source on-state
resistance
Fig. 10
Fig. 11
VGS = 5 V; ID = 10 A; Tj = 175 °C;
Fig. 12; Fig. 11
Dynamic characteristics
QG(tot)
total gate charge
ID = 10 A; VDS = 64 V; VGS = 5 V;
Tj = 25 °C; Fig. 13; Fig. 14
ID = 10 A; VDS = 64 V; VGS = 10 V;
Tj = 25 °C; Fig. 13; Fig. 14
PSMN025-80YL
Product data sheet
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PSMN025-80YL
NXP Semiconductors
N-channel 80 V, 25 mΩ logic level MOSFET in LFPAK56
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
QGS
gate-source charge
ID = 10 A; VDS = 64 V; VGS = 5 V;
-
5.2
-
nC
QGD
gate-drain charge
Tj = 25 °C; Fig. 13; Fig. 14
-
5.8
-
nC
Ciss
input capacitance
VDS = 25 V; VGS = 0 V; f = 1 MHz;
-
2032
2703
pF
Coss
output capacitance
Tj = 25 °C; Fig. 15
-
147
176
pF
Crss
reverse transfer
capacitance
-
75
103
pF
td(on)
turn-on delay time
VDS = 60 V; RL = 4.98 Ω; VGS = 5 V;
-
11.6
-
ns
tr
rise time
RG(ext) = 5 Ω; Tj = 25 °C
-
17.2
-
ns
td(off)
turn-off delay time
-
23.9
-
ns
tf
fall time
-
15.3
-
ns
Source-drain diode
VSD
source-drain voltage
IS = 10 A; VGS = 0 V; Tj = 25 °C; Fig. 16
-
0.81
1.2
V
trr
reverse recovery time
IS = 10 A; dIS/dt = -100 A/µs; VGS = 0 V;
-
23.8
-
ns
recovered charge
VDS = 25 V; Tj = 25 °C
-
27
-
nC
Qr
ID
(A)
003aaj009
80
003aaj010
100
10 V
RDSon
4.5 V
80
3.5 V
60
VGS = 3 V
60
2.8 V
40
2.6 V
20
40
20
2.4 V
0
0
0.5
1
1.5
2
2.5
3
3.5
VDS (V)
0
4
Tj = 25 °C; tp = 300 μs
Fig. 6.
Fig. 7.
Output characteristics; drain current as a
function of drain-source voltage; typical values
PSMN025-80YL
Product data sheet
0
2
6
8
10
12
14
VGS (V)
16
Drain-source on-state resistance as a function
of gate-source voltage; typical values
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PSMN025-80YL
NXP Semiconductors
N-channel 80 V, 25 mΩ logic level MOSFET in LFPAK56
ID
(A)
003aaj012
75
003aah025
3
VGS(th)
(V)
2.5
60
max
2
45
typ
1.5
30
min
1
15
0.5
175°C
Tj = 25°C
0
Fig. 8.
0
0.5
1
1.5
2
2.5
3
3.5
VGS (V)
0
-60
4
Transfer characteristics; drain current as a
function of gate-source voltage; typical values
Fig. 9.
003aah026
10-1
60
120
Tj (° C)
003aaj015
RDSon
10-2
180
Gate-source threshold voltage as a function of
junction temperature
100
ID
(A)
2.6 V
2.8 V
80
min
10-3
typ
max
60
10-4
40
10-5
20
10-6
0
0
1
2
V GS (V)
0
3
Fig. 10. Sub-threshold drain current as a function of
gate-source voltage
PSMN025-80YL
Product data sheet
3V
4.5 V
3.5 V
VGS = 10 V
0
5
10
15
20
25
30
35
ID (A)
40
Tj = 25 °C; tp = 300 μs
Fig. 11. Drain-source on-state resistance as a function
of drain current; typical values
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PSMN025-80YL
NXP Semiconductors
N-channel 80 V, 25 mΩ logic level MOSFET in LFPAK56
003aag817
3
VDS
a
ID
2.4
VGS(pl)
1.8
VGS(th)
VGS
1.2
QGS2
QGS1
0.6
0
-60
0
60
120
Tj (°C)
QGS
QGD
QG(tot)
003aaa508
Fig. 13. Gate charge waveform definitions
180
Fig. 12. Normalized drain-source on-state resistance
factor as a function of junction temperature
VGS
(V)
003aaj017
10
003aaj018
104
C
(pF)
Ciss
8
103
VGS = 14 V
6
64 V
4
Coss
102
Crss
2
0
0
5
10
15
20
25
30
35
QG (nC)
Fig. 14. Gate-source voltage as a function of gate
charge; typical values
PSMN025-80YL
Product data sheet
10
10-1
40
1
10
VDS (V)
102
Fig. 15. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
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PSMN025-80YL
NXP Semiconductors
N-channel 80 V, 25 mΩ logic level MOSFET in LFPAK56
003aaj019
150
IS
(A)
125
100
75
50
25
175°C
Tj = 25°C
0
0
0.25
0.5
0.75
1
1.25
VSD (V)
1.5
Fig. 16. Source-drain (diode forward) current as a function of source-drain (diode forward) voltage; typical values
PSMN025-80YL
Product data sheet
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PSMN025-80YL
NXP Semiconductors
N-channel 80 V, 25 mΩ logic level MOSFET in LFPAK56
11. Package outline
Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads
E
A2
A
SOT669
C
c2
b2
E1
b3
L1
mounting
base
b4
D1
D
H
L2
1
2
3
e
4
w
b
A
X
c
1/2 e
A
(A3)
A1
C
q
L
detail X
0
y C
θ
5 mm
8°
scale
0°
Dimensions (mm are the original dimensions)
Unit(1)
A
A1
A2
A3
b
b2
max 1.20 0.15 1.10
0.50 4.41
nom
0.25
min 1.01 0.00 0.95
0.35 3.62
mm
c
c2
D(1) D1(1) E(1) E1(1)
b3
b4
2.2
0.9
0.25 0.30 4.10 4.20
5.0
3.3
2.0
0.7
0.19 0.24 3.80
4.8
3.1
e
1.27
H
L
L1
L2
6.2
0.85
1.3
1.3
5.8
0.40
0.8
0.8
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
Outline
version
SOT669
References
IEC
JEDEC
JEITA
w
y
0.25
0.1
sot669_po
European
projection
Issue date
11-03-25
13-02-27
MO-235
Fig. 17. Package outline LFPAK56; Power-SO8 (SOT669)
PSMN025-80YL
Product data sheet
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PSMN025-80YL
NXP Semiconductors
N-channel 80 V, 25 mΩ logic level MOSFET in LFPAK56
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
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12.1 Data sheet status
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Document
status [1][2]
Product
status [3]
Objective
[short] data
sheet
Development This document contains data from
the objective specification for product
development.
Preliminary
[short] data
sheet
Qualification
This document contains data from the
preliminary specification.
Product
[short] data
sheet
Production
This document contains the product
specification.
[1]
[2]
[3]
Definition
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limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Please consult the most recently issued document before initiating or
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The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have
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Product data sheet.
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PSMN025-80YL
Product data sheet
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authorized or warranted to be suitable for use in life support, life-critical or
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Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
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representation or warranty that such applications will be suitable for the
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and the products or of the application or use by customer’s third party
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
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PSMN025-80YL
NXP Semiconductors
N-channel 80 V, 25 mΩ logic level MOSFET in LFPAK56
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
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NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications.
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12.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Bitsound, CoolFlux, CoReUse, DESFire, FabKey, GreenChip,
HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, MIFARE,
MIFARE Plus, MIFARE Ultralight, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP
Semiconductors N.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
PSMN025-80YL
Product data sheet
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PSMN025-80YL
NXP Semiconductors
N-channel 80 V, 25 mΩ logic level MOSFET in LFPAK56
13. Contents
1
General description ............................................... 1
2
Features and benefits ............................................1
3
Applications ........................................................... 1
4
Quick reference data ............................................. 1
5
Pinning information ............................................... 2
6
Ordering information ............................................. 2
7
Marking ................................................................... 2
8
Limiting values .......................................................2
9
Thermal characteristics .........................................4
10
Characteristics ....................................................... 5
11
Package outline ................................................... 10
12
12.1
12.2
12.3
12.4
Legal information .................................................11
Data sheet status ............................................... 11
Definitions ...........................................................11
Disclaimers .........................................................11
Trademarks ........................................................ 12
© NXP Semiconductors N.V. 2016. All rights reserved
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 14 April 2016
PSMN025-80YL
Product data sheet
All information provided in this document is subject to legal disclaimers.
14 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved
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