Data Sheet

Document Number: MD8IC925N
Rev. 0, 5/2013
Freescale Semiconductor
Technical Data
RF LDMOS Wideband Integrated
Power Amplifiers
The MD8IC925N wideband integrated circuit is designed with on−chip
matching that makes it usable from 728 to 960 MHz. This multi−stage
structure is rated for 24 to 32 volt operation and covers all typical cellular base
station modulation formats.
Driver Application — 900 MHz
• Typical Single−Carrier W−CDMA Performance: VDD = 28 Volts,
IDQ1(A+B) = 58 mA, IDQ2(A+B) = 222 mA, Pout = 2.5 Watts Avg., IQ Magnitude
Clipping, Channel Bandwidth = 3.84 MHz, Input Signal PAR = 7.5 dB
@ 0.01% Probability on CCDF.
Frequency
Gps
(dB)
PAE
(%)
ACPR
(dBc)
920 MHz
36.2
17.5
−48.9
940 MHz
36.2
17.4
−49.5
960 MHz
36.1
17.3
−49.1
• Capable of Handling 10:1 VSWR, @ 32 Vdc, 940 MHz, 25 Watts CW
Output Power (3 dB Input Overdrive from Rated Pout)
• Typical Pout @ 1 dB Compression Point ] 26 Watts CW
Driver Application — 700 MHz
• Typical Single−Carrier W−CDMA Performance: VDD = 28 Volts,
IDQ1(A+B) = 58 mA, IDQ2(A+B) = 222 mA, Pout = 2.5 Watts Avg., IQ Magnitude
Clipping, Channel Bandwidth = 3.84 MHz, Input Signal PAR = 7.5 dB
@ 0.01% Probability on CCDF.
Frequency
Gps
(dB)
PAE
(%)
ACPR
(dBc)
728 MHz
36.4
17.2
−48.9
748 MHz
36.4
17.6
−49.7
768 MHz
36.4
17.9
−50.5
MD8IC925NR1
MD8IC925GNR1
728−960 MHz, 2.5 W AVG., 28 V
SINGLE W−CDMA
RF LDMOS WIDEBAND
INTEGRATED POWER AMPLIFIERS
TO−270WB−14
PLASTIC
MD8IC925NR1
TO−270WBG−14
PLASTIC
MD8IC925GNR1
Features
• Characterized with Series Equivalent Large−Signal Impedance Parameters
and Common Source S−Parameters
• On−Chip Matching (50 Ohm Input, DC Blocked)
• Integrated Quiescent Current Temperature Compensation with
Enable/Disable Function (1)
• Integrated ESD Protection
• Designed for Digital Predistortion Error Correction Systems
• Optimized for Doherty Applications
• 225°C Capable Plastic Package
• In Tape and Reel. R1 Suffix = 500 Units, 44 mm Tape Width, 13−inch Reel.
1. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family and to AN1987, Quiescent Current Control
for the RF Integrated Circuit Device Family. Go to http://www.freescale.com/rf. Select Documentation/Application Notes − AN1977 or AN1987.
© Freescale Semiconductor, Inc., 2013. All rights reserved.
RF Device Data
Freescale Semiconductor, Inc.
MD8IC925NR1 MD8IC925GNR1
1
VDS1A
RFinA
VDS1A
VGS2A
VGS1A
RFinA
N.C.
N.C.
N.C.
N.C.
RFinB
VGS1B
VGS2B
VDS1B
RFout1/VDS2A
VGS1A
Quiescent Current
Temperature Compensation (1)
VGS2A
VGS1B
Quiescent Current
Temperature Compensation (1)
VGS2B
RFinB
1
2
3
4
5
6
7
8
9
10
11
12
14
13
RFout1/VDS2A
RFout2/VDS2B
(Top View)
RFout2/VDS2B
Note: Exposed backside of the package is
the source terminal for the transistors.
VDS1B
Figure 1. Functional Block Diagram
Figure 2. Pin Connections
Table 1. Maximum Ratings
Symbol
Value
Unit
Drain−Source Voltage
Rating
VDSS
−0.5, +65
Vdc
Gate−Source Voltage
VGS
−0.5, +10
Vdc
Operating Voltage
VDD
32, +0
Vdc
Storage Temperature Range
Tstg
−65 to +150
°C
TC
150
°C
Case Operating Temperature
Operating Junction Temperature
(2,3)
Input Power
TJ
225
°C
Pin
20
dBm
Symbol
Value (3,4)
Unit
Table 2. Thermal Characteristics
Characteristic
Thermal Resistance, Junction to Case
Case Temperature 77°C, 2.5 W CW, 940 MHz
Stage 1, 28 Vdc, IDQ1(A+B) = 58 mA, 940 MHz
Stage 2, 28 Vdc, IDQ2(A+B) = 222 mA, 940 MHz
°C/W
RθJC
5.4
1.8
Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22−A114)
1A
Machine Model (per EIA/JESD22−A115)
A
Charge Device Model (per JESD22−C101)
I
Table 4. Moisture Sensitivity Level
Test Methodology
Per JESD22−A113, IPC/JEDEC J−STD−020
Rating
Package Peak Temperature
Unit
3
260
°C
1. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family and to AN1987, Quiescent Current Control
for the RF Integrated Circuit Device Family. Go to http://www.freescale.com/rf. Select Documentation/Application Notes − AN1977 or AN1987.
2. Continuous use at maximum temperature will affect MTTF.
3. MTTF calculator available at http://www.freescale.com/rf. Select Software & Tools/Development Tools/Calculators to access MTTF
calculators by product.
4. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.freescale.com/rf. Select
Documentation/Application Notes − AN1955.
MD8IC925NR1 MD8IC925GNR1
2
RF Device Data
Freescale Semiconductor, Inc.
Table 5. Electrical Characteristics (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Zero Gate Voltage Drain Leakage Current
(VDS = 65 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
μAdc
Zero Gate Voltage Drain Leakage Current
(VDS = 28 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
μAdc
Gate−Source Leakage Current
(VGS = 1.5 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
μAdc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 4 μAdc)
VGS(th)
1.2
2.0
2.7
Vdc
Gate Quiescent Voltage
(VDS = 28 Vdc, IDQ1(A+B) = 58 mA)
VGS(Q)
—
2.4
—
Vdc
Fixture Gate Quiescent Voltage
(VDD = 28 Vdc, IDQ1(A+B) = 58 mA, Measured in Functional Test)
VGG(Q)
4.1
4.8
5.6
Vdc
Zero Gate Voltage Drain Leakage Current
(VDS = 65 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
μAdc
Zero Gate Voltage Drain Leakage Current
(VDS = 28 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
μAdc
Gate−Source Leakage Current
(VGS = 1.5 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
μAdc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 19 μAdc)
VGS(th)
1.2
2.0
2.7
Vdc
Gate Quiescent Voltage
(VDS = 28 Vdc, IDQ2(A+B) = 222 mA)
VGS(Q)
—
2.15
—
Vdc
Fixture Gate Quiescent Voltage
(VDD = 28 Vdc, IDQ2(A+B) = 222 mA, Measured in Functional Test)
VGG(Q)
3.5
4.3
5.0
Vdc
Drain−Source On−Voltage
(VGS = 10 Vdc, ID = 190 Adc)
VDS(on)
0.1
0.21
1.2
Vdc
Stage 1 − Off Characteristics (1)
Stage 1 − On Characteristics (1)
Stage 2 − Off Characteristics (1)
Stage 2 − On Characteristics (1)
Functional Tests (2,3) (In Freescale Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQ1(A+B) = 58 mA, IDQ2(A+B) = 222 mA, Pout = 2.5 W Avg.,
f = 940 MHz, Single−Carrier W−CDMA, IQ Magnitude Clipping, Input Signal PAR = 7.5 dB @ 0.01% Probability on CCDF. ACPR measured in
3.84 MHz Channel Bandwidth @ ±5 MHz Offset.
Power Gain
Gps
34.5
36.2
39.5
dB
Power Added Efficiency
PAE
15.5
17.4
—
%
ACPR
—
−49.5
−47.0
dBc
IRL
—
−27
−10
dB
Adjacent Channel Power Ratio
Input Return Loss
Typical Performance over Frequency (In Freescale Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQ1(A+B) = 58 mA, IDQ2(A+B) = 222 mA,
Pout = 2.5 W Avg, Single−Carrier W−CDMA, IQ Magnitude Clipping, Input Signal PAR = 7.5 dB @ 0.01% Probability on CCDF. ACPR
measured in 3.84 MHz Channel Bandwidth @ ±5 MHz Offset.
Frequency
Gps
(dB)
PAE
(%)
ACPR
(dBc)
IRL
(dB)
920 MHz
36.2
17.5
−48.9
−27
940 MHz
36.2
17.4
−49.5
−27
960 MHz
36.1
17.3
−49.1
−28
1. Each side of device measured separately.
2. Part internally matched both on input and output.
3. Measurements made with device in straight lead configuration before any lead forming operation is applied. Lead forming is used for gull wing
(GN) parts.
(continued)
MD8IC925NR1 MD8IC925GNR1
RF Device Data
Freescale Semiconductor, Inc.
3
Table 5. Electrical Characteristics (TA = 25°C unless otherwise noted) (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
Typical Performance (In Freescale Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQ1(A+B) = 58 mA, IDQ2(A+B) = 222 mA, 920−960 MHz
Bandwidth
Pout @ 1 dB Compression Point, CW
P1dB
—
26
—
W
Pout @ 3 dB Compression Point, CW
P3dB
—
31
—
W
—
20
—
—
75
—
—
—
1.1
1.9
—
—
IMD Symmetry @ 28 W PEP, Pout where IMD Third Order
Intermodulation ` 30 dBc
(Delta IMD Third Order Intermodulation between Upper and Lower
Sidebands > 2 dB)
IMDsym
VBW Resonance Point
(IMD Third Order Intermodulation Inflection Point)
VBWres
Quiescent Current Accuracy over Temperature (1,2)
with 18 kΩ Gate Feed Resistors (−30 to 85°C)
with 20 kΩ Gate Feed Resistors (−30 to 85°C)
MHz
ΔIQT
Stage 1
Stage 2
MHz
%
Gain Flatness in 40 MHz Bandwidth @ Pout = 2.5 W Avg.
GF
—
0.2
—
dB
Gain Variation over Temperature
(−30°C to +85°C)
ΔG
—
0.043
—
dB/°C
ΔP1dB
—
0.004
—
dB/°C
Output Power Variation over Temperature
(−30°C to +85°C)
Typical Performance over Frequency (In Freescale 700 MHz Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQ1(A+B) = 58 mA, IDQ2(A+B) =
222 mA, Pout = 2.5 W Avg., Single−Carrier W−CDMA, IQ Magnitude Clipping, Input Signal PAR = 7.5 dB @ 0.01% Probability on CCDF.
ACPR measured in 3.84 MHz Channel Bandwidth @ ±5 MHz Offset.
Frequency
Gps
(dB)
PAE
(%)
ACPR
(dBc)
IRL
(dB)
728 MHz
36.4
17.2
−48.9
−17
748 MHz
36.4
17.6
−49.7
−17
768 MHz
36.4
17.9
−50.5
−18
1. Each side of device measured separately.
2. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family and to AN1987, Quiescent Current Control for
the RF Integrated Circuit Device Family. Go to http://www.freescale.com/rf. Select Documentation/Application Notes − AN1977 or AN1987.
MD8IC925NR1 MD8IC925GNR1
4
RF Device Data
Freescale Semiconductor, Inc.
MD8IC925N
VDD1A
C1
Rev. 3
C21
C2
C22
C3 C4
C23
R1
VGG2A
R15
R2
VGG1A
VDD2A
C5
C6
R3
C24*
C7
R4
R5
C8
CUT OUT AREA
C9 C10
Z1
R13, R14**
C12 C13
R9
R8
R7
R16
C25* C26* C27*
R6
C11
Z2
C28*
C29* C30*
C34
C31*
C16
R12
VGG1B
C15
C14
R11
VDD2B
R17
VGG2B
R10
C32
C33
C18 C19
C20
C17
VDD1B
*C24, C25, C26, C27, C28, C29, C30 and C31 are mounted vertically.
**R13 and R14 are stacked.
Figure 3. MD8IC925NR1 Test Circuit Component Layout — 920−960 MHz
Table 6. MD8IC925NR1 Test Circuit Component Designations and Values — 920−960 MHz
Part
Description
Part Number
Manufacturer
C1, C20, C21, C34
220 μF, 100 V Electrolytic Capacitors
EEV−FK2A221M
Panasonic−ECG
C2, C17, C22, C33
10 μF Chip Capacitors
C5750X7S2A106M230KB
TDK
C3, C6, C9, C12, C15, C18
0.01 μF Chip Capacitors
C0805C103K5RAC
Kemet
C4, C7, C10, C13, C16, C19
47 pF Chip Capacitors
ATC600F470JT250XT
ATC
C5, C8, C11, C14
1 μF Chip Capacitors
C3225X7R2A105KT
TDK
C23, C24, C31, C32
47 pF Chip Capacitors
ATC100B470JT500XT
ATC
C25, C28
6.8 pF Chip Capacitors
ATC100B6R8CT500XT
ATC
C26, C29
2.2 pF Chip Capacitors
ATC100B2R2JT500XT
ATC
C27, C30
4.3 pF Chip Capacitors
ATC100B4R3CT500XT
ATC
R1, R4, R7, R10
0 , 3 A Chip Jumpers
CRCW12060000Z0EA
Vishay
R2, R3, R5, R6, R8, R9, R11, R12
1 k, 1/4 W Chip Resistors
CRCW12061K00FKEA
Vishay
R13, R14
100 , 1/4 W Chip Resistors
CRCW1206100RFKEA
Vishay
R15, R17
0 , 2 A Chip Jumpers
WCR1206−R005J
Welwyn
R16
50 , 10 W Chip Resistor
81A7031−50−5F
Florida RF Labs
Z1, Z2
815−960 MHz Band, 90, 3 dB Chip
Hybrid Couplers
GSC362−HYB0900
Soshin
PCB
0.020″, r = 3.55
RF35
Taconic
MD8IC925NR1 MD8IC925GNR1
RF Device Data
Freescale Semiconductor, Inc.
5
18
PAE
17.5
VDD = 28 Vdc, Pout = 2.5 W (Avg.)
IDQ1(A+B) = 58 mA, IDQ2(A+B) = 222 mA
Single-Carrier W-CDMA
Gps, POWER GAIN (dB)
37
36.5
17
16.5
Gps
36
35.5
16
3.84 MHz Channel Bandwidth
Input Signal PAR = 7.5 dB
@ 0.01% Probability on CCDF
PARC
35
34.5
-47
0.5
-48
0.4
-49
ACPR
34
-50
33.5
33
820
840
860
880
900
920
940
960
ACPR (dBc)
37.5
0.3
0.2
-51
0.1
-52
0
PARC (dB)
38
PAE, POWER ADDED
EFFICIENCY (%)
TYPICAL CHARACTERISTICS
980
f, FREQUENCY (MHz)
IMD, INTERMODULATION DISTORTION (dBc)
Figure 4. Output Peak−to−Average Ratio Compression (PARC)
Broadband Performance @ Pout = 2.5 Watts Avg.
-10
VDD = 28 Vdc, Pout = 28 W (PEP), IDQ1(A+B) = 58 mA
IDQ2(A+B) = 222 mA, Two-Tone Measurements
(f1 + f2)/2 = Center Frequency of 940 MHz
-20
IM3-U
-30
IM5-U
-40
IM5-L
IM3-L
IM7-U
-50
IM7-L
-60
1
10
100
200
TWO-TONE SPACING (MHz)
Figure 5. Intermodulation Distortion Products
versus Two−Tone Spacing
35.5
35
34.5
34
VDD = 28 Vdc, IDQ1(A+B) = 58 mA, IDQ2(A+B) = 222 mA, f = 940 MHz
ACPR 60
0
Gps
50
-1
-2 dB = 9 W
-1 dB = 6.5 W
-2
PAE
-3
40
PARC
30
-3 dB = 12 W
-4
20
Single-Carrier W-CDMA, 3.84 MHz Channel Bandwidth
Input Signal PAR = 7.5 dB @ 0.01% Probability on CCDF
-5
1
4
7
10
13
-25
70
10
16
-30
-35
-40
ACPR (dBc)
36
OUTPUT COMPRESSION AT 0.01%
PROBABILITY ON CCDF (dB)
Gps, POWER GAIN (dB)
36.5
1
PAE, POWER ADDED EFFICIENCY (%)
37
-45
-50
-55
Pout, OUTPUT POWER (WATTS)
Figure 6. Output Peak−to−Average Ratio
Compression (PARC) versus Output Power
MD8IC925NR1 MD8IC925GNR1
6
RF Device Data
Freescale Semiconductor, Inc.
60
VDD = 28 Vdc, IDQ1(A+B) = 58 mA, IDQ2(A+B) = 222 mA
Single-Carrier W-CDMA
38 3.84 MHz Channel Bandwidth
PAE
50
37 920 MHz 960 MHz 940 MHz
40
960 MHz
ACPR
36
30
940 MHz
920 MHz
35
Gps
20
920 MHz
940 MHz
34
10
Input Signal PAR = 7.5 dB @ 0.01% Probability on CCDF
33
1
0
0
10
-10
-20
-30
-40
ACPR (dBc)
39
PAE, POWER ADDED EFFICIENCY (%)
Gps, POWER GAIN (dB)
TYPICAL CHARACTERISTICS
-50
-60
40
Pout, OUTPUT POWER (WATTS) AVG.
Figure 7. Single−Carrier W−CDMA Power Gain, Power Added
Efficiency and ACPR versus Output Power
39
GAIN (dB)
VDD = 28 Vdc
Pin = 0 dBm
38 I
DQ1(A+B) = 58 mA
IDQ2(A+B) = 222 mA
37
Gain
36
35
34
33
700
750
800
850
900
950
1000
1050
1100
f, FREQUENCY (MHz)
Figure 8. Broadband Frequency Response
MD8IC925NR1 MD8IC925GNR1
RF Device Data
Freescale Semiconductor, Inc.
7
W−CDMA TEST SIGNAL
100
10
0
-10
3.84 MHz
Channel BW
-20
1
Input Signal
-30
0.1
(dB)
PROBABILITY (%)
10
0.01
W-CDMA. ACPR Measured in 3.84 MHz
Channel Bandwidth @ ±5 MHz Offset.
Input Signal PAR = 7.5 dB @ 0.01%
Probability on CCDF
0.001
0.0001
0
1
2
3
4
5
6
-40
-50
-60
+ACPR in 3.84 MHz
Integrated BW
-ACPR in 3.84 MHz
Integrated BW
-70
-80
7
8
9
PEAK-TO-AVERAGE (dB)
Figure 9. CCDF W−CDMA IQ Magnitude
Clipping, Single−Carrier Test Signal
10
-90
-100
-9
-7.2 -5.4 -3.6 -1.8
0
1.8
3.6
5.4
7.2
9
f, FREQUENCY (MHz)
Figure 10. Single−Carrier W−CDMA Spectrum
MD8IC925NR1 MD8IC925GNR1
8
RF Device Data
Freescale Semiconductor, Inc.
VDD = 28 Vdc, IDQ1(A+B) = 58 mA, IDQ2(A+B) = 222 mA, Pout = 2.5 W Avg.
f
MHz
Zin
W
Zload
W
820
47.9 + j2.34
7.51 + j5.45
840
47.9 + j2.47
7.62 + j5.42
860
47.8 + j2.61
7.60 + j5.41
880
47.8 + j2.75
7.48 + j5.44
900
47.7 + j2.89
7.27 + j5.55
920
47.7 + j3.04
7.00 + j5.74
940
47.7 + j3.19
6.71 + j6.01
960
47.6 + j3.34
6.40 + j6.37
47.6 + j3.49
6.10 + j6.79
980
Zin
=
Zload =
Device input impedance as measured from
gate to ground.
Test circuit impedance as measured from
drain to ground.
Output
Matching
Network
Device
Under
Test
Zin
Zload
Figure 11. Series Equivalent Input and Load Impedance
MD8IC925NR1 MD8IC925GNR1
RF Device Data
Freescale Semiconductor, Inc.
9
VDD = 28 Vdc, IDQ1A = 21 mA, IDQ2A = 101 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
(W)
Zin
(W)
Zload (1)
(W)
Gain (dB)
(dBm)
(W)
PAE
(%)
AM/PM
(5)
920
59.9 − j18.3
56.8 + j19.1
10.9 + j2.37
32.4
43.0
20
57.8
−4.9
940
60.7 − j18.5
61.2 + j14.3
12.4 + j1.56
32.2
42.9
20
54.9
−5.2
960
62.9 − j10.5
64.5 + j8.82
14.8 + j0.656
31.9
42.9
20
55.1
−5.2
Max Output Power
P3dB
Zload
(W)
f
(MHz)
Zsource
(W)
Zin
(W)
920
59.9 − j18.3
56.9 + j16.9
940
60.7 − j18.5
60.8 + j12.3
960
62.9 − j10.5
64.5 + j8.82
(2)
Gain (dB)
(dBm)
(W)
PAE
(%)
AM/PM
(5)
10.7 + j1.54
30.1
43.8
24
57.2
−5.4
11.7 + j1.11
30.0
43.7
24
55.6
−5.6
14.8 + j0.656
31.9
42.9
20
55.1
−5.2
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Note: Measurement made on a per side basis.
Figure 12. Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, IDQ1A = 21 mA, IDQ2A = 101 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Power Added Efficiency
P1dB
f
(MHz)
Zsource
(W)
Zin
(W)
Zload (1)
(W)
Gain (dB)
(dBm)
(W)
PAE
(%)
AM/PM
(5)
920
59.9 − j18.3
60.9 + j20.8
11.1 + j10.9
34.2
41.3
13
66.4
−6.7
940
60.7 − j18.5
66.5 + j16.0
10.0 + j11.8
34.4
40.7
12
63.5
−7.8
960
62.9 − j10.5
69.0 + j9.28
11.6 + j11.5
33.9
40.9
12
63.3
−6.8
Max Power Added Efficiency
P3dB
Zload
(W)
f
(MHz)
Zsource
(W)
Zin
(W)
920
59.9 − j18.3
59.7 + j19.9
940
60.7 − j18.5
64.3 + j14.2
960
62.9 − j10.5
69.0 + j9.28
(2)
Gain (dB)
(dBm)
(W)
PAE
(%)
AM/PM
(5)
9.03 + j9.12
32.3
42.2
17
65.3
−9.9
10.5 + j9.80
32.1
42.0
16
62.3
−7.6
11.6 + j11.5
33.9
40.9
12
63.3
−6.8
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Note: Measurement made on a per side basis.
Figure 13. Load Pull Performance — Maximum Power Added Efficiency Tuning
Output Load Pull
Tuner and
Test Circuit
Device
Under
Test
Zin
Zload
MD8IC925NR1 MD8IC925GNR1
10
RF Device Data
Freescale Semiconductor, Inc.
ALTERNATIVE CHARACTERIZATION — 728−768 MHz
MD8IC925N
VDD1A
C1
Rev. 3
C21
C2
C22
C3 C4
C23
R1
VGG2A
R15
R2
VGG1A
VDD2A
C5
C6
R3
C24*
C7
R4
R5
C27*
C26*
C8
C25*
CUT OUT AREA
R6
C9 C10
Z1
R13, R14**
C12 C13
R9
R8
R7
C11
R16
Z2
C29*
C30*
C28*
C34
C31*
C16
R12
VGG1B
C15
C14
R11
VDD2B
R17
VGG2B
R10
C32
C33
C18 C19
C20
C17
VDD1B
*C24, C25, C26, C27, C28, C29, C30 and C31 are mounted vertically.
**R13 and R14 are stacked.
Figure 14. MD8IC925NR1 Test Circuit Component Layout — 728−768 MHz
Table 7. MD8IC925NR1 Test Circuit Component Designations and Values — 728−768 MHz
Part
Description
Part Number
Manufacturer
C1, C20, C21, C34
220 F, 100 V Electrolytic Capacitors
EEV−FK2A221M
Panasonic−ECG
C2, C17, C22, C33
10 F Chip Capacitors
C5750X7S2A106M230KB
TDK
C3, C6, C9, C12, C15, C18
0.01 F Chip Capacitors
C0805C103K5RAC
Kemet
C4, C7, C10, C13, C16, C19
47 pF Chip Capacitors
ATC600F470JT250XT
ATC
C5, C8, C11, C14
1 F Chip Capacitors
C3225X7R2A105KT
TDK
C23, C24, C31, C32
68 pF Chip Capacitors
ATC100B680JT500XT
ATC
C25, C28
2.2 pF Chip Capacitors
ATC100B2R2JT500XT
ATC
C26, C27, C29, C30
5.6 pF Chip Capacitors
ATC100B5R6CT500XT
ATC
R1, R4, R7, R10
0 3 A Chip Jumpers
CRCW12060000Z0EA
Vishay
R2, R3, R5, R6, R8, R9, R11, R12
1 k 1/4 W Chip Resistors
CRCW12061K00FKEA
Vishay
R13, R14
100 1/4 W Chip Resistors
CRCW1206100RFKEA
Vishay
R15, R17
0 , 2 A Chip Jumpers
WCR1206−R005J
Welwyn
R16
50 , 10 W Chip Resistor
81A7031−50−5F
Florida RF Labs
Z1, Z2
815−960 MHz Band, 90, 3 dB Chip
Hybrid Couplers
GSC362−HYB0900
Soshin
PCB
0.020″, r = 3.55
RF35
Taconic
MD8IC925NR1 MD8IC925GNR1
RF Device Data
Freescale Semiconductor, Inc.
11
18
17.5
17
16.5
-47
0.3
36.4
-48
0.2
36.3
-49
ACPR
36.2
36.1
-50
Input Signal PAR = 7.5 dB @ 0.01% Probability on CCDF
36
710
720
730
740
750
760
770
780
0.1
0
-51
-0.1
-52
-0.2
PARC (dB)
18.5
VDD = 28 Vdc, Pout = 2.5 W (Avg.)
PAE
36.9 I
DQ1(A+B) = 58 mA, IDQ2(A+B) = 222 mA
36.8
Single-Carrier W-CDMA
36.7
3.84 MHz Channel Bandwidth
36.6
Gps
PARC
36.5
ACPR (dBc)
Gps, POWER GAIN (dB)
37
PAE, POWER ADDED
EFFICIENCY (%)
ALTERNATIVE CHARACTERIZATION — 728−768 MHz
790
f, FREQUENCY (MHz)
Figure 15. Output Peak−to−Average Ratio Compression (PARC)
Broadband Performance @ Pout = 2.5 Watts Avg.
37
50
40
36
35
30
728 MHz
768 MHz
768 MHz
20
748 MHz
728 MHz
34
10
Input Signal PAR = 7.5 dB @ 0.01% Probability on CCDF
33
1
0
-10
-20
-30
-40
-50
0
10
ACPR (dBc)
38
Gps, POWER GAIN (dB)
60
768 MHz
VDD = 28 Vdc, IDQ1(A+B) = 58 mA
PAE
IDQ2(A+B) = 222 mA, Single-Carrier W-CDMA
3.84 MHz Channel Bandwidth
728 MHz
748 MHz
748 MHz
Gps
ACPR
PAE, POWER ADDED EFFICIENCY (%)
39
-60
40
Pout, OUTPUT POWER (WATTS) AVG.
Figure 16. Single−Carrier W−CDMA Power Gain, Power Added
Efficiency and ACPR versus Output Power
39
GAIN (dB)
VDD = 28 Vdc
Pin = 0 dBm
38 I
DQ1(A+B) = 58 mA
IDQ2(A+B) = 222 mA
37
Gain
36
35
34
33
650
700
750
800
850
900
950
1000
1050
f, FREQUENCY (MHz)
Figure 17. Broadband Frequency Response
MD8IC925NR1 MD8IC925GNR1
12
RF Device Data
Freescale Semiconductor, Inc.
VDD = 28 Vdc, IDQ1(A+B) = 58 mA, IDQ2(A+B) = 222 mA, Pout = 2.5 W Avg.
f
MHz
Zin
W
Zload
W
710
48.2 + j1.65
8.02 + j6.72
720
48.2 + j1.71
8.43 + j6.89
730
48.2 + j1.77
8.64 + j7.04
740
48.1 + j1.83
8.84 + j7.17
750
48.0 + j1.89
9.01 + j7.29
760
48.1 + j1.95
9.16 + j7.39
770
48.0 + j2.01
9.28 + j7.49
780
48.0 + j2.08
9.38 + j7.59
48.0 + j2.14
9.45 + j7.68
790
Zin
=
Zload =
Device input impedance as measured from
gate to ground.
Test circuit impedance as measured from
drain to ground.
Output
Matching
Network
Device
Under
Test
Zin
Zload
Figure 18. Series Equivalent Input and Load Impedance — 728−768 MHz
MD8IC925NR1 MD8IC925GNR1
RF Device Data
Freescale Semiconductor, Inc.
13
VDD = 28 Vdc, IDQ1A = 21 mA, IDQ2A = 101 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
(W)
Zin
(W)
Zload (1)
(W)
Gain (dB)
(dBm)
(W)
PAE
(%)
AM/PM
(5)
730
25.7 − j5.86
24.7 + j3.12
8.35 + j5.97
34.0
42.7
19
58.9
−3.6
750
24.8 − j8.46
24.8 + j6.48
8.50 + j5.61
33.9
42.8
19
57.8
−2.6
770
27.5 − j12.2
26.5 + j10.4
10.0 + j4.28
33.7
43.1
20
60.0
−3.0
Max Output Power
P3dB
Zload
(W)
f
(MHz)
Zsource
(W)
Zin
(W)
730
25.7 − j5.86
25.7 + j3.64
750
24.8 − j8.46
26.0 + j6.61
770
27.5 − j12.2
26.5 + j10.4
(2)
Gain (dB)
(dBm)
(W)
PAE
(%)
AM/PM
(5)
8.59 + j4.89
31.6
43.5
23
60.0
−6.0
8.40 + j4.59
31.5
43.6
23
58.2
−4.4
10.0 + j4.28
33.7
43.1
20
60.0
−3.0
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Note: Measurement made on a per side basis.
Figure 19. Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, IDQ1A = 21 mA, IDQ2A = 101 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Power Added Efficiency
P1dB
f
(MHz)
Zsource
(W)
Zin
(W)
Zload (1)
(W)
Gain (dB)
(dBm)
(W)
PAE
(%)
AM/PM
(5)
730
25.7 − j5.86
23.9 + j6.61
14.0 + j13.4
36.2
40.7
12
68.0
−6.4
750
24.8 − j8.46
24.2 + j10.2
12.4 + j13.8
36.5
40.5
11
66.0
−6.1
770
27.5 − j12.2
25.7 + j14.3
11.4 + j13.5
36.3
41.0
13
70.5
−8.2
AM/PM
(5)
Max Power Added Efficiency
P3dB
Zload
(W)
f
(MHz)
Zsource
(W)
Zin
(W)
730
25.7 − j5.86
24.1 + j6.09
750
24.8 − j8.46
25.3 + j9.02
770
27.5 − j12.2
25.7 + j14.3
(2)
Gain (dB)
(dBm)
(W)
PAE
(%)
11.2 + j12.4
34.4
41.6
14
69.4
−11
12.0 + j11.3
34.0
42.0
16
67.8
−6.3
11.4 + j13.5
36.3
41.0
13
70.5
−8.2
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Note: Measurement made on a per side basis.
Figure 20. Load Pull Performance — Maximum Power Added Efficiency Tuning
Output Load Pull
Tuner and
Test Circuit
Device
Under
Test
Zin
Zload
MD8IC925NR1 MD8IC925GNR1
14
RF Device Data
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
MD8IC925NR1 MD8IC925GNR1
RF Device Data
Freescale Semiconductor, Inc.
15
MD8IC925NR1 MD8IC925GNR1
16
RF Device Data
Freescale Semiconductor, Inc.
MD8IC925NR1 MD8IC925GNR1
RF Device Data
Freescale Semiconductor, Inc.
17
MD8IC925NR1 MD8IC925GNR1
18
RF Device Data
Freescale Semiconductor, Inc.
MD8IC925NR1 MD8IC925GNR1
RF Device Data
Freescale Semiconductor, Inc.
19
MD8IC925NR1 MD8IC925GNR1
20
RF Device Data
Freescale Semiconductor, Inc.
PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS
Refer to the following documents, software and tools to aid your design process.
Application Notes
• AN1907: Solder Reflow Attach Method for High Power RF Devices in Plastic Packages
• AN1955: Thermal Measurement Methodology of RF Power Amplifiers
• AN1977: Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family
• AN1987: Quiescent Current Control for the RF Integrated Circuit Device Family
• AN3789: Clamping of High Power RF Transistors and RFICs in Over−Molded Plastic Packages
Engineering Bulletins
• EB212: Using Data Sheet Impedances for RF LDMOS Devices
Software
• Electromigration MTTF Calculator
• RF High Power Model
• .s2p File
Development Tools
• Printed Circuit Boards
For Software and Tools, do a Part Number search at http://www.freescale.com, and select the “Part Number” link. Go to the
Software & Tools tab on the part’s Product Summary page to download the respective tool.
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
0
May 2013
Description
• Initial Release of Data Sheet
MD8IC925NR1 MD8IC925GNR1
RF Device Data
Freescale Semiconductor, Inc.
21
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E 2013 Freescale Semiconductor, Inc.
MD8IC925NR1 MD8IC925GNR1
Document Number: MD8IC925N
Rev. 0, 5/2013
22
RF Device Data
Freescale Semiconductor, Inc.