Freescale Semiconductor Technical Data Document Number: A2I20D020N Rev. 0, 5/2016 RF LDMOS Wideband Integrated Power Amplifiers The A2I20D020N wideband integrated circuit is designed with on--chip matching that makes it usable from 1400 to 2200 MHz. This multi--stage structure is rated for 20 to 32 V operation and covers all typical cellular base station modulation formats. 1800–2200 MHz Typical Single--Carrier W--CDMA Characterization Performance: VDD = 28 Vdc, IDQ1(A+B) = 32 mA, IDQ2(A+B) = 110 mA, Pout = 2.5 W Avg., Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF.(1) Frequency Gps (dB) PAE (%) ACPR (dBc) 1800 MHz 31.0 19.7 –44.3 1900 MHz 31.0 21.7 –45.0 2000 MHz 31.1 22.1 –45.2 2100 MHz 31.4 21.1 –45.2 2200 MHz 32.0 19.6 –44.8 1. All data measured in fixture with device soldered to heatsink. Features A2I20D020NR1 A2I20D020GNR1 1400–2200 MHz, 2.5 W AVG., 28 V AIRFAST RF LDMOS WIDEBAND INTEGRATED POWER AMPLIFIERS TO--270WB--17 PLASTIC A2I20D020NR1 TO--270WBG--17 PLASTIC A2I20D020GNR1 Extremely Wide RF Bandwidth RF Decoupled Drain Pins Reduce Overall Board Space On--Chip Matching (50 Ohm Input, DC Blocked) Integrated Quiescent Current Temperature Compensation with Enable/Disable Function (2) 2. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to http://www.nxp.com/RF. Select Documentation/Application Notes -- AN1977 or AN1987. Freescale Semiconductor, Inc., 2016. All rights reserved. RF Device Data Freescale Semiconductor, Inc. A2I20D020NR1 A2I20D020GNR1 1 VDS1A VBWA RFinA VDS1A VGS2A VGS1A RFinA N.C. GND GND N.C. RFinB VGS1B VGS2B VDS1B RFout1/VDS2A VGS1A Quiescent Current Temperature Compensation (1) VGS2A VGS1B Quiescent Current Temperature Compensation (1) VGS2B RFinB RFout2/VDS2B VDS1B VBWB 17 1 2 3 4 5 6 7 8 9 10 11 12 16 15 14 13 VBWA(2) RFout1/VDS2A GND RFout2/VDS2B VBWB(2) (Top View) Note: Exposed backside of the package is the source terminal for the transistors. Figure 1. Functional Block Diagram Figure 2. Pin Connections 2. Device can operate with VDD current supplied through pin 13 and pin 17. 1. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family, and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to http://www.nxp.com/RF and search for AN1977 or AN1987. Table 1. Maximum Ratings Symbol Value Unit Drain--Source Voltage Rating VDSS –0.5, +65 Vdc Gate--Source Voltage VGS –0.5, +10 Vdc Operating Voltage VDD 32, +0 Vdc Storage Temperature Range Tstg –65 to +150 C Case Operating Temperature Range TC –40 to +150 C (3,4) TJ –40 to +225 C Characteristic Symbol Value (4,5) Unit Operating Junction Temperature Range Table 2. Thermal Characteristics Thermal Resistance, Junction to Case Case Temperature 74C, 2.5 W, 2000 MHz Stage 1, 28 Vdc, IDQ1(A+B) = 30 mA Stage 2, 28 Vdc, IDQ2(A+B) = 110 mA RJC C/W 7.8 2.9 Table 3. ESD Protection Characteristics Test Methodology Class Human Body Model (per JESD22--A114) 1A Machine Model (per EIA/JESD22--A115) A Charge Device Model (per JESD22--C101) II Table 4. Moisture Sensitivity Level Test Methodology Per JESD22--A113, IPC/JEDEC J--STD--020 Rating Package Peak Temperature Unit 3 260 C 3. Continuous use at maximum temperature will affect MTTF. 4. MTTF calculator available at http://www.nxp.com/RF/calculators. 5. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.nxp.com/RF and search for AN1955. A2I20D020NR1 A2I20D020GNR1 2 RF Device Data Freescale Semiconductor, Inc. Table 5. Electrical Characteristics (TA = 25C unless otherwise noted) Symbol Min Typ Max Unit Zero Gate Voltage Drain Leakage Current (VDS = 65 Vdc, VGS = 0 Vdc) IDSS — — 10 Adc Zero Gate Voltage Drain Leakage Current (VDS = 32 Vdc, VGS = 0 Vdc) IDSS — — 1 Adc Gate--Source Leakage Current (VGS = 1.0 Vdc, VDS = 0 Vdc) IGSS — — 1 Adc Gate Threshold Voltage (1) (VDS = 10 Vdc, ID = 2 Adc) VGS(th) 0.8 1.2 1.6 Vdc Gate Quiescent Voltage (VDS = 28 Vdc, IDQ1(A+B) = 32 mAdc) VGS(Q) — 1.9 — Vdc Fixture Gate Quiescent Voltage (VDD = 28 Vdc, IDQ1(A+B) = 32 mAdc, Measured in Functional Test) VGG(Q) 7.5 8.2 9.0 Vdc Zero Gate Voltage Drain Leakage Current (VDS = 65 Vdc, VGS = 0 Vdc) IDSS — — 10 Adc Zero Gate Voltage Drain Leakage Current (VDS = 32 Vdc, VGS = 0 Vdc) IDSS — — 1 Adc Gate--Source Leakage Current (VGS = 1.0 Vdc, VDS = 0 Vdc) IGSS — — 1 Adc Gate Threshold Voltage (1) (VDS = 10 Vdc, ID = 11 Adc) VGS(th) 0.8 1.2 1.6 Vdc Gate Quiescent Voltage (VDS = 28 Vdc, IDQ2(A+B) = 110 mAdc) VGS(Q) — 1.8 — Vdc Fixture Gate Quiescent Voltage (VDD = 28 Vdc, IDQ2(A+B) = 110 mAdc, Measured in Functional Test) VGG(Q) 4.1 4.8 5.6 Vdc Drain--Source On--Voltage (1) (VGS = 10 Vdc, ID = 200 mAdc) VDS(on) 0.1 0.3 1.5 Vdc Characteristic Stage 1 -- Off Characteristics (1) Stage 1 -- On Characteristics Stage 2 -- Off Characteristics (1) Stage 2 -- On Characteristics 1. Each side of device measured separately. (continued) A2I20D020NR1 A2I20D020GNR1 RF Device Data Freescale Semiconductor, Inc. 3 Table 5. Electrical Characteristics (TA = 25C unless otherwise noted)(continued) Characteristic Symbol Min Typ Max Unit (1,2) Functional Tests (In Freescale Production Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQ1(A+B) = 32 mA, IDQ2(A+B) = 110 mA, Pout = 2.5 W Avg., f = 1900 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF. ACPR measured in 3.84 MHz Channel Bandwidth @ 5 MHz Offset. Power Gain Gps 30.2 31.0 35.0 dB Power Added Efficiency PAE 20.3 21.2 — % Adjacent Channel Power Ratio ACPR — –44.0 –43.0 dBc Pout @ 3 dB Compression Point, CW P3dB 19.5 22.2 — W Load Mismatch (In Freescale Production Test Fixture, 50 ohm system) IDQ1(A+B) = 32 mA, IDQ2(A+B) = 110 mA, f = 2200 MHz VSWR 10:1 at 32 Vdc, 46.8 W CW Output Power (3 dB Input Overdrive from 40.7 W CW Rated Power) No Device Degradation Typical Performance (3) (In Freescale Characterization Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQ1(A+B) = 32 mA, IDQ2(A+B) = 110 mA, 1800–2200 MHz Bandwidth Pout @ 1 dB Compression Point, CW P1dB — 16 — W (4) P3dB — 24 — W AM/PM (Maximum value measured at the P3dB compression point across the 1800–2200 MHz frequency range.) — –7.6 — — — 2.7 1.9 — — Pout @ 3 dB Compression Point Quiescent Current Accuracy over Temperature (5) with 4.7 k Gate Feed Resistors (--30 to 85C) Stage 1 with 4.7 k Gate Feed Resistors (--30 to 85C) Stage 2 IQT Gain Flatness in 400 MHz Bandwidth @ Pout = 2.5 W Avg. GF — 1.0 — dB Gain Variation over Temperature (–30C to +85C) G — 0.023 — dB/C P1dB — 0.015 — dB/C Output Power Variation over Temperature (–30C to +85C) % Table 6. Ordering Information Device A2I20D020NR1 A2I20D020GNR1 Tape and Reel Information R1 Suffix = 500 Units, 44 mm Tape Width, 13--Reel Package TO--270WB--17 TO--270WBG--17 1. Part internally input and output matched. 2. Measurements made with device in straight lead configuration before any lead forming operation is applied. Lead forming is used for gull wing (GN) parts. 3. All data measured in fixture with device soldered to heatsink. 4. P3dB = Pavg + 7.0 dB where Pavg is the average output power measured using an unclipped W--CDMA single--carrier input signal where output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF. 5. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family, and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to http://www.nxp.com/RF and search for AN1977 or AN1987. A2I20D020NR1 A2I20D020GNR1 4 RF Device Data Freescale Semiconductor, Inc. VDD1A VGG2A VDD2A VGG1A R1 R2 C7 R5 C9 C11 C5 Z1 C3 Q1 C6 C8 R3 C12 C10 A2I20D020N Rev. 4 C17 C15 C13 C1 Z2 C4 C2 C14 C16 C18 R6 R4 VGG1B VDD2B VGG2B D77506 VDD1B Note: All data measured in fixture with device soldered to heatsink. Production fixture does not include device soldered to heatsink. Figure 3. A2I20D020NR1 Test Circuit Component Layout Table 7. A2I20D020NR1 Test Circuit Component Designations and Values Part Description Part Number Manufacturer C1, C2 3.9 pF Chip Capacitors ATC600F3R9BT250XT ATC C3, C4 0.5 pF Chip Capacitors ATC600F0R5BT250XT ATC C5, C6, C7, C8 4.7 F Chip Capacitors GRM31CR71H475KA12L Murata C9, C10, C11, C12, C13, C14, C15, C16, C17, C18 10 F Chip Capacitors GRM31CR61H106KA12L Murata Q1 RF LDMOS Power Amplifier A2I20D020N NXP R1, R2, R3, R4 4.7 k, 1/4 W Chip Resistors CRCW12064K70FKEA Vishay R5, R6 50 , 10 W Chip Resistors 060120A15Z50-2 Anaren Z1, Z2 1700–2300 MHz, 90, 3 dB Hybrid Couplers X3C19P1-03S Anaren PCB Rogers RO4350B, 0.020, r = 3.66 D77506 MTL A2I20D020NR1 A2I20D020GNR1 RF Device Data Freescale Semiconductor, Inc. 5 Table 8. Load Pull Performance — Maximum Power Tuning VDD = 28 Vdc, IDQ1 = 16 mA, IDQ2 = 57 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle Max Output Power P1dB Zload () f (MHz) Zsource () Zin () 1805 92.7 + j84.9 72.9 – j80.3 1840 70.5 + j83.3 62.6 – j79.4 1880 53.3 + j79.4 50.7 – j74.5 (1) Gain (dB) (dBm) (W) D (%) AM/PM () 21.8 – j4.48 31.6 40.6 11 54.5 –3 19.0 – j6.17 31.4 40.6 11 52.5 –3 17.9 – j5.52 31.3 40.6 12 51.6 –3 Max Output Power P3dB f (MHz) Zsource () Zin () Zload (2) () Gain (dB) (dBm) (W) D (%) AM/PM () 1805 92.7 + j84.9 71.2 – j79.5 20.1 – j7.48 29.3 41.5 14 53.7 –6 1840 70.5 + j83.3 61.5 – j78.8 18.5 – j6.91 29.3 41.5 14 52.8 –6 1880 53.3 + j79.4 50.1 – j73.8 17.5 – j6.54 29.2 41.5 14 51.8 –5 (1) Load impedance for optimum P1dB power. (2) Load impedance for optimum P3dB power. Zsource = Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output of the device at the package reference plane. Note: Measurement made on a per side basis. Table 9. Load Pull Performance — Maximum Efficiency Tuning VDD = 28 Vdc, IDQ1 = 16 mA, IDQ2 = 57 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle Max Drain Efficiency P1dB f (MHz) Zsource () Zin () Zload (1) () 1805 92.7 + j84.9 73.1 – j84.4 41.8 + j7.22 32.9 39.0 8 61.7 –5 1840 70.5 + j83.3 62.4 – j82.2 32.6 + j4.15 32.6 39.4 9 59.9 –4 1880 53.3 + j79.4 50.5 – j77.9 26.6 + j12.0 33.0 38.8 8 57.5 –5 Gain (dB) (dBm) (W) D (%) AM/PM () Max Drain Efficiency P3dB f (MHz) Zsource () Zin () Zload (2) () Gain (dB) (dBm) (W) D (%) AM/PM () 1805 92.7 + j84.9 72.6 – j82.9 41.0 + j3.98 30.8 40.0 10 61.1 –8 1840 70.5 + j83.3 62.5 – j81.6 30.9 + j5.87 30.6 40.3 11 59.8 –7 1880 53.3 + j79.4 50.2 – j76.9 30.1 + j10.2 30.9 39.7 9 58.1 –6 (1) Load impedance for optimum P1dB efficiency. (2) Load impedance for optimum P3dB efficiency. Zsource = Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output of the device at the package reference plane. Note: Measurement made on a per side basis. Input Load Pull Tuner and Test Circuit Output Load Pull Tuner and Test Circuit Device Under Test Zsource Zin Zload A2I20D020NR1 A2I20D020GNR1 6 RF Device Data Freescale Semiconductor, Inc. P1dB -- TYPICAL LOAD PULL CONTOURS — 1840 MHz 20 15 39.5 5 0 39 37 38.5 37.5 38 –5 P –10 54 10 E 40 56 15 IMAGINARY () 10 IMAGINARY () 20 36.5 40.5 5 56 –5 P –10 –15 –15 –20 10 –20 20 30 40 50 60 E 58 0 52 54 44 46 48 50 52 10 20 50 30 40 50 60 REAL () Figure 4. P1dB Load Pull Output Power Contours (dBm) Figure 5. P1dB Load Pull Efficiency Contours (%) 20 20 15 15 10 10 5 0 32.5 –5 P –10 –15 –20 10 33 E IMAGINARY () IMAGINARY () REAL () 30.5 –10 –8 –6 –4 5 E 0 –5 P –15 31 20 –4 –12 –10 31.5 30 29.5 32 –14 30 40 REAL () 50 60 –20 10 –2 20 –2 30 40 50 60 REAL () Figure 6. P1dB Load Pull Gain Contours (dB) NOTE: Figure 7. P1dB Load Pull AM/PM Contours () P = Maximum Output Power E = Maximum Drain Efficiency Gain Drain Efficiency Linearity Output Power A2I20D020NR1 A2I20D020GNR1 RF Device Data Freescale Semiconductor, Inc. 7 P3dB -- TYPICAL LOAD PULL CONTOURS — 1840 MHz 20 20 38 15 5 10 38.5 E IMAGINARY () IMAGINARY () 10 39 0 39.5 –5 P 40 –10 20 30 0 58 –5 P 40 56 44 –15 40.5 –20 10 E 5 –10 41 –15 54 15 46 48 –20 10 60 50 54 50 52 20 30 40 50 60 REAL () REAL () Figure 8. P3dB Load Pull Output Power Contours (dBm) Figure 9. P3dB Load Pull Efficiency Contours (%) 20 15 –10 –15 –20 10 10 IMAGINARY () IMAGINARY () 30 5 –5 15 30.5 10 0 20 31 E 29.5 29 28.5 P –18 –16 –14 –12 5 E –8 0 –5 –10 –6 P –4 –10 28 –15 27.5 20 30 40 REAL () 50 60 –20 10 –2 20 30 40 50 60 REAL () Figure 10. P3dB Load Pull Gain Contours (dB) NOTE: Figure 11. P3dB Load Pull AM/PM Contours () P = Maximum Output Power E = Maximum Drain Efficiency Gain Drain Efficiency Linearity Output Power A2I20D020NR1 A2I20D020GNR1 8 RF Device Data Freescale Semiconductor, Inc. Table 10. Load Pull Performance — Maximum Power Tuning VDD = 28 Vdc, IDQ1 = 16 mA, IDQ2 = 57 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle Max Output Power P1dB f (MHz) Zsource () Zin () Zload () (1) Gain (dB) (dBm) (W) D (%) AM/PM () 2110 26.5 + j66.6 26.8 – j66.8 17.2 + j0.65 32.6 40.6 12 50.7 –4 2140 28.6 + j67.5 26.6 – j69.1 18.0 + j1.74 33.3 40.7 12 52.9 –5 2170 27.7 + j71.6 28.6 – j71.2 16.6 + j2.92 33.9 40.8 12 55.3 –5 Max Output Power P3dB f (MHz) Zsource () Zin () Zload (2) () Gain (dB) (dBm) (W) D (%) AM/PM () 2110 26.5 + j66.6 26.3 – j66.3 17.2 + j0.31 30.6 41.5 14 52.3 –7 2140 28.6 + j67.5 26.1 – j68.6 17.4 + j1.43 31.3 41.6 14 53.6 –8 2170 27.7 + j71.6 28.0 – j70.2 18.6 + j0.54 31.5 41.7 15 54.5 –9 (1) Load impedance for optimum P1dB power. (2) Load impedance for optimum P3dB power. Zsource = Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output of the device at the package reference plane. Note: Measurement made on a per side basis. Table 11. Load Pull Performance — Maximum Efficiency Tuning VDD = 28 Vdc, IDQ1 = 16 mA, IDQ2 = 57 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle Max Drain Efficiency P1dB f (MHz) Zsource () Zin () Zload (1) () 2110 26.5 + j66.6 26.0 – j67.4 15.9 + j12.4 34.1 39.4 9 58.3 –5 2140 28.6 + j67.5 26.1 – j69.4 16.2 + j12.9 34.6 39.7 9 60.9 –6 2170 27.7 + j71.6 28.1 – j71.5 13.7 + j12.4 35.1 39.6 9 64.3 –8 Gain (dB) (dBm) (W) D (%) AM/PM () Max Drain Efficiency P3dB f (MHz) Zsource () Zin () Zload (2) () Gain (dB) (dBm) (W) D (%) AM/PM () 2110 26.5 + j66.6 25.7 – j67.3 16.2 + j12.1 32.0 40.5 11 60.0 –7 2140 28.6 + j67.5 25.6 – j69.4 14.7 + j12.9 32.7 40.4 11 61.8 –9 2170 27.7 + j71.6 27.4 – j71.4 14.2 + j13.7 33.2 40.2 10 63.5 –11 (1) Load impedance for optimum P1dB efficiency. (2) Load impedance for optimum P3dB efficiency. Zsource = Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output of the device at the package reference plane. Note: Measurement made on a per side basis. Input Load Pull Tuner and Test Circuit Output Load Pull Tuner and Test Circuit Device Under Test Zsource Zin Zload A2I20D020NR1 A2I20D020GNR1 RF Device Data Freescale Semiconductor, Inc. 9 P1dB -- TYPICAL LOAD PULL CONTOURS — 2140 MHz 20 20 39 15 E IMAGINARY () IMAGINARY () 15 39.5 40 10 40.5 5 P 0 44 60 10 E 46 58 48 56 5 54 P 52 50 0 40 –5 –10 –5 39.5 39 10 20 30 REAL () 40 –10 50 Figure 12. P1dB Load Pull Output Power Contours (dBm) 15 IMAGINARY () 30 REAL () 40 50 20 35 –2 34.5 E 15 34 10 33.5 5 33 P 0 32.5 –5 –10 10 20 Figure 13. P1dB Load Pull Efficiency Contours (%) IMAGINARY () 20 10 31.5 30 –8 –4 E –6 –4 5 P 0 –5 32 20 10 40 50 –10 10 20 REAL () 30 REAL () Figure 14. P1dB Load Pull Gain Contours (dB) Figure 15. P1dB Load Pull AM/PM Contours () NOTE: P = Maximum Output Power E = Maximum Drain Efficiency 40 50 Gain Drain Efficiency Linearity Output Power A2I20D020NR1 A2I20D020GNR1 10 RF Device Data Freescale Semiconductor, Inc. P3dB -- TYPICAL LOAD PULL CONTOURS — 2140 MHz 20 39 20 39.5 40 15 15 60 40.5 10 IMAGINARY () IMAGINARY () E 41 5 41.5 0 P –5 E 10 58 5 56 54 P 0 52 50 48 46 –5 –10 10 20 30 REAL () 40 50 –10 Figure 16. P3dB Load Pull Output Power Contours (dBm) 10 20 30 REAL () 40 50 Figure 17. P3dB Load Pull Efficiency Contours (%) 20 20 33 IMAGINARY () E 15 32.5 32 10 IMAGINARY () 15 31.5 5 31 P 0 30.5 –5 –10 –12 E –4 –10 5 P 0 –8 –6 –8 –5 30 29.5 10 –2 10 20 30 REAL () 40 50 Figure 18. P3dB Load Pull Gain Contours (dB) NOTE: –10 10 20 30 REAL () 40 50 Figure 19. P3dB Load Pull AM/PM Contours () P = Maximum Output Power E = Maximum Drain Efficiency Gain Drain Efficiency Linearity Output Power A2I20D020NR1 A2I20D020GNR1 RF Device Data Freescale Semiconductor, Inc. 11 PACKAGE DIMENSIONS A2I20D020NR1 A2I20D020GNR1 12 RF Device Data Freescale Semiconductor, Inc. A2I20D020NR1 A2I20D020GNR1 RF Device Data Freescale Semiconductor, Inc. 13 A2I20D020NR1 A2I20D020GNR1 14 RF Device Data Freescale Semiconductor, Inc. A2I20D020NR1 A2I20D020GNR1 RF Device Data Freescale Semiconductor, Inc. 15 A2I20D020NR1 A2I20D020GNR1 16 RF Device Data Freescale Semiconductor, Inc. A2I20D020NR1 A2I20D020GNR1 RF Device Data Freescale Semiconductor, Inc. 17 PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS Refer to the following resources to aid your design process. Application Notes AN1907: Solder Reflow Attach Method for High Power RF Devices in Over--Molded Plastic Packages AN1955: Thermal Measurement Methodology of RF Power Amplifiers AN1977: Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family AN1987: Quiescent Current Control for the RF Integrated Circuit Device Family Engineering Bulletins EB212: Using Data Sheet Impedances for RF LDMOS Devices Software Electromigration MTTF Calculator RF High Power Model .s2p File Development Tools Printed Circuit Boards To Download Resources Specific to a Given Part Number: 1. Go to http://www.nxp.com/RF 2. Search by part number 3. Click part number link 4. Choose the desired resource from the drop down menu REVISION HISTORY The following table summarizes revisions to this document. Revision Date 0 May 2016 Description Initial Release of Data Sheet A2I20D020NR1 A2I20D020GNR1 18 RF Device Data Freescale Semiconductor, Inc. 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All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. E 2016 Freescale Semiconductor, Inc. A2I20D020NR1 A2I20D020GNR1 Document Number: RF Device Data A2I20D020N Rev. 0, 5/2016Semiconductor, Inc. Freescale 19